CA1318358C - Digital radio frequency receiver - Google Patents

Abstract

ABSTRACT
DIGITAL RADIO FREQUENCY RECEIVER

A digital radio receiver is described. The digital receiver (100) of the present invention contemplates a digital radio receiver which operates on a received analog signal which has been converter to a digital form after preselection at the output of the antenna. The digital receiver (100) of the present invention comprises a preselector (106), a high-speed analog-to-digital (A/D) converter (108), a digitally implemented intermediate-frequency (IF) selectivity section (110) having an output signal at substantially baseband frequencies, and digital signal processor (DSP)circuit (120) performing demodulation and audio filtering. The radio architecture of the present invention is programmably adaptable to virtually every known modulation scheme and is particularly suitable for implementation on integrated circuits.

Description

-13~83~8 Digital Radio Frequency Receiver FELD OF THE ~VENTION

This invention relates eo the field of radio communications and specifically eo a radio frequency receiver which is substantially implemented with digit~
o s cilcuitry.

BACKGROIJND OF THE INVENTION

Conventional radio communications equipment is implemented primarily 10 with analog circui~y. The inherent characteristics of analog components limit the amountof signal processing possible. For example, the noise and gain characteristics of analog amplifiers lim~t the dynarnic range of the processed analog signal. In addition, analog information can not be readily stored in a manner which allows sophisticated signal processing.
The use of digital signal processing to replace operations previously perforrned using analog processing eliminates undesirable variations in those operations which may have resulted from external effects such as temperature, humidity, and aging on analog components. In addition, digital signa} processingtechniques offer flexibility m terms of programmable operating characteristics and 2 o features. For example, a ~igital intermediate frequency (IF~ integrated c~rcuit would be programrnable in terrns of its channel frequency, its sampling rate, and, to some extent, its filter response. A digital signal processor ~DSP), executing alternate stored programs, can perform dif~erent filtering and demodulation to implement completely differen~ types of radios. Also, the DSP may be used to introduce 2 5 advanced processing techniques such as adaptiYe equalization.
An additional advantage of a digital receiver structure is that the DSP and IF
circuitry carl be designed so that it can be "reversed" to perform the corresponding operations for a digitally implemented transmitter. For half-duplex operation, the circuitry might be switched so that it simply reverses "direction," while for 30 full-duplex operation two IF filters would be needed.

2 ~3~83~8 The primary technology contribution leading to the feasibility of a substantially digit~l receiver is a high-speed (20-100 MHz), high-resolution (10-12 bits) A/D converter. A secondary factor leading to the technical feasibility of a digital receiver structure is the high level of irltegration and high speeds attainable in o 5 VLSI IC implementations, ultimately permitting, for exarnple, a 4-pole/4-zero double-precision digital filter with a 40-lcHz sampling rate to beimplemented in apresent-day digital signal processor. The present invention combines these new technologies with improved techniques for front-end analog processing and digital lF filtenng to aGhieYe a feasible design for a substantially 10 digital receiver.
The receiver structure of the present invention permits a revolutionary change in the manufacturing technology and operating characteristics of mobile radios. Furthermore, this approach permits a radio to be built with a minimal number of parts, which a~ once reduces parts and manufacturing costs, while alsol 5 improving radio reliability and serviceabilty.

SUMMARY AND OBJECTS OF T~ INVENTI5N

In summary, the present invention contemplates an all digital radio receiver 2 o which operates on a received R.F signal which is converted to a digital form after prPselection at the output of an antenna. The receiver of the present inven~ion comprlses a preselector1 a high-speed analog-to-digital (A/D) conYerter, a digitally implemented inte~nediate-frequency (lF) selectivity section having an output signal at sl~bstantiaIly baseband frequencies, and general-purpose digital signal processor 2 5 (DSP) integrated circuits performing final selectivity or equalization, demodulation, and post-demodulation processing.
Accordingly it is an object of the present invention to provide a digitally implemented radio receiver.
It is another object of the present imention to provide a radio receiver 3 o structure which is readily adapted to receive a plurality of ~ansmission schemes.
It is yet another object of the present invention to provide a radio receiver structure which may be substantially implemented using integrated circuit techniques.
It is still another object of the presen~ invention to provide a digital receiver 3 5 IF filter design which opcrates at a relatively fast rate so as to reduce the resolution and step size demands on the A/D converter.

3 13~83~8 PRIEF DES~IION OF T~ DRAWINGS
Figure 1 is a block diagram showing the functions of the digital receiver of the present invention.
Figure 2 is a sche,,natic diagram of the front-end circuitry of the digital o 5 receiver of the present invention.
Figure 3 is a block diagram of the digital zero I.F. selectivity section of the present invention.
Figure 4a is a schematic and block diagrarn of ~he digital oscillator referenccd in Figure l.
lFigure 4b is a schematic diagram of a pseudorandom dither gerlerator compatible with the digital zero I.F. selectivity section of Figure 3.
Figure 5a is a block diagram of a desired "fast", narrowband lowpass filter.
Figure Sb is a bloclc diagr~n of a decomposed approxirnation to the fast lowpass f~llter of Figure Sa.
Figures 6a through 6d are frequency diagrarns detailing the characteristics of the fast lowpass filters of Figure S.
F:igure 7 is a schematic diagram of the second-order narrowband lowpass infinite-impulse-response (IIR) filter used in the decomposed"fast" lowpass fil~ers of Pigure Sb.
2 o Figure 8 is a schematic diagram of the second-order fimite-impulse-response (~FIR) filter with a notch at half the sampling rate used in the decomposed fastlowpass filters of Figure Sb.
Figures 9a through 9c are schematic diagrams of the time-division-multiplexed second-order lowpass IIR filter used in the time-division-multiplexed "slow" lowpass filters described in conjunction with Figure 3.
Figure l0 is a block diagram of the fifth-order lowpass FIR filter used to further reduce the sampling rate from 80 io 40 IcHz.
Figure 1 l is a block diagram of the fourth-order lowpass IIR filter used for final selectivity and passband equalization, pnor to demodulation.
Figure 12 is ~ block diagram of an FM demodulator implemented with a general purpose DSP.
Figures 13a through 13c are diagrams,detailing the principles of phasors in the context of the present invention.
Pigures 14a and 14b are flow diagrams detailing the operation of the background routine of the FM demodulator of the present invention.

~318;~8 Figures 13a through lSb are flow diagrams of the oper~tion of the scale roudne described in conjunction with Fi~ure lSa.
Figu~es 16a and 16b are flow diagrarns detai1ing the operation of -the r~maining portions of the digital demlodulator of the present invention.

o 5 DETALED DESCRIPTIVN OF T~ DRAWINGS
Figure ~ illustratçs thc ~unctions of a digital receiver, comprising three major operations. While the diagram shows no example of receiver diYersity, it will be obvious to one skilled in t~c art that various diversit,Y approaches could be applied for use in a receiver of the pr~sent invention. In particular, the "front-end" section 104, which is further detailed in Figure 2, interfaces an antenna 102, receiving an analog radio-~equency (R~:~ signal, to the digitally irnplementsd IF selectivitysection 110. The preselector 106 provides wideband fileering of the incoming signal, to prevent aliasing in the sllbsequçnt A/D conversion process. The A1D
block 108 includes the gain and sarnple-and-hold operations necessary for the digital processing of the present receiver stlucture.
The next major sestiQn, lF selectivity section 110, further detailed below in conjunction with Figure 3, proYides a quadrature local oscillator (I,O) 116 which generates a con plex exponential signal (quadrature signals sine and sosine). The frequency o~ this signal is selected by the system channel ~requency input "A" The 20 quadrature mixers 112 use digital multipliers to ~requency-shift the desired narrowband channel down to the ~ frequency of approximatly zero Hz. The higb-speed selecgivity section 114 includes several cascaded narrowband lowpass filter sections, which rernove undesired signals at higher frequencies from the desired signal which is centered near zero ~equency. rnis lowpass filtenng perrnits 2 5 gradual satnpling rate reduction from ~he high rates at the output of the A/D converter 108 to rates comparable to the channel bandwidth at the input to the "back-end"
section 120.
The "back-end" section 120 is used to "specialize" the general-purpose radio structure into one specifically tailored to a particular radio application, designated by 30 a system radio-type input "B". Its best implementation may comprise a general-purpose digital signal processor (DSP). The final selectivi~y section 124 prov;des any additional filtering needed pnor to demodulation of the radio signal in accordaslce with the ~pe of modulation and c~annel characteristics. For example, it may provide adaptive channel cqualization for a digital data communications 35 system. This filter section 124 also provides adjacent channel attenuation, and - ~ 31~358 passband equalization to compensate for imperfections m the charactenstics of the high-speed selectivity filters 114, resulting from the coarse coefficient quantization needed to implement multiplierless (lowpass) filters. The demodulation section 126 rnay be software-progralTlmed to irnplement many types of demodulation, lncluding 05 FM demodulation for voice and frequency-shift-keyed (FSK) data. The demodulated voice signal may be converted back to analog form, then amplified and played through a loudspeaker, as suggested by icons 121 Emd 1?,2. Alternatively, a digital voice rnessage may be stored in digital a digital memory 123 for later playback. In a data communications system (not shown), the demodulated data 10 symbols may be routed to a computer for further processing or to a cornpu~er terminal for immediate display. In addition, control inforrnation to implement automatic frequency tracking 128 may be generated in the "back-end" section 120.Finally, a clock-generaeion secti-on 118 is required eo control the input sampling rate of the A/D conversion as necessary for accurate down conversion, to operate the 15 digital circui~y in a regular fashion, and to control the output sampling rate, perhaps for synchronizing with subsequent systems. In the exemplary embodiment to be described here, the sampling rate fs is taken to be 20 MHz, and the band of frequencies to be received is cente~ed at approximately 875 MHz.
Figure 2 is a schematic diagram of the front end circuitry of the digital 2 o receiver of the present invention. This circuitry functions to digitize a selected band of radio frequency signals. The present invention provides that sampling is donedirectly at R.F. frequencies. However, wideband pre-selection is provided by R.F.
analog ~11ters plior to sampling. The function of the R.F. filters 202 and 206 is to provide selectivity to spurious responses. These spunous responses included the 25 image, half I.F. spurs, Able-Baker spurs, etc. as found in a conventional receiver front-end. In addition to these spurs, selectivity must be provided to frequencies which can be aliased by the sampling process. Maximum allowable bandwidth is lirnited to the IYyquis~ bandwidth (f5/:2, where f5 is the sampling rate), although pracdcal filters will sign~lcantly reduce this.
Use of a 2-pole and 5-pole filter as shown in Figure 2, each with bandwidths of approximately 4 MHz, will provide greater than 90 dB rejection to aliased frequencies when sampled at a 20 MHz rate. In addition to providing selectivity to signals entering antenna 224, filter 206 bandlirn~ts wideband noise entering the first sample and hold 208 generated by R.F. prearnplifier 204. This is 3 5 necessary to prevent aliasing of noise, thus effectively increasing the noise figure of the front-end 200. R.F. preamplifier 204 is used to amplify the R.F. signal to asufficient leve~ to provide the necessary signal-to-noise ratio needed for system 6 ~3~3~

sensitivity. Since different filters are needed for different bands, it is practical to include the R.F. amplifier 204 as part of the ~lltet structure (202 and 206~. The receiver of the present invention provides an R.F. amplifier 204 having a gain of approximately 28 dB and a noise figure of approx~ma~ely S dB.
05 Clock 212 a~nd sampling pulse generator 210 provide clock signals and sampling pulses to the flrst sample and hold 208, second sample and hold 220, the analog to digital converter 222, and the digital zero-D~ selcctivity section (not shown). Cloclc gèneration may be accomplished by a 20 MHz crystal osci}lator, which is widely available. A 40 MHz signal for use by the digital signal processor (not shown) is derived by doubling the 20 MHz signal by an analog doubling circuit.
The pulse generator 21Q is used to shape the 20 MHz clock signal (an approximate sinusoid) into very narrow pulses. The width of thc sampling puise depends on the highest frequeilcy band desired to be received. A pulse width of approximately 300 psec. will generate a "comb" of harmonics with approximately uniforrn amplitude to approximately 1 GHz. This is necessary for operation at the operating frequency of approximately 875 MHz of the receiver of the present invention. Pulse generation may be accomplished using a conventional step recovery diode and ringing circuit. A circuit of this type is described in a publication entitled Harmonic Generation Using Step Recovery Diodes and SRD modules, Hewlett Packard Application note #920, available from ~ewlett Packard Microwave Semiconductor Di~rision, 350 ~rimble Rd., San Jose~ Ca., 95131.
The band of signals arnplified and seleçted by blocks 202, 204, and 206 is sampled by the first sample and hold 208. This is analogous to down-converting in a conventional R.F. receiver. Although a flash analog-to-digital converter effectively samples the signal, practical converters have bandlimited inputs, ~hus requiring sampling prior to conversion. Also, to date, all known high resolution (>
10 bits), high speed converters utilize a two-step conversion process. This type of converter necessitates the use of a second sample and hold circuit 220.
Double sampling is necessary to over&ome the practical lirnitations of acquisition time, accuracy, and droop. The first sasnple and hold must acquire extremely fast~ in the range of 300 psec in the recei~er of the present invention. This requires the use of a small hold capacitor in order to charge the capacitor fromsample to sample to approximately the voltage of the input signal. The inability to completely charge in the sarnpling interval to the value of the input signal results in a mild filtering processing which can be considered rlegligible for narrowband signals typically used for land mobile communications. The use of a small hold capacitor in 7 ~L31~8 the first sample and hold ~sults in ~ droop rate unacceptable for use by a two-step ana~og to digital onvcrter. Also, s~ttlin~ time of ~ relatively simplc hold cucuit as can be usod by the fiIst sarnple and hold ITuy b5 inadequ~te for a tw~step converter.
For these reasons, a high accur~cy s~cond sample and hold 220 is uscd. Since the05 sigral has been effecti~ely down eonvcrtcd9 it is changing at a much slower ratc.
This allows the use of a larger acquisition time and largcr hold capacitor. Known tw~step converters rcquire the sample and hold to d~oop less than 1/2 the step size in significantly less than thc sampling pcriod ~typical~y less than 1/2 thc sampling penod).
lhe first sample and hold (208) may be implemented according to conventional techniques using a Schot~y diode bridge and a~ dual gatc MOS FET asthe buffer amplifier. The seeoad sample and hold may be ~:alizcd using a Scho~tky diode.bridgc, with additional back biasing to limlt droop in the hold mode. A high speed amplifier consis~ng of J-FETS in differential configuration as inputs and high 15 dynamic rallge bipolar followers se~vcs as a buffer amplifier.
Wideband amplifier 209 is necessa~y ~o further a nplify the signal in orde~ to overcome the quan~ization noisc of the ~alog to digital converter. The amplifier 209 is used to amplify a sampled signal; hence it mus~ be wideband. High dynamic range is also necessary to prevent alT plifier nonlinearities f~om distorting ~e signal.
20 ~he amplier 209 noise figure is dependent on the amount of "takeover" ~ain provided,~y R.F. amplifier 204 and overall noise requirements for sensitivity. AMotorola~HU'591 CAl V wideband amplifier is suitable ~r use as the wideband amplifier with the 800 MHz reccive~ of the present invention. An A/D converter structure similar to ~e ~pe descr~bcd herein is shown in an a~icle by Muto, Peetz, 2s and Rehner entitled Designing a l~bit, 20 Ms-Per-Secor~c~ Analog-to-Digital conYerter System, HE~E~T PACKARD JOURNAL, Vol 33, #11, pp. 9-29,. Nov 1~82.
According to the teachings of the present invention, a dither signal 218 is added to the sampled signal at combincr/isolator 214. The combinerlisolator helps 30 prcvent nonlineanties present in the wideband amplifier and dither source ~rom translating the low passed noise to other frcquencies. I he purposc of the dither 218 i5 to uniformly spread quantization noise of thc analog-to- digital converter. The uniform spreading of the noise floor over the Nyquist bandwidth prevents ~ntennodula~ion distor~on caused by quantizing frorn being an inherent problern, and 35 also allows signal recovcry below the Icast significant bit level, thus rcducing gain requir mcnts before the AID convertcr and easin~ thc problems caused by non-lineari~ in the stages precciing the conver~er. 'rhe di~er signal 218 must be 8 13-~ 8~3 added before the second sasnple and holt 220 if a two~step converter is used since the signal must be held constant during the conversion p~riod. The dither source218 can be realized by using an analog noise sou~ce such as a noisc diode. The general characteristics and advantages of dither signals are descnbed ~n a paper by 05 Schuchman, L., Dither Sfgnals and Their E~ec~ on Ql~antizanon Noise, I:EE~
TRANSACTIONS ON COMMUNICATIONS TEC~O~OGY, E~P- 162-165, Dec. 1964.
Noise added to the signal should be spectrally isolated from the informa~ion.
The sampling performed in the 800 MHz receiver of the present invention places the information approximately between 3 and 7 MHz. Low pass filter 216 prevents 10 noise ~rom being added to the information signal. Tlle receiver of the present invention is provided with a 5-pole elliptic filter with a 1.5 MHz cutoff fre~uency for low-pass ~llter 216. The average voltage level of the dither signal over the noise equivalent bandwidth of ~e low pass filter 216 should be greater dlar approx~mately 3 step sizes of the analog to digital converter. Care must be exercised to prevent ~he 15 dither signal from causing clipping at the A/D converter 222.
The analog-to-digital converter 222 converts the analog signal to a digital signal. The converter must be capable of accepting signals over the dynanuc environment of the intended receiver application. For the land mobile communications application, a minimum of 10 A/l:) bits is necessary, and theoretical 20 studies indicate the dynamie range provided by a 12-bit converter should be cornpasable wi~h all existing conventional land-mobile receivers. The two factors of prime importance of the analog to digital converter 222 are sampling speed and step size. The step size detern~nes the amount of gain necessary prior to the converter in order to take over the quantization noise floor. The larger the step si7e, the larger the 25 gain requirement. Large amounts of gain result in nonlinear e~fects prior to the conver~er. Conversion speed is also very important since this determ~nes the allowable bandwidth of the front-end fiiters, and also reduces the gain r~quirement by spreading the quantization noise over a larger bandwidth.
An analog to digital converter 222 satisfactory for use with the 800 hlHz 30 digital receiver of the psesent invention is a two-step l~bit converter with a step size of approximately 3 mV, which is capable of ~onverting at rates greater than ~0 MHz. According to the principles of the present invention, a front end gain of approximately ~4 dB is necessary to realiu a ~ost detection signal to noise ratio of approximately 10 dB in a receiver having a 30 kHz bandwidth when receiving a 0.335 ~v signal sampled at a 20 MHz rate. The large amount of gain necessary prior to converter 222 limits the nonlinear performance of the system. Intermodulation ratio (I~) is limited to approx~mately 65 dB which is somewhat less than that achievable 9 11 3~83~8 by convcn~onal rcceivsrs. It will be obv~ous to one of ordinary skill in the ~ that a reduction of the step size to approxi nately 200 ~V will allow an IMR ~ 80 dB to be achieved. This value is comparable with most existing conv~ntional 800 MHz receivers.
05 Referring now to Figure 3, a digital zero-IF selectivity section (DZISS) compatible with the praetice of the present invention is depicted in bloek diagram forrn. The digital zer~IF sel~tivity section is disposed between the front-end circuihy 200 of Figure 2 and the backend DSP 120 of Figure 1, and it operates toconvert the modulated digital RF signal output by front end 200 to the baseband signal processed by the backend DSP 120. The D~ISS 300 is çomprised of an in-phase mixer 304, a quadrature-phase mixer 306, a digital quadrature local oscillator (L0) 302 (providing an in-phasc L0 signal 309 and a quadrature phase L0 signal 311), two "fast" digital lowpass filters 308 and 310, two "slow" digital lowpass filters 312 and 313, and a clock source (not shown).
In the practice of the present invention identical digital information is applied to both the m-phase mixcr 304 and the quadrature-phase m~xer 306 at input por~s 303 and 307 respectively. Generally, ports 303 and 307 are not single lines, but are in fact multiple lines representing a multi-bit te.g., 10 or 12 bits) digital word. The actual length of the digital word used in any given appli~ ation is dependent upon 2 o many fac~ors, ~ncluding: the resolution required, the dynamic range regu~red and the frequency of sampling the received RF signal. For example, a word length of 12 bits is considered to have an acceptable performance in receiving a typical radio signal sampled at 20MHz.
Mi%ers 304 and 306 have as a second input quadrature L0 lines 309 and 311, respectively. As with the A/D output signal discussed above, the L0 signalsare not single connections, but are multi-blt discrete time representations of signals that are 90 degrees apart in phase (i.e~, sine and cosine waveforms). Mixers 304and 306 perform arithmetic multiplications of the A/D inpu~ word and the L0 word, rounding the result to form an output word that is applied ~rom the output ports of mixers 304 and 306 to the input ports of digital lowpass filters 308 and 310, respectively. The digital word lengths of the LO and mixer output signals may beselected to yield acceptable noise performance. As the digital word is lengthened, more quantization levels are available ~o represent the signals. The smaller quantization increments lead to improved noise perfonnance, as is well understood in the art. This quadrature mixing proccss described above is analogous to that performed in an analog "zero-lF', or direct conversion receiver.

~3~83 ~

However, the use of truly linear digital multipliers precludes second order rnixing of undesired signals to D.C., and other undes~rable effects, as occurs with analog direct conversion.05 The quadrature mixing performed by multipliers 3û4 and 306 acts tofrequency-translate the desired signal to a center frequency of approximately zcro Hz, where the amount of frequency translation maybe determ~ned by channel frequency con~rol 305. The resultant quadrature signal may then be lowpass filtered to remove out-of-band noise and undesired signals. In the preferred practice of the present invention, this selectivity is provided in two stages. The first stage is forrned by fast recursive digital filter sections 308 an~ 3l0. I)igital filters 308 and 310 are identical in structure and may be formed from a recursiv~ filter topology which will be described below in greater detail. The remaining selecti~ity is provided by "slower" recursive filters 312, and 313, respectively. lhis choice of architecture will be discussed in more detail below. E:ollowing the filtering process, the digital signals are output to a backend DSP 120 for furt31er processing.
Figure 4a is a schematic and block diagram of the digital oscillator described in conjunction with Figure 3. Recall that the function of the quadrature oscillator is to provide digitized, sampled versions of the cosine and sine waveforms utilized in 2 o the quadrature m~xing process. Implementation of the digital zero-IF selectivi~
section depends on the ability to generate accurate, stable digital representations of these waveforms. A class of digital oscillator realizations particularly suited to Ihe requirements of the present inYention is based on the concept of ROM ~read only memory) lookup. Consider the generation of a digital signal comprising samples of the complex sinusoid:
W(t) = ~2JtfCt where fc is the desired oscillator frequency.

According to conventional communications theory, 3 5 ~7~fCt _ cos2~fct + jsin2~fct, ~1 ~ 3~g~38 Thus the des~red cosine and sine wave~orms may be regarded as the real and imaginary parts, respectively, of the complex sinusiod waveform. The sampled version of e)2~fct is obtained by replacing the continuous time val~able t by the discrete time variable nT, where n is a counting integer (172,3, ...) and T is the sampling perlod, which equals l/fS - 1/sampling rate. This discrete time si~nal is then equivalent to:
w(n)= ei2~fc(nT) ROM lookup methods of generating this signal follow from making the frequency var~ab!e fc~ as well as the time vanable, discrete. If we let fc = kfS/2N
(where k and N are integers), then:

w(n) = e i2~kfs(nl~s3l2N - e j2~nk/2N

It can be seen that cosine and sine values for only 2N different phases need be generated. One method of generating these values, called direct ROM lookup, basically involves the use of E~OM table containing the 2N pairs of values (cosin~
2 o and sine), which is addressed by a register containing the integer nk (proportion to phase.) The phase register is incremented by the incremented by the value k (corresponding to the desired frequency fc) at each sample time tcorresponding to n). The frequency resolution obtained is ~f = f5/2~, wherein 2N distinct frequencies can be generated.
Depending on the application, the direct RS:)M look-up technique may involve large amounts of ROM. The ROM size may be reduced somewhat by taking advantage of the symmetric properties of cosine and sine waveforms. Such pFoperties allow the number of table entnes to be reduced from 2N, to 2N/8, pairs of numbers. Even with this reduction the ROM size may still be excessive~ In such cases, a technique called Factored ROM lookup may be employed to further reduce ROM size~
The digital local oscillator 400 of the present invention uses the factored ROM look-up technique utilizing the fact that the unit magnitudc phasor can be broken into a cotnplex product of l'coarse" and "fine" phasors. Thus, the unit magnitude phasor e)0 can be represented dividing the signal into eJ0c 0 ~ f~
Therefore, ~he unit magnitude phasor can be reali~ed by halring separa~

1 2 ~ 3 ~ 8 coarse value phasors and ~me-value phas~rs stored in ROM which are multiplied together to get thediscrete time sine and cosine values required for the quadrature mixers. The advantage of this ~actorization is that the amount of RVM necessa~y to store the coarse-value and fine value phasors is greatly reduced from that required 05 for the direct R(:)M look-up approach. The expense paid for this ROM size reduction is the introduction of circui~y to perform the c omplex multiplica~ion of coarse and fine phasors. Generally, a complex multiplication can be ~mplcmented with four multipliers and two adders. By proper selection of the fine-value phasor, and recalling that the cosine of a small angle c~n be appro7umated by one, the ROM
10 for the cosine fine-value phasor can be eliminated. Further, by approximating the small angle cosine values as one, two multipliers can be eliminated from the multiplication structure required to generate a complex product. This results in both a cost and siæ savings in the ~tored ROM implementation.
Referring still to Figure 4a, the digital quadrature local oscillator 400, as 15 implemented using a factored-ROM approach, is depicted in block diagram forrn.
Frequency information, in the form of an N bit binary number proportional to thedesired ~requency, within the band sampled by the A/D converter, is loaded into the channel frequency latch 40~. Channel frequency latch 402 may be realized in manydifferent forms. For example, assuming that N=20, five cascaded 74LSl75's 20 (Quad D flip-flops~, manufactured by Motorola, Inc., and others, provide an accepeable implementation. Those skilled in the art will appreciate that channelfrequency latch 402 may be loaded by various means. For example, in a single frequency radio the channel frequency latch could be permanently loaded with a single binary number. For multiple frequcncy radios, channel frequency latch 402 2 5 could be loaded from an EPROM or ROM look-up table or else calculated by and latched from a microprocessor.
The output of channel frequency latch 402 is coupled to a binary summer 404. It will be understood by those skilled in the art that in the following discussion of digital quadrature local oscillator 400 all coupling lines ~n between the functional 30 blocks are in fact multi-bit binary words and not single connections. The output of adder 404 is coupled to phase accumulator 406. Phase accumulator 406 can be implemented as an N-bit binary latch which is used to hold the address of the next location of ROM to be addressed. Thus, the output of phase accumulator 406 may be di~ectly coupled to cosine coarse-~alue ROM 418, sine coarse-value ROM 416, 35 and sine ffne-value ROM 414 trecall that fine-Yalue cosine ROM is not required, as it is being approximated by one). Further, the ou~put of phase accumulator 406 is fed back into summer 404 to be added (modulo 2N) to the binary number representing 13 ~L3183~8 the channel frequency information located in the channel frequency latch 402. The outpu~ of phase accurnulator 406 is updated once everS~ clock pulse, which is generally the sampling frequency The result of this binary addition is that phase accurmulator 406 is holding the binary sum (proportional to phase) of the last addrzss O S plus a binary vector contained in the channel frequency latch. This number indica~es the next address to be requ~red to create the quadrature local oscillator signals cos 2~nT and sin 2~fcn7'.
In the preferred embodiment, the ROM siz~ may be reduced, or equivalently, the frequency resolution may be improved without incre2sing the ROM
size, by adding a digital dither signal to the output of phase accumulator 406 and trunCatiDg the result prior to addressing the ROM tables. The frequency resolution of the local oscillator is def~m~ by the data path width (N) of the phase accumulator and the sampling rate fs required. The most straight-forward metho~ of increasing frequency resolution is to add more bits to the phase accumulator and increase the size of the ROM tables. However this can be an expensive solution since the E~OMmust double in size for each bit added to the phase accumulator. Another option would be to add bits to the phase accumulator but Iruncate the additional bits before performing the ROM look-up. This introduces severe phase rounding and causes spurs in the local oscillator output. In order to avoid these spurs a IQW level dither 2 o signal is added to the accumulator output before truncation.
According to the principles of the present invention, the frequency resolution of the digital oscillator may be enhanced, without increasing ROM si7e and without introducing SpUTS in the output, by adding a binary dither signal to the output of phase accumulator 406 before truncating. To accomplish this, digital 2 5 oscillator 400 is provided with an L-bit dither source 408, which generates an L-bit - wide, uniform probability density, pseudorandom "white noise" signal. Oither source 408 is clocked at the sampling ~requency fs~ so as to provide a new L-bitdither word for every phase word output from phase accumulator 406. An N-bit dither word is formed by appending M = N - L leading zeroes to the L-bit dither word outpu~ from dither source 40B. I~his composi~e N-bit dither signal is added to the N-bit output of phase accumulator 406 by N-bit binary adder 410, in Modulo 2N
fashion. The sum output of adder 410 is then truncated to M bits (truncation notshown). In practice this truncation process is achieved by simply ignonng the least significant bits produced at the output of digital adder 410. The truncation operation itself allows for reduced ROM size.
Quantization or trunca~ion of the binary phase word produces distortion or noise in the generated sine and cosine waveforms. Since the phase is a periodic 1 4 1 3 ~ ~ 3 5 ~

function (sawtoo~h), the noise produced by quanti7ation would also be periodic unless it is randomi~ed somehow. Periodic noise would result in discrete "spurs" in the oscillator output spectrum which are undesirable in rnost applications if their level exceeds some threshold, Addition of the dither signal prior ~o phase o 5 quantization randomizes the phase noise, resulting in a more desirable white noise spectrurn at the output, The binaly phase word is represented by a binary word of N
bits, The dither signal comprises a pseudo-random binary word of L bits which issurnrned with the N bit phase word, The pr~ess results in a binary word ~J - L ~M bits, This binary word is then truncaîed to a binary phase word of M bits which 10 is relatively free of the spurious signals described above, The effect of phase quantization on oscillator OUtpltt noise can be shown by the following analysis. The desired oscillator output is described by the following equation:

wtn) = ei27~fcnT = ej0(n) If the phase angle is quantized with error a(n), the actual output is descnbed as follows:
w(n) = ej[0(n)+a(n~]
The error intrc~uced is:

E(n) = w~n) - w(n) = ei~0(n)~a(n)] - el0(n) ei0(n) [aJ~(n) l]

For the case of interest where ~(n) is very small (~ a(n) can be approxirnated by 1 +ja(n), thus yielding:

E(n) = ~0(n) The spectrum of E(n) can be seen as simply a frequency translation (and unimportant scaling by j) of the spectmm of the phase quantization noise a(n), Thus if ~(n) is random or "white", so is E(n), Furtherrnore, the power of E(n) equals the power of a(n), allowing the output noise level created by the phase noise to be easily 35 estin~ted.
ChGosing the power level of the dither signal involves a tradeoff between noise whitening effçct and output noise power level. As the dither power is ~5 ~31~

increased (by increasing the numSer of bits, L, in the dither signal), the noisebecomes more whitened, but the total phase noise power incr~ases as well. It can be shown tha~ if the dither signal exhibits a uniform probability density, the choice of L = N~M results in the preferrcd level of dither power since it 05 represents the srrlallest dither signal necessary to cornpletely whiten the phase quantization noise. Thus, in the preferred implementation, the number of dither bits L equals the number of bits discarded in the truncation process. It may be notedthat dither signals exhibiting other than uniforrn probability density may be u~ilized.
However, a uniform density is preferred as it is the most easily generated. With10 L = N-M, the variance (power3 of the phase noise is equal to 2 times the equivalent phase variance of the dither signal. Given a desired frequency resolution, determ~ned by N and fs then L and M, and hence the required ROM size, are detern~ned by the allowable level of white noise at the oscillator output.
As an ex mple, with f5 a 2(1 MHz~ and N - 2û bits, the frequency resolution is 1~.07 Hz. Truncating to M=17 bits ~to reduce ROM size by a factor of 8) without dither creates spurs in the oscillator output, which for one particular frequency are 98 dB below the level of the desired signal. Addition of a 3-bit dither signal prior to truncation whitens the error signal, elim~nating the spurs. According to the principlcs of the present invention, the frequency 2 o resolution of the digital oscillator, for a given level of output noise, can be increased indefinitely by simply adding more bits to the frequency and phase latches, and to the dither signal. The ROM size, detenn~ned by M, remains constant. The M-bit binary word retained after truncation is coupled to the ROM address latch 412, whose output is coupled to ROM's 418, 416, and 414. Upon receiving an address, ROM's 418, 416, and 414 output the digital binary ~ord located at the received address on their respective output ports. The digital quadrature signals are ~hen arithmetically generated from the three bina~y numbers.
As stated previously, the output signals of ROM 416, and 418 are binary numbers proportional to the cosine and sine of the coarse phase. l~e output signal of ROM 414 is a binary number proportional to the sme of the fine phase. In order to minimize the error in the fine cosine approximation, the fine phase values used are the values centered around the positive axis The output of ROM address latch 412 lB 13~8358 is an M bit number that is divided into a M~ bit coarse address and an Mf bit fine addre~s where M = Mc + Mf. The coa~e phase is 27~(Pc ~ 1/23 /2Mc, where Pc is the integer corres~nding to the Mc blt coarse add~ess. The fime phase is 2~(pf-2Mf-1)12~, where Pf is the integer correspondin~ to the Mf bit fine address. For05 example, if Mc = 10 and Mf a 7, the ROM table en~ies may be sonfigured as shown below in Tables I and 2.

Address (Pc) I Contents of I Contents of coarse CC)S RO~ I coarse S:~l ROM

o I cos 27~o(l)12~ IN 2~-(1)/211 1 cos 2~r~(3)/~11 1 s~ 2~ 3)/211 1 2 I COS 2~-(5)/211 I SIN ~ (5)/~ll 1 3 I COS 21~-(7)/2ll I S~ 27C-(7)/2ll 1 4 I COS 2~(9)/211 I SIN 27~-~9~/2ll I l I I
;022 ~ )S 27~(~045)/2ll I SIN 2~(2045)12 2 o 1 1023 I COS ~(2347)l21 1 I SlN 27~(2047)/2l 1 __ , _ _ _ _ _ Address OEf) I Contentsof . fine SIN ROM
I _ --_ I ata~dr~f' I
I
O I SIN 2~ 64)1217 SIN 2~ 3)12l7 2 I S~ ~(-62~l217 3 I Sl:N 2J~ (-61)/217 ;26 I SI~ 2~(62)/217 1~7 I S~ ~(63)1217 17 13183~8 To generate the cosine wave~orm (i.e., the real component of the compl~x wave~orrn), the outputs of sine coarse-value ROM 41~ and sine fine-va~ue ROM 414are first muldplied in multiplier 426. The output of multiplier 426 is fed to summ~ng circuit 440 where it is subtracted (2's complement form) from ~he output of cosine 05 coarse-value RC)M 416. This arithmetic process yields the cosine~value which is output on port 441 and coupled to quadrature mixer 304 of Figure 3. To generate the sine values of the digital quadrature L0 the outputs oF the rosine coarse-Yalue ROM 416 and sine fine value RO2~ 414 are multiplied in multiplier 428. The output of multiplier 428 is fed to a surnming c~rcuit 442 where it is surnmed wilh the output of sine coarse-value ROM 418. Surnm~ng circuit 442 outputs Yia connection 443 the discrete time sine value digital word which is coupled to ~uadrature mixer 306 of Figure 3. Therefore, since the discrete time values of the sme and cosine signals are calculated mathematically, perfect 90 phase control is achieved using mini~r~l ROM
space. Latches 420, 422, 424, 434 and 438 provide pipelining which facilitates high operating speed of the digital oscillator. Delays 430 and 436 are provided to equalize ~he delays of the various signal paths.
The factored ROM LO reduces the ROM area while maintaining acceptable frequency resolution. For example, to implement a digital quadratur~ LO that operates at 20 MHz, the coarse-value ROM's 416, 418 could each be implemented in a 1024 x lS ROM and the ~ne-value sine ROM 414 could be implemented in a 128 X 8 ROM. This would result in frequency resolution of approximately 20 Hz using approximately 34,000 bits of lROM. The factored-ROM con~lguration is preferred for operation at high sarnpling rates, since, except for the phase accumulator, there is no circuitry connected in a feedback manner. This allows the 2 5 rest of the LC) CilCUih~l (especially multipliers 426 and 428, which represent the main speed bottleneck) to be pipelined to achieve a very high operating rate. Pipelining would consist of introducing latches at certain critical points, such as within the multipliers themselves, as is well understood in the art. Thus, a factored-ROM LO
is described which outputs discrete time digital quadrature signals which exhibit a selected fr~quency.
A digital adder suitable for use with the apparatus of ~he present invention may be of a type cons~ucted with several 74LS181 4-bit arithmetic logic unit devices, connected in parallel. These devices are shown and described in a data manual entitled "Motorola Schot~y lTL Data Book", avaliable from Motorola, Inc.,Box 2092 Phoenix, Anzona, 85036. ROMs 418t 416 and 414 may be formed by a varie~ of well Icnown ROM devices such as a 82LS181 available from Signetics Corporation, 811 E. Argues Avenue, P.O. Box 3409, Sunnyvale, Calif. 94088, and ~ ~8~8 described in the "Sign~tics Bipolal Memory Data Manual", 1984. Both multiplier 426 and 428 may be realized as, for example, an MPY016K manufactured by TRW, Inc., TRW Electronic Components Group, P.O. E~ox 2472, LaJollal Ca. 9203~.
The amoun~ of coarse-value RC3M required can be further reduced by taking 05 advantage of syrnrnetries in the cosine and sine wave fonns, and thereby stor~ng only the values of the unit magnitude phasor residing in the ~Irst octant (i.e., the first 45) of the phasor unit circle. Those sk~lled in the art will appreciate that the unit magnitude phasor represents sine or cosine values rotating through 360. Vue to the symmetrical nature of sinusoidal waveforms, the valucs of the cosine and sine waveforms over the f~t octant of the unit circle are identical to the values of these waveforrns over any other octant, except fo~ possible sign changes and reversal of roles (i.e., sine becornes cosine and vice versa). Therefore, the only coarse-value phasors ~hat are required are tliose in the fiIst ~tant provided there is an indicator of which octant ~he phasor is currendy residing, and there is c~rcuitry present to negate ~i.e., change sign) andlor exchange the outputs of coarse-cosine ROM 416 and coarse-sine ROM 418 accordi~g to the current octant. A~s octant indicator is readily implemented using three binary bits of the ROM address. For example, the three most-signiflcant-bits ~MSB's) could be used to indicate the octant, and the rema~ning bits used to address the RC)M for the coarse-valued phasor.
2 o Figure 4b ;s a schematic diagram of an exarnple of a type of digital dither generator compatible with the digital oscillator of the present invention. A digital dither signal can bc generated by any of several well-known pseudorandom sequence generation techni~ues. One ~pe of dither, or random number generator isshown and described in a paper by G. I. Donov, A ~figh-Speed Random-Number Cenera~or, RADIO ELECTRoNIcs AND COMMUNICATlON-sYSTEMS, Vol. 25 No.4, pp. 88-90, 1982.
Referring now to Figure 4b, a feedback shift register pseudorandom sequence generator which may be advantageously employed in tne practice of the present invention is shown in schema~ic forrn. The sequence generator of Figure 4b is used to provide an L-bit digital dither signal to the binary adder 410 of Figure 4a. The dither generator 408 includes an R-bit shift register 460 which may be foz7TIed of a plu~ality of fli~nops 4S4 through 499 which are connected in a cascade fashion. In the preferred practice of the present invention, a parallel 3-bit dither signal is tapped from the shift register at the ou.tputs of flip-flops 478~ 491 and 499 3 5 respectively. The inputs to an E~clusive-Or gate 462 are coupled to the outputs of flip-flops 464, 493, 498 and 499. The output of Exclusive-C)r gate 462 is coupled to the input of flip-flop 464. The shift register produces a 3-bit pseudo-random 19 13183~

dither signal which is added to the output of the phase accumulator 406 of Figure 4a. The flip-flops 464-499 and the ~xclusive-C)r gate 462 as well as the other de~ices used in the practice of the present inYention may be any of several wellknown logic devices; however, hi~h s~eed TTL. devices arc particularly wcll adapted 0 5 for the practice of the prcsent invention. Implementations employing other logic families will also be obvious to one of ordinary skill in the~ art. The dither generator of Figure 4b is set fossh as an exasrlple of one ~pe of digital dither generator which pe~fonns satisfactorily with the digital oscilla~or of the present invention. It would be obvious to one skilled in the art that many other digital dither generators could also be advantageously employed, provided the digital dither generator provides a pseudorandom sequence of L-bit numbers whose periodl is at least as long as 2N
samples, and whose probability density is uniform, in order for the phase noise produced by truncation to be "whitened".
As shown in Figure 3, the ~ntermediate-frequency (~:) fiiter section accepts data from the A/D converter at the rate of 20M samples/sec, mixes the received signal to dc (the zero IF frequency3, lowpass filters the received signal to extract the desired signal, and sends the signal to the backend 120 of Figure l at a (drastically) reduced sampling rate. In the preferred implementation~ the lowpass filtering and sample-rate reduction are not separate operations; instead, the sampling rate isgradually reduced between filter sections, as undesired signals (which could cause aliasing if not removed) are filtered out. The only filtering section which operates at the input sampl~ng rate (fS=20 MHz in the exemplary embodiment dPscribed here) is the f*st section. The only other circuitry which operates at that rate are the quadrature local oscillator (LO) and mixers. Thus i~ is this high-speed circuitry which sets an upper limit on the overall operational speed of the digital zero-IF
selectivity secdon. High-speed operation is very impor~ant to ths digital receiver of the present invention, to minim~ze intermodulation problems occurring with the front-end sample-and-hold and A/D converter and to allow a sufficiently widebandsignal to be accepted.
Figure Sa is a block diagram of the "fast", na~owband lowpass filters 308 and 3l0 of Figure 3. The quadrature local oscillator 302 and mixers 304 and 306 are non-feedback eircuits (primarily ROMs and multipliers) which are amenable topipelining or other forrns of parallelism to insrease their speed. However, because the lowpass filter sections 308, 310 are implemented as recursive (infinite impulse response) fil~ers, they cannot be pipelined to increase their speed. Their speed is deterrnined by the maximum delay around a closed tfeedback) path. For ~he lowpass filter implementation of the present invention, this pa~h includes two digital 13~3~

adders and one latch. It is this path which limits the A/D sampling rate and, therefore, potentially limits the overall performance of a digi~ receiver. Because of problems in at~air~ing shis very high speed the f;lteY was designed by interleaving two I~MHz l'rL ~ilters. The aliasing problems that would orclinanly be associated with o s using a lower sampling rate are alleviated by adding zeroes near the unwanted filter poles.
The "Fast" lowpass section 546 of Figure Sa is decomposed into two half-speed sections plus a combil~ing filter, as is shown in Figure Sb. This modification ~erm~ts the digisal IF section to operate at twicc the speed that would 10 otherwise be possible, and potentially allows improved p~rforrnance of the digital receiver of the present invention. The "decomposed" filter of the present invention is shown in conjunction wid~ Figures 3 and ~. Other filter decomposition techniques have been discussed, ~or example, in a paper, M. Bellanger, G. BQnnerott and M.
Coudreuse, Digital Filtering ~y Polyphasc Network: Applica~ion to Sample-Rate 15 Alteration and FilterBanks. EEE TRANSACIIONS ON ACOUSTICS, SPEECH, AND
SlGNAL PROCESS~G, Vol. ASSP-24, No. 2, April 1976.
The combining filter 554 is a nonrecursive filter. The combining filter, which is shown in greater detail in Figure 8, uses two zeros at fS/2 (z = -1) to cancel the poles introduced by the decomposi~ion. Such a filter can be implemented with 20 only adders and lasches (i.e., without multipliers), and so adds minimal hardware.
Note that although decomposition requires additional hardware, it norninally increases power consumption ~with a CMOS implementatior~), since two half-speed circuits require approximately the same power as a single full-speed circuit.
~ignoring the addi~onal power of the combining filter.
Figure 6 illus~r2tes Ihe decornposition process in detail with several magnitude plots. In particular, Figure 6a shows the response of the original version of the first two-pole section, for an input sampling rate fs of 20 hIHz. Figure 6b shows the "decomposed" characteristic which results from two 10-MHz sections, while Figure 6c shows the response of the subsequent "combining" fil~er. Finally, Figure 6d shows the ~omposite (i.e., cascade) of Figure 6b and Figure 6c, which is virtually indistinguishable from Figure 6a, except for ~he "notch" at 10 MHz (which results from the two zeros at fs 12, which cancel the two nearby poles).

The decomposed filter can be represented as follows:

y(n)= ~: y(n-i)hd(i)~x(n) i =l ~1 131~3~8 where x and y are complex filter inputs and outputs, respectively (i.e., they have both a real pa~t and an imaginary pa~t). Also, hd are th~ decomposed filter polynomial coef~lcients, and ND = 2 is the order of the original full-speed filter.
Since the desomposed 2~MHz filter is expressed in terms of ~-2 (as will be shown 5 in the next s~tion), it can be implemented in t~rns of a 10-MHz circuit where~n:
hd (i ) = hh (i /2), i even 0, i odd where hh are the original high speed coefficients.

15 Then the decimating f;lter can be reexpressed as:

y(n)= ~; y(n-i)hh(i/2)+x(n) i =2 2 o step 2 The change of var~ables i fi 2; simplifies this sunuTtation to:
ND

y (n ) = ~; y (n -2j ) hh (i ) + x (n) j _l From this formulation, decimating-filter inputs x and outputs y can be decomposed into two s~eams, as shown in Figure Sa:

x (Y)(m ) = ~ (2m + y ) 30y (Y~(m ) = y (2m +y) where:
y = mod(n, 2) %0 {~,1 }
Substituting n fi 2m + 1 in the above decirnating-filter sumnLation yields:
ND

y (n ) - ~ y (2m -2j +1) bh (j ) + x (2m + y) j=l ~ ~ 3~$3~
Finally, the two decomposed decim~tin$ filters ( y = 0,1) may be represented as:
N~
y (y)(m ) = ~ y (Y)(m j ) hh (i) + x (Y)(m ) j --1 Assume that ~he desired filter has a pole z - zp. Then the colTesponding filter character~stic rnay be represerlted as:
H = (1 - zp z~

If this pole is "repeated" 180 away, the following characteristic is obtained:

H ' = [~1 zp z ~ zp e iJ~ Z -l)~ -1 = [(1 Zp Z ~ zp z -1)]-1 = (1_Zp2Z-2~-1 Since the resulting characteristic is in terms Of z ~2, it can be decomposed (as was shown in the previous section) into ~vo hal~-speed fil~ers, each with pole z 2 = zp2 2 5 The lowpass filter sections in the digital zero-IF selectivity implementation of the present invention is realized using the following form, which is writ~en in terms of coefficients a and b, where b = ca . ~or a pole-pair zp, zp*, vhere:

zp = (l-d )eiq ~d~ q 1 the coefficients are:
a @ 2d alld b =d2+q2 For the half-speed filters, the pole-pairs are zp2 and (zp2)*, Since zp2=[(l-d)ejq]2 @ (1-2d ) e j2q 23 ~31~8 Then the coemcients for the hal~-speed filt~r may be obtalned m terms of those ~or ~he full-speed case by analogy to the full~speed case:
a ' = 2(2~ ) =22 5 and b ' = (2d )~ ~ (2q)2 =4~d2+q2) = 4b This design is illustrated in Figure Sb. A second-order [IR filter is described in a paper, Agarwal, A.C., Burrus C.S., New Recursive D~git~l ~ilter Strucfure3 Having Very Low Sensitivity and Roundoff Noise, EEE TRANSACTIONS ON
CIRCUITS AN~ SYS1EMS, VO1. CAS-27, No. 12, Dec. 1975. The filter structure II
proposed by Agarwal and Burrus has been modified for minimum delay around all 15 feedback loops for the purposes of the present invention. Ihe filter structure of the present invention is illustrated ~n Fi~ure 7.
All digital filter struct~ues are made up of basically the same ~ee CQmpOnentS:
adders, multipliers, and delay circuits (generally latches or RAM). The factors affecting the performance of a digital filter all have to do with the ~act that the various 2 parameters of the filters are quantized, that is, they have finite precision rather ~han the infir~ite precision available in analog filters. The fimite precision of a digital filter basically gives rise to three major performance effects that must be con~rolled in any ~mplemen~ation of a digital filter.
Coefficient roundoff is one of these effects. The constant valued coefficients 25 found in a digital filter determine its frequency response. The result of rounding these coefficients so that they may be represented digitally in a finite number of bits causes a perrnanent, predictable change in the filter response. This is analogous to changing the RLC values in an analog ~ er; however, digital filters do not suffer the detriment of temperature vanations as in analog filters. Generally, the higher Q of 30 the filter ~i.e. natrow bandwidth compared to the sampling rate) the more the frequency response is distorted by coefficient rounding, unless special structures are employed. Judicious selection of the filter structure is of key importance in light of the fact that IF filters are generally ex~emely narrow band, or highQ filters.
Round-off noise is another of the performance characteristics that must be 3 5 conttolled in a digital filter. Data cntering a digital filter has been rounded to a finite number of bits, and it is almost always necessary to pcrform additional toundings a~

24 ~3~8~

certain points w~thin the filter. Such rounding operations create an error or noise si~al in the digit~ lter. For example, if th~ digital word length used in a filter is 16 bits and the coefficients are represented in 10 bits each mu}tiplication operation would create a 2S bit product, which must be rounded to 16 bits before the result o 5 may be put back into memory.
The last major effect that is controlled in a digital fi~.ter is thç overflow level.
The fact that data samples are represented in a fillite m~mber of bits means that there is a maximum allowable absolute value associated withl every node in the filter which, if exceeded, results in an overflow phenomenon (generally wrap-around if 2's complement binary arithrnetic is used). This largest allowed data value, coupled with the level of roundoff noise descr~bed previously, determines the dynan~c range of the filter.
Several c~nYentional structures are available to implement digital filters. A
straight fo~vard design approach is to cascade sections of ~lrst and second order direct-forrn filters until the desired filter order is achieved The advantages of this melhod are its simplici~, regulari~, and the ease of actual filter design However, the conventional approach also suffers from rnany detrisnents mostly stemming from the fact that high precision (for example 16 bit~ filter coefficient representation is required to implement a narrowband filter This necessitates highly complex 2 o multiplications ~for exarrlple 1~ o 20 bits) be performed in the feedback paths of the filter sections. The multiplications place severe speed and time limitations on the operation of the filters. Further, pipelining, a cornmon technique used to speed logic circuits, cannot be employed in geedback loops Las~ly, high precision, high speed multipliers consume tremendous amounts of power Referring now to Figure 7, a digital lowpass filter section 700 is depicted in block diagram fonn The filter employed in ~e DZISS is a recursive filter (i e., the output signal is îed back, scaled, and summed at strategic points in th~ filter structure) having a nalTow bandwidth and optimized for high-speed and low-sensitivity to the previously described detrimental effects of parameter 3 0 quantization on digital filters The second-order narrowband lowpass infinite-impulse response (IIR) filter of Figure 7 is used in the deeomposed "fast"
lowpass filter of Figure Sb, which operates at the speed of the A/D converter Decomposition is useful in attaining this high operational speed, bu~ requires additional hardware: tWO second-order IIR sections instead of one, and a second-order FIR sec~on which would not otheruise be needed.
The digital low pass filter 700 provides the function depicted by the function blocks 550 and 552 of Figure Sb The digital lowpass filter 700 consists of four 25 ~318~

digital adders (2's complement) 704, 708, 712, and 716, two digital delays or latches 710 and 718, and twc binary shi~ters 706 and 714. As mentioned previously in the discussion of the digital quadrature local oscillator 400, the individualconnections of lowpass filters 308, 310, and 312, and 313, as deseribed in Figure O 5 3, are multi-bit digital words and not single electrical lines.
The input signal to ~e digital ~llter 700 is applied to a non-inver~ng input 702of the digital adder 704. A second inverting input to the digital adder 70J, is taken from digital delay 718 which is fed back from the output 720 vf the filter circuit The difference (2's complement) result of digital adder 704 is next applied to the input of ~ain element 706 which presents the shifted first sum signal as one input of digital adder 708.
Bit shifter 706 shifts all bits of the data word outpuned from digital adder 70~ to the right ~i.e., toward the least significant bit) by Nc bits, effecting multiplication by a coefficient c equal to 2-NC. This bit shift may be implemented by an appropriate routing of the data lines from digital ladder 704 to adder 708. Thus, high operating speed of digital filter section 700 is facilitated, since there is no time delay associated with bit shifter 706, as there would be in a coefficient multiplication implemented by a conventional muldplier c~rcuit.
Digital adder 708 adds to the shi~ted first sum signal the last output of digital 2 o adder 708 as hel~ in delay 710. Further, the last or previous output of digital adder 708 is applied to digital adder 712. A second inverted input to digital adder 712 is taken ~rom digital delay 718 which, as previously mentioned, is taken from the output 720 of the digital filter. The result of digital adder 712 is applied to bit shifter 714 which is coupled to digital adder 716. Bit shifter 714 shifts all bits of the data word outputted frolh digital adder 712 to the right by Na bits, effecting multiplication by a coefficient a equal to 2~Na. Bit shifter 714 also facilitates high operating speed since no ~ime delay is incurred. The parame~ers Mc and Na associated with bit shifters 706 and 714 respectively, control the frequency response of digital filter section 700, and may be chosen to yield the response appropriate to the intended application, as shown by the previous analysis. Digital adder 716 adds the second shifted sum signal to the previous output of 716 as held in delay 718.
The output of delay 718 is also the output of the digital lowpass filter section 700 and represents a band-limited representation of the input signal 702 that was previously appli~d to the input of summing circuit 704.
3 s Figure 8 is a block diagram of the second-order combining finite-impulse.response (F~R) filter with a notch at half the sampling rate used in the decomposed fast lowpass filters of Figurc Sb. The input 802 to filter 800 is 13~3~
2~

coupled to the output 720 of filter 700, as pictured in Figure Sb. According to Figure 8, the digital filter 800 compr~ses digihl shifters 8~, 8C~6, ~nd 808 coupled to digital delays 810 and 814 and digital surnrners 812 and 816, respectively. The digital shifters 804, 806, ~d 808 use gains of 1/4, 112, and 1/4, ~espectively, to 05 implement a filter with two zeros on the unit c~cle, at half the sampling frequency.
TSlese digital shifters perfo~m right shifting of the input 802 by 2, 1, and ~ bits, respectively. Since such "bit shifting" may be implemented by routing the w~nng conneetions m the appropriate rnanner, these ga~ll operations consume no actual time and require no actual hardware. A first partiai sum is formed in adder 812 using the 10 scaled output sf gain element 806 as the first input and the previous, or last, scaled output of gain element B04 as the second input, obtained from delay element 810.Sirnilarly, the output 81B is obta~ned as the second partial sum formed in adder 816 using the scaled output of gain element 808 as the first input and the previous, or last, first partial sum of adder 812 as the second input, obtained from delay element 15 814. The transfer function of this filter may be written:

H(z) - Y(z) / X(z) = ~1/4)E1 + z~l (2 + z-l)]

To compute an output, this FIR ~llter needs only to perform one addition and ODe latch operation, compared with two additions and one latch operation in the IIR
sections, so that the FIR combining filter easily operates at the full input sampling 25 rate (20-MHz). An alternative design would allow the adder to run at a lower sampling rate by the use of additional control circuitry. This would pennit the FIR
filter to operate rnore slowly by inco~orating decimation into the filter operatiQn, i.e., eomputing only the outputs needed by subsequent filter sections operating at a reduced samplmg rate. In a CMOS implementation, power consumption is typically 30 reduced when operational speed is reduced. There~re, the power consumption ofthe FIF~ combining filter eould be reduced at the expense of some control circuitry.
Between the "fast" filters 308 and 310 and"slow" lowpass filters 31~ and 313 of Figure 3, it is desirable to perform sampling rate reduction, or decimation. As is well known in the art, the degree of sampling rate reduction possible depends on the 35 amount of attenuation provided by the "fast" lowpass filters. For example, if a 20 MH~ input sampling rate is used, and the "fast" filters are implemented as decomposed filters with coefficients as listed below in table 3, then an output 27 ~8~3~8 sampling rate of 2 MHz can be used with over 100 Db of aliasing protectiOn provided by the"fast" filters filter ~ I rate o5 fast(dcco~s~d) 1 2 8 2-g 1 20 slowl 1 2-6 2 ~
slow2 1 2-6 2-3 1 2 SloW3 1 2-6 2-4 1 2 1~ ~ ~_I
TAP,LE 3 .The "slow" lowpass ~llters 312 and 313 can be imp]emented by several stage$ of two pole filter sections For example, if three stages, each having the structure of l 5 Figure 9a, 9b, and 9c and the coefficients listed in Table 3 are used, wherein slow 1 slow 2 and slow 3 correspond to Figures Figure 9a, 9b, and 9c, respectively, then the sampling rate can be reduced from 2 MHz to 80 KHz An alternative hardware-saving design ~nvolves interleaving the in-phase and quadrature sample sample streams and using ~hree stages of time-division-2 o multiplexed filtering This requires that the filters run at twice the raee they wouldoperate with a non-multiplexed design but since the sampling rate is reduced by a factor of 10 from the fast filter, this multiplexed ~llter still çan operate at one-fifth ~he rate of the f~t filt~n~ stage Figure 9a is a block diagram of the first time-division-multiplexed 2 5 second-order lowpass IIR filterirlg stage used in the time-division-multiplexed implementation oî the "slow" lowpass filters Figure 9a through 9c represent a time-division multiplexed version of a filter structu~e similar to ~hat depicted in Figure 7. The la~in difference between the structure in Figure 7 and the multiplexed version in Figure 9 is th~t the delay elements have been doubled in length. Thus30 instead of using z~1 elements, implemented in hardware as single latches, z-2elementr, are used which are implemented as two latches configured in series. The effect of this slructure is that the filter alternates each sample between processing in-phase and quadrature samples In thc following discussion, the operation of Figure 9 is discussed in detail. After processing by digital filter 900a, the signal is 3 5 couplèd to the second filtering stage 900b and subsequently to the third filtering stage, depicted by Figure 900c The overall filter structure of digital filters 900a, 900b, and 900c is identical, so only digital filter 900a is discussed in detail ~ 3~3~8 2~

However, the data paths and filter r~sponses of digital filters 900a, 900b and 900c vary slightly between the various stages, as shown by Figures 9a,9b and 9c,respertively, as well as Table 3.
The digital lowpass filter 900a consists of four digital adders (2's complement) o 5 904a, 908a, 912a, and ~16a, four digital latches two each in 910a, and 918a, and two binary shifters 906a and 914a. The input signal to the digital ~llter 900a is applied to a non-inverting input ~02a of the digital adder 904a. A second inverting input to the digital adder 904a is taken from digital latch pa~r 918a which is fed back ~rom the output 920a of the fi~ter circuit. The difference (2's complement) result of digital adder 904a is next appli d to the input of bit shifter 906a which presents the shifted first sum signal as one ~nput of digital adder 908a.
Bit shifter 906a shifts all bits of the data word outputted from digital adder 904a to the nght (i.e., toward the least significant bit) by Nc bits, effeeting multiplication by a coefficient equal to 2-Nc. This bit shift rnay be implemented by an appropriate routing of the data lines from digital adder 904a to adder 908a. Thus, high operating speed of digital filter section 900a is facilitated, since there is no t~rne delay associated with bit shifter 906a, as there would be in a coefficient multiplication implemented by a conventional multiplier circuit.
Digital adder ~08a adds to the shifted first sum signal the output of digital adder 2 o 908a from two sample times past as held in latch pair 910a Further, the output of digital adder 908a as held in latch 910a is applied to digital adder 912a. A second inverting input to digital addar 912a is taken from latGh pair 918a which, as previously mentioned, is taken from the output 92ûa of the digital filter. The result of digital adder 912a is applied to bit shifter 914a which is coupled to digital adder 912a. Bit shifter 914a shifts all bits of the data word outputted from digital adder 912a to the right by Na bits, effecting multiplication by a coef~lcient equal to 2~Na.
Bit shifter 914a also facilitates high operating speed since no time delay is incurred.
The parameters Nc and Na associated with bit shifters 906a and 914a respectively, control the frequency response of digital filter section 900a, and may be chosen to yield the response appropnate to the intended application. Digital adder 916a adds the second shifted sum si~nal to the previous output of 916a as held in delay 918a.
The vutput of delay 918a is also the output of the digital lowpass f;lter section 900a and represents a band-limited representation of the input signal 902a that was previously applied to the input of sumn~ng circuit 904a.
It will be obvious to one skilled in the art that more gradual sample-rate reduction could be employed, say, between each of the four (total) lowpass filter sections. Gradual sa nple-rate reduc~.ion o~fers a significan~ advantage in that it gives 29 13~83~

much flexibility ~n establishing the overall ratio of the input to thc output sarnpling rates. This pern~ts the A/D sarnpling rate to be established almost arbi~arily to match a desired p~eselector passband, subject to a constr~int on thc output sa~npling rate. At the output of the third (and last) "slGw" lowpass filter section, sufficient 0 5 attenuatiorl has been applied to channels at higher frequencies, so that the aliasing caused by dec~mation fr~m 2 MHz to 80 kHz does not interfere with the des~red band, cen~red at approximately zero frequency.
After filter processing and decimation by the high speod selectivi~ sections 114of Figure 1, the recovered digital signal comprises a received digital signal having quadrature components. The quadrature characteI~stics of the received digital signal insures that phase information present in the or~inal RF signal is preserved through the processing cha~n. The received qu~ture digital signals are coupled to the digital receiver backend 120 of Figure 1, which is advantageously implemented by a prograrnmable, general purpose digital signal processing I.C., as men~ioned above.
The radio backend 120 performs the addidonal processing required to generate thedigital baseband signal used to provide a recovered data or audio signal. In addition, the radio backend 120 can provide final predemodulation filteling and post-demodulation processing of the recovered signal. Figures 10 and 11 detail digital filter structures suitable for performing final predemodualtion selectivity in 2 o ~he context of a digital signal processing I,C:. F}gure 12 below details one technique which is suitable ~or dçmodulating an FM signal in accordance with the teachings of the present invention.
Figure 10 shows a fifth-order nonrecursive filter 1000 which provides additional attenuation so that the sampling rate may be further reduced from 80 to 49 kHz while causing negligible aliasing distortion of the desired band. Because ~his filter is operating at the relatively low output sarnpling rate of 40 ~I7 (complex samples), it is possible to împlement it in a general-pulpose digital signal processor.
Such processors are typically well suited to pipelined multiply operations 1004,lOI0, 1016, 1026, 1030, 1036, and accumulate operations 1006, 1012, 1020, 1~24, and 1032, so that the "direct~form" ~lter structure was chosen.
Figure 11 shows a direct-form filter structure 1100 wi~h four poles and four zeros, which is employed to smooth out the passband response of the composite receiver filter. it may be implemented with a senes of multiply operations 1104,1112, 1118, 1120, 1126, 1132, 1140, 1146, and 1150, an-accumulate operaiions 1106, 1114, 1116, 1122, 1108, 1130, 1136, and 11~ in a general-purpose digital signal processor, Because single-precision (~pically 16-bit wordlen~th) operations ~o 13~83~

do not asr~os~ sufficient dynamic range for mobile-radio applications, it is necessa~y to use double-precision calculations in the DSP implementation. It will be apparant to one skilled in the ~t that different bandwidths ~or the final selectivity section could be programmably obta~ned by choosing different ~llter coefficients in 0 5 the back^end DSP. Also, different selectivi~ bandw~dths may be obtained through use of different downsasnpling rates, or through different w~red-gain elements (via two-to-one selectors, for example) in the multiplierless lowpass filter sections.
Figure 12 is a diagrarn of a digital FM dernodulator compatible with the digitalradio architecture of the p~esent invention. In reality, digital demodualtion i5 one 10 task, among others, performed by a digital signal processor I. C. According tv Figure 12, limiter section 1202 complises dle scaling stage 1204 together with the in-phasechannel inverse calculation generatorl210 and ~e productmultiplier 1212 where the reciprocal of the scaled and rotated in-phase (I') con~ponent is multiplied with ehe scaled and rotated out-of-phase (Q') componentpr~ducing a 15 terrn equal to ~he value of the tangent of the phase angle of the scaled and roeated signal vector sample. The action of digital multiplier 1212 perfosms an ideal limi~ng of any amplitude variations of the input signal vector that may be present.
The terrn passed from the digital muleiplier 1212 represents the tangent of the roeated and scaled signal vector sample. This tenn is processed by the arctas~gent 2 o generator stage 1214 whose output equals the phase angle of the ~otated and scaled signal vector. This quantity when added by digital susslmer 1214 to the coarse phase value output from the coarsc phase accumulator 1206 represents the total phase angle of the input signal ve t~r sample. ll~e difference signal generatedat the output of digital summer 1218 between the phase angle of ~e current signal 25 vector sample and ~e negative of the delayed output generated by digital delay 1220 represents 1 sample of the output demodulated message.
Figures 13a through 13c are diagrams detailing the principles of phasors ~n the cantext of the present irlvention. Referring now to Figure 13a, the scaler's 1204 func~on is to scale ~he amplitude of the input signal vector of varying magnitude to 30 the shaded region shown. The coarse phase accumulator 1206determines the coarse phase angle of the signal vector, 0~, and the output of the arctangent generator stage 1212 equals the fine phase of the signal vector, 0f, as depicted in fig. 13b. The signal vector 0f is conshained by the vector rotation to lie in the range of -~/4 5 0f S +~/4 (shaded region of Figure 13b.) The sum of these 2 3 5 quantities generated at the output of digital sun~ner 1214 represents the total phase angle of the input signal 3 1 1 3 1 8 3 ~ 8 vector sample, 0(n). The difference value ~ (n)) generated by digital summer 1218 between the current phase sample, 0(n), and the phase sample, ~(n-1) generated by digital delay 1220, as shown in Figu~e 13c, represents one sample of the demodulated OlltpUt message. The s~eam of samples representing the 0 5 demodulated outF ut mcssage may be low passed filtered ItO remove noise outside the message bandwidth, as is ~pically perfonned subsequenlt to ~M detection.
It would be obvious to one of ordinary skill in the art that the digital demodulator described in the f1gures above could be implemented with discrete hardware digital multipliers, adders, registers, etc. The d:igital demodulator of the 10 present invention is particularly suitable for implementation with a class of devices known as digital signal processors. The present invention would perform satisfactorily with a varie~ of well Icnown digital signal processors such a NEGD7720, available from NEC Electronics U.S.A. Inc., One Natick lExecutive Park, Natick, Mass. 01760, or a TMS 32010 available from Texas Instruments Inc, P.C).
Box 225012, Da:llas, Texas 75226S. Digital signal pr~cessors generally include hardware high speet digital multipliers as well as the abili~ to process a digital data stream in accordance with a predete~ned algorithm.
Figures 14a and 14b are flow diagrams detailing the background processing oF
the present invention as ~mplemented with a digital signal processor. In all 20 descriptions of the present invention, the in-phase and out-of-phase signal vector components will hereinafter be referred to as the components I and Q respectively.
The algorithm of the present invention begins at 1402, which causes the digital signal processor to execute deeision 1404 to determine the sign of the I component.
Based on the outcome of decision 1404, the sign oî the Q component is determined by decisions 1406 and 1448. Next, ehe difference of the I and Q
components is deterrnined by items 141Q 1408, 1472, and 1450 which generate values comprising the values of Q ~ Q, Q - I, and Q + I, respectively. The sign of the respective results is determ~ned by decisions 1430, 1412, 1474, and 1452, respectively. Based Oll the results of these decisions, the component (I or Q) which has the greater abso1ute value is known, and the octant ~i.e. multiple of 7~/4) in which the signal vector lies is also known. This value, if less than zero, is complementedbyitems 1420, 1486, 1476, and 1462, respectively. The valu~ that represents the greatest absolute value of either the I or Q channel is pushed onto a program staclc by items 1442, 1432, 1422, 1414, 1488, 1478, 1466, or 1454, respectively, and is hereafter referred to as the quantity SMAX. 'rhe quantity S~X is used by the call to she scale subroutine by items 1444, 1434, 1424, 141~, 1490, 1480, 1466, or 1456 32 ~ ~183~8 respectively, to deter~r~îne the correct amount of 5caling to be applied to the input signaI vector sample. The scale subroutine returns correctly scaled signal vector components I and r:2. Next a coarse phase value, based on the octant location ofthe signal vector is stored to a temporary storage location by items 1446, 1436,05 1426, 1418, 1492, 1482, 1468, or 1460, respectively.
This value will always be a multiple of ~/2 radians over the range of -~ S
0(c) 5 ~. The signal vector is then geometrically rotated Iby the negative of the coarse phase value that was saved by items 1440, 1428, 1492, 1484, 1470,or 1460,respectively. The scaled and rotated signalcomponents that result are hereafter referred to as the I' and Q' signal vector components. The effectof this vector rotation is torotate the signal vector such that the rotated signal vector components I' and Q' yield a composlte vector with a phase angle in the range of -J~/4 S 0f ~ ~/4.
Figures lSa and lSb ~re flow diagrarns of the operation of the scale subroutine described in conjunctiorl with Figure 14a above. The scaling subroutine 1500 examines the value of SMAX todeterrn~ne the correct amountof scaling to be applied to the signal vector components I and Q. The operation of this subroutine is dependent on the resolution or nurnber of bits used to represent the signal vector cornponents. The operation of the scale subroutine will be explained 2 o in the context of using 32 bit long words to represerlt the signal vector components.
Upon en~y to the scale subroutine at 1502, the most significant word (MSW) of the quantity SMAX is compared to zero by decision 1504. If the MSW of SMAX is greater than zero, the ieast significant word (LSW) of SMAX will be discarded, and the MSW will be compared to a scaling threshold value by item 15û6. If the MSW of S~X is found to equal zero, then the MSW will be discarded, and the LSW will be compared to a scaling threshold value by item 1528. The results of the comparisions generated by items 1506, and 1528, respectively, are tested againstzero by decisions 1508, and 1530, respectively, and if the result is found to begreater than zero, no scaling of the signal vector components is necessary, and the 3 0 subroutine exits through item lSS0 to the point where the routine activated subroutine 1~00. If the retained word (i.e. MSW or LSW) of SMAX is less than the threshold value, the retained word is tested to see if it absolute magnitude is greater than 255 by decisions lS 10, and 1~32, respectively. This is equivalent to determining if the upper 8 bits of the retained word of SMAX are greater than or3 5 equal to zero. If the result of this test is true (i.e. the MSW or the LSW of SMA~
is greater than 255), theretained word is dividedby256byitemslS14OrlS36 respectively. This has the effect of shifting the upper 8 bits of the retained word of ~3~L~3~

SMAX ~nto the lower 8 bits of this word. If the result of decision 1510, or 1532indicates thatthe reta~ned word is less tban 255, then no division is p~rforned. This quantity is now used as an address o,ffset by items lS16, 1512, lS38, or 1534 to select values stored in ROM data table, ard a scaling factor iso 5 retrieved from a ROM by items 1520, 1540. This factor is adjusted to the correct value necessaly to scale this signal vector components, depending on previous decisions 1510 or 1532. Finally the signal vertor components are scaled to the correctregion for use by the approxirnations applied within the demodulator by iterrls 1522 and 1524 or 1542 and 154~ and the routine e xists back to the calling procedure through items 1526 or lS4~.
Referring now to Figure 16a, the inverse or reciprocal of the I' vector component is nowdetermined. This processing is accomplished by - -irnplementing a 6th order Chebyshev polynomial approx~rnation to the function f(x) = l/x.
The polynornial whi~h approximates dlis function is:

f(x) = (l/x) ~
{[[[~[ C7(x-i)+C6 ~(x-l)~C5 ](x-l)+C4 ](x-ll+C3 ](~ C2 ](x-l)+Cl }
where, x=I' and, C1 = +1.00000, C2 = -1.0027, C3 = +1.00278, ~4 = -0.91392, CS = +0.~1392, C6 = -1.62475, ~7 ~ ~1.6~47~.

According to the principles of the present inYention, ~he Q' component is pushedon a program stack storage area by item 1604 and the quantity (I'-l) is c~lculated by item 1606, hereinafter referred to as the quantity ARG. Coefficien~ C7 is fetched from data ROM by item 1608 and is multiplied with ARG by item 1610 forrning a quantity 1~. Coefficient C6 is fetched from as data ROM by item 1612 and added to l'MP by iten 1614 yielding the new value for TMP. This pattem is successively repeated by items 1616 through lS44 until the Q' component is then fetched from the pro~ram stack storage by item 1648 and multiplied with l~P by item 1650 yielding an approximation to the quantity tan 0f = Q'll'.

34 ~3~8~8 Thç arctangent of the quantity obtained by item 1650 is now determined. This pr~cessing is performed by implementing a 5th order Chebyshev polynomial approx~mation to the function:
0f = arctan(x) The polynomial that approximates this function is:

arctan(x) ~
x{[[[[C6(y)+CS]y+C4]y~3]y~C2]y~CI }
where, x = Q'/I' y _x2 = (Q~ 2 and,C6=-0.01343, C5-+0.05737, C4=-O.l~109, C3=+0.19556, C2 = -Q.33301, C1 - +0.99997.
The quantity x = (Q'/I') is push onto program stack storage by item 16~2, and the value of the squared quantity y, x2, hereinafter referred to as ARG is calculated by item 16~4. In a chain like manner, similar to the calculation of the inverse value described previously, the value of the arctangent of the quanti~
(Q'/I') is computed by iterns 1656 through 1692. The result of this process is asigned value representing the phase angle of the rotated signal vector, or the fine phase angle of the inpu~ signal vector sample. The value of the coarse phase of the input signal veetor sample is retrieved from a temporary storage location by item 1694 and is surruned with the result of ~he arctangent calculation by item 1696.2 5 This result represents the phase angle of Ihe input signal vector s~mple. The phase angle of the previous input signal vector sarnple~ 0n- l, is fetch~d from a program sSack by item 1700. The currenl phase sample is pushed onto a pro~Fam stack by item 1702. Finally, the diffe~nce of the previous phase sample and the current phase sample is calcula~ed by item 1704 thus yielding an output s~nple of the demodulated message m(n) The message sample m(n) compnses the demodulated voice signal in a sa npled folm. The demodulated voice signal may be converted back to analog forrn, then amplified and played through a loudspealcer,~s mentioned above. Alternatively, adigital voice message may be stored in digisal a digital memory 123 for later use 35 1 3~ 83~8 In a data colT~nunications system (not shown), demodulated data symbols nnay be routed to a computer for funher p~ocessing or to a computer te~ninal for immediate display.
In su~runary, a digital radio receiver has been described. The digital receiver of o 5 the present invention contemplates an all digital radio rece iver which operates on a received signal which is converted to a digital form after preselection at the output of the antenna The receiver of the present invention compr;ses a preselector, a high-speed analog-to-digital (A/D) converter, a digitally isnplemented intermediate-frequency ~IF) selectiYity section having an output signal at substantially baseband frequencies, and general-purpose digital signal processor(DSP) integrated circuits perfo2m~ng demodulation and audio f;lter~ng. Other uses and modifications of the present invention will be obvious to one of ordinary skill in the art without departing from the spirit and scope of the present invention.

l S We claim:

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A method of digitally demodulating a received angle-modulated signal, said method comprising the steps of:

(a) inputting digitized quadrature samples of a signal centered approximately at zero frequency, said samples indicating a composite signal vector;

(b) scaling said samples to a desired magnitude within a predetermined range;

(c) calculating the nearest octant within which the scaled composite signal vector lies, said nearest octant comprising a coarse phase range value;

(d) rotationally scaling the scaled composite signal vector to lie within a range between -.pi./4 to + .pi./4, (e) calculating a second value equal to the tangent of the phase of the rotationally scaled signal vector;

(f) calculating a third value equal to the phase angle of said signal vector by deriving the arctangent of said second value, said third value comprising a fine phase angle value;

(g) summing the fine phase angle and coarse phase angle values to produce a composite phase angle sample equivalent to the phase angle of the input signal vector;

(h) filtering the sequence of phase angle samples to produce a sequence of demodulated message samples;
and (i) outputting said demodulated message samples to an output register.

2. A digital demodulator apparatus having improved linearity, said apparatus comprising:

(a) means for inputting a sampled input vector comprising a quadrature signal centered approximately zero frequency;

(b) scaler means for quantizing said inputted sampled quadrature signal within a predetermined range;

(c) phase accumulator means for generating a current coarse phase value related to input vectors of the quadrature FM signal;

(d) vector rotation means for rotating said input vector to a quadrant within a range between -n /4 to +.pi./4;

(e) means for determining a fine phase value based on said rotated input signal vector;

(f) summing means for summing said fine and coarse phase values and outputting a composite phase value;
and (g) filtering means for filtering the sequence of phase angle samples to produce a sequence of demodulated message samples.

3 A method of digitally demodulating a received FM signal, said method comprising the steps of:
(a) inputting digitized quadrature samples of a signal centered approximately ar zero frequency, said samples indicating a composite signal vector;
(b) scaling said samples to a desired magnitude within a predetermined range;

(c) calculating the nearest octant within which the scaled composite signal vector lies, said nearest octant comprising a coarse phase range value;

(d) rotationally scaling the scaled composite signal vector to lie within a range between -.pi./4 to +.pi./4.

(e) calculating a second value equal to the tangent of the phase of the rotationally scaled signal vector;

(f) calculating a third value equal to the phase angle of said signal vector by deriving the arctangent of said second value, said third value comprising a fine phase angle value;

(g) summing the fine phase angle and coarse phase angle values to produce a composite phase angle sample equivalent to the phase angle of the input signal vector;

(h) subtracting the value of the previous composite phase angle sample from the value of the current composite phase angle sample to produce a demodulated message sample; and (i) outputting said demodulated message sample to an output register.

4 A digital FM demodulator apparatus having improved linearity, said apparatus comprising:

(a) means for inputting a sampled input vector comprising a quadrature FM digital signal centered approximately zero frequency;

(b) scaler means ar quantizing said inputted sampled quadrature signal within a predetermined range;

(c) phase accumulator means for generating a current coarse phase value related to input vectors of the quadrature FM signal;

(d) vector rotation means for rotating said input vector to a quadrant within a range between -.pi./4 to +.pi./4;

(e) means for determining a fine phase value based on said rotated input signal vector;

(f) summing means for summing said fine and coarse phase values and outputting a composite phase value;
and (g) filtering means for subtracting the value of the previous composite phase angle sample from the value of the current composite phase angle sample to produce a demodulated message sample.