CA1311858C - Resonant-tunneling three-terminal unipolar device - Google Patents

Abstract

RESONANT-TUNNELING THREE-TERMINAL UNIPOLAR DEVICE

Abstract Negative conductance as well as negative transconductance are realized in a unipolar three-terminal device which includes an ohmically contacted quantum well structure between a source contact and a drain contact on a channellayer. Contemplated primary device use is in switching and microwave applications.

Description

131 1~58 RESONANT-TUNNELING THREE-TERMINAL UNIPOLAR DEVICE

Technical Field The invention is concerned with three-terminal semiconductor unipolar devices whose operation is based on resonant tunneling through a quantum well.
Back~round of the Invention C~haracterized by carrier energy coinciding with a quantized energy level in a potential well, resonant tunneling of carriers through a potential well (quantum well) is receiving increasing attention largely on account of negative differential resistance effects as potentially useful in ultrahigh-frequency device applications. For example, three-terminal devices based on resonant-tunneling operation have considerable functional potential in digital and microwave circuits.
Reports concerning implemented resonant-tunneling, three-terminal devices describe a resonant-tunneling hot electron transistor (RHET) and a resonant-tunneling bipolar transistor (RTBT); for these, and for other relevant devices and device-related experimental investigations see N. Yokoyama et al., "A New Functional, Resonant-Tunneling Hot Electron Transistor (~ET)", Japanese Journal of Applied Physics, Vol. 24 (1985), pp. L853-L854, F. Capasso et al., "Quantum-Well Resonant Tunneling Bipolar Transistor Operating at Room Temperature", IEEE Electron Device Letters, Vol. EDL-7 (1986), pp. 573-576, S. Luryi et al., "Hot Electron Injection Devices", Superlattices and Microstructures, Vol. 1 (1985), pp. 389-400, and M. Tsuchiya et al., "Room Temperature Observation of Differential Negative Resistance in an AlAs/GaAs/AlAs Resonant Tunneling Diode", Japanese Journal of Applied Physics, Vol. 24 (1985), pp. L466-L468.
Summary of the Invention Negative conductance as well as negative transconductance are realized in a three-terminal device comprising a substrate-supported channel layer, source and drain contacts on the channel layer, and a quantum well structure with a gate contact between the source contact and the drain contact. While, in geometric terms, the device may resemble a field effect transistor (and thus maybe designated as a "resonant tunneling gate field effect transistor"), the gate contact to the quantum well structure is ohmic and, under most contemplated device operating conditions, there will be a significant flow of gate current.
According to one aspect of the invention there is provided a semiconductor unipolar device, said device comprising a substrate-supported channel layer, source and drain contacts on said channel layer, a layered structure on said channel layer between said source contact and said drain contact, and a gate contact on said layered structure, said layered structure forming at least one quantum well between said gate contact and said channel layer.
Brief Description of the Drawin~
FIG. 1 is a schematic cross-sectional view of an embodiment of the invention, including a resonant-tunneling double barrier structure;
FIG. 2 is a schematic energy band diagram as applicable under operating conditions of resonant tunneling through the double barrier structure of FIG. 1;FIG. 3 is a schematic energy band diagram applying to operating conditions under which resonant tunneling through the double barrier structure of FIG. 1 is inhibited or "quenched";
FIG. 4 is a graphic representation of gate and drain currents as a function of gate voltage as realized in an embodiment of the invention, drain and source being tied to the same potential;
FIG. 5 is a graphic representation of gate and drain currents as a function of gate voltage as realized in an embodiment of the invention, the drain being negatively biased with respect to the source;
FIG. 6 is a graphic representation of gate and drain currents as a function of drain bias as realized in an embodiment of the invention, gate voltage being zero; and FIG. 7 is a graphic representation of gate and drain currents as a function of drain bias as realized in an embodiment of the invention, gate voltage being positive.

- 2a - 1 31 1 858 Detailed Description For the sake of specificity, and without precluding the use of other materials in device implemcn~tion, the description of the Figures applies to a GaAs/AlGaAs n-channel device. Also, the description of device operation is not 5 intended to be exhausdve, operation under a variety of alternate conditions being of potential practical significance.
nG. 1 shows semi-insulating gallium arsenide substrate 1, n-doped gallium arsenidc channel layer 2 and, on layer 2, source contact 3 and drain contact 4. Also on layer 2, between source contact 3 and drain contact 4, is a 10 structure including undoped gallium arsenide spacer layer 5, resonant tunneling double barrier 6, undoped gallium arsenide spacer layer 7, n+-GaAs contact layer 8, and gate contact metallization 9. Resonant tunneling double barrier 6 comprises undoped aluminum arsenide barrier layer 61, undoped gallium arsenide quantum well layer 62, and undoped aluminum arsenide barrier layer 63.
For the sake of ease of interpretation of the drawing, layer dimensions are not shown to scale; typical dimensions are a channel layer thickness in a preferred range from 0.05 to 1 micrometer, a spacer layer thickness in a preferred range from 20 ts) 100 Angstroms, a barrier layer thickness in a preferred range from 20 to 50 Angstroms, and a quantum well layer thickness in a preferred rangefrom 30 to 100 Angstroms. Also, more generally, compositions such as Al Ga xAs, 0.25 <x < 1 are suitable as barrier layer materials, and the use of yet oXthe~~
compound semiconductor matelials is not precluded. For example, barrier layers can be made of indium phosphide, and a well layer of gallium indium arsenide.
Or, aluminum gallium arsenide barrier layers can be combined with an indium gallium arsenide (strained) well layer. Well and barrier layers are preferably undoped, and the presence of optional, undoped spacer layers is preferred in theinterest of minimizing scattering.
In lieu of a double-barrier structure forming a single quantum well, it is possible to use a superlattice of alternating barrier layers and well layers,forming a plurality of quantum wells.
FIG. 2 and 3 are based on the assumption that the quantum well structure of the device is positioned at the midpoint between source and drain contacts, without precluding alternate, off-center positions.
Current-voltage characteristics of nG. 4 and 5 at fixed drain-source voltage (0 in FIG. 4, -0.2 V in FIG. 5) show common features such as negative conductance regions in gate current IG versus source-gate voltage, and these maybe interpreted as being associated with the suppression of resonant tunneling through the double barrier. Such suppression of resonant tunneling produces a variation (either an increase or a drop, depending on the gate bias polarity) in the drain current ID at the same gate-source voltage. It is readily seen that the variation in gate and drain current is abrupt for positive gate-source voltage, and gradual for negative gate-source voltage. This phenomenon may be explained in tercns of accumulation or depletion layers which form, depending on gate bias polarity, in the channel layer adjacent to the double barrier structure.
More specifically with respect to FIG. 4, it is appreciated that negative conductance in gate current occurs when the potential difference between the region of the channel adjacent to the double barrier and the gate contact layer is large enough to quench resonant tunneling. This is accompanied by a corresponding peak in drain current.
With respect to FIG. 5, when gate-source voltage is positive and the drain is negatively biased with respect to the source, the current-voltage characteristics are shifted to lower gate-source voltages. This is understood asresulting from an increase of the electron potential energy in the region of thechannel under the gate, so that less positive gate bias is required for quenching of resonant tunneling. It is noted that both gate and drain currents drop abruptly as gate-source voltage is increased. When drain-source voltage is negative, the drain current consists of electrons flowing from the drain to the source and from the drain to the gate. When resonant tunneling is quenched, the latter flow is reduced, and the drain current drops. As a result, this device also exhibits negative transconductance.
Further with respect to FIG. S it is observed that, for negative gate-source voltage in correspondence with the negative conductance region in the gate current versus gate-source voltage characteristic, and for sufficiently large drain-source voltage, the drain current increases. Also, the decrease in gate current is quite gradual. When a negative drain-source voltage is applied at small negativegate-source voltage, the gate current consists of electrons which tunnel from the channel into the gate layer. When the gate is made more negative, so that the gate potential first e~uals and then exceeds the potential in the channel under the gate, the gate current first goes to zero and then changes sign. As the magnitude of the gate-source voltage is further increased, the resonant tunneling of electrons into the channel is eventually suppressed, and this leads to a decrease in gate current. The drop in the gate current here is gradual, in contrast to the shalp drop in the case of positive gate-source voltage; this indicates that reson~nt tunneling is not quenched at the same gate voltage throughout the double barrier - as caused by a thin depletion layer at the interface between the double-barrier structure and the channel layer.
In FIG. 6 and 7, gate and drain currents are shown as a function of drain bias for fixed gate-source voltages (0 in FIG. 6, +0.2 V in FIG. 7).
Specifically with respect to FIG. 6, when drain-source voltage is positive, electrons tunnel from the gate layer into the channel. And, when drain-source voltage is negative, electrons tunnel from an accumulation layer at the interface between the double barrier and the channel, into the gate contact layer.

1 3 1 1 ~5~3 Specifically with respect to FIG. 7, at zero drain-source voltage, electrons tunnel from the channel into the gate, and a positive drain-source voltage is required first to suppress such tunneling, and then to reverse the direction of tunneling electrons.
While the discussion above is based on an n-channel device, p-channel analogue device embodiments are not precluded. Still, since hole mass isgreater than electron mass (and hole mobility lower~, n-channel devices are preferred with respect to device operating speed.
Devices of the invention can serve as oscillators, frequencies of 20 to 30 GHz being readiiy achievable. Other uses are in logical and switching applications; e.g., an "exclusive or" gate can be implemented readily. Also, devices can be interconnected in various ways, and such devices can also be usedin combination with other types of semiconductor devices. For exarnple, when used in combination with a metal-semiconductor field effect transistor, a complementary structure can be realized as suitable, e.g., for logical inverter application. As compared with the use of ordinary transistors, use of negaeive-transconductance devices of the invention can lead to savings with respect to the number of devices used for complicated functions and, as a result, to savings ofspace, to reduced interconnection requirements, and to faster systems operation. The following Example provides device dimensions and manufacturing conditions as have been used in making a specific embodiment of the invention. All quantitative values are nominal or approximate.
Example A device as schematically depicted in FIG. 1 was made by molecular-beam-epitaxy deposition on a semi-insulating substrate made by liquid-encapsulated Czochralsky growth. The channel layer was grown 1 micrometer thick, n-doped with 4X1017 cm~3 Si. The undoped spacer layers were grown 25 Angstroms thick, and the undoped resonant-tunneling double barrier between the spacer layers was made of successive layers of aluminum arsenide (25 Angstroms), gallium arsenide (70 Angstroms), and aluminum arsenide (25 Angstroms~. The n+ tsx1017 cm 3) contact layer was 0.4 micrometer thick.
The gate metallization was made by successive evaporation of 60 Angstroms germanium, 135 Angstroms gold, 500 Angstroms silver, and 750 Angstroms gold.

The channel was exposed by etching a 5500-Angstrom-high mesa, using a selective etch to remove gallium arsenide, and hydrochloric acid to remove aluminum arsenide. (The selective etch consisted of a few drops of ammonium hydroxide in hydrogen peroxide to give a pH of approximately 7.2).
The drain and source contacts were defined by lift-off. Source and drain contactmetallizations were made by successively evaporating 50 Angstroms Ni, 385 Angstroms gold, 215 Angstroms germanium, and 750 Angstroms gold. The contacts were simultaneously alloyed in flowing hydrogen at a temperature of approximately 400 degrees C for approximately 10 seconds. Horizontal device dimensions are a gate length of 4.65 micrometers, a gate width of 308 micrometers, source-gate spacing of 2.15 microme~ers, and source-drain spacing of 9.8 micrometers.
Experimental results as graphically depicted in FIG. 4-7 were obtained at a temperature of approximately 100 degrees K.

Claims (5)

1. A semiconductor unipolar device, said device comprising a substate-supported channel layer, source and drain contacts on said channel layer, a layered structure on said channel layer between said source contact and said drain contact, and a gate contact on said layered structure, said layered structure forming at least one quantum well between said gate contact and said channel layer.

2. The device of claim 1, said device having operating conditions under which conductance is negative.

3. The device of claim 1, said device having operating conditions under which transconductance is negative.

4. The device of claim 1, said layered structure comprising barrier layers and awell layer forming a resonant-tunneling double barrier.

5. The device of claim 4, said barrier layers consisting essentially of gallium arsenide, and said well layer consisting essentially of AlxGa1xAs, 0.25 < x < 1.6. The device of claim 4, said barrier layers and said well layer being essentially undoped.
7. The device of claim 4, said layered structure comprising a spacer layer between said channel layer and said resonant-tunneling double barrier.
8. The device of claim 4, said layered structure comprising a spacer layer between said gate contact and said resonant-tunneling double barrier.
9. The device of claim 1, said layered structure forming a plurality of quantum wells.
10. The device of claim 9, said layered structure comprising a superlattice.
11. The device of claim 1, said channel layer being n-doped, and said gate contact comprising an n-doped contact layer.