CA1248600A - Sine-wave generator - Google Patents
Sine-wave generatorInfo
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- CA1248600A CA1248600A CA000547089A CA547089A CA1248600A CA 1248600 A CA1248600 A CA 1248600A CA 000547089 A CA000547089 A CA 000547089A CA 547089 A CA547089 A CA 547089A CA 1248600 A CA1248600 A CA 1248600A
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- 230000010355 oscillation Effects 0.000 claims abstract description 5
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 238000005259 measurement Methods 0.000 description 21
- 238000004804 winding Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 3
- 239000000700 radioactive tracer Substances 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- PCLIRWBVOVZTOK-UHFFFAOYSA-M 2-(1-methylpyrrolidin-1-ium-1-yl)ethyl 2-hydroxy-2,2-diphenylacetate;iodide Chemical compound [I-].C=1C=CC=CC=1C(O)(C=1C=CC=CC=1)C(=O)OCC[N+]1(C)CCCC1 PCLIRWBVOVZTOK-UHFFFAOYSA-M 0.000 description 1
- 241000272470 Circus Species 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
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- Measurement Of Current Or Voltage (AREA)
Abstract
Abstract:
The present invention relates to a sine-wave generator. The generator is comprised of a variable frequency signal generator and a frequency divider for producing a plurality of divided output signals by dividing the output frequency of the variable frequency signal generator. A phase comparator is provided for comparing one of the divided output signals from the frequency divider with the AC line voltage and controlling an oscillation frequency of the variable frequency signal generator in response to the comparison result. A
converter unit is provided for converting an input signal into a sine-wave voltage in response to the divided output signals from the frequency divider. A voltage comparator is provided for comparing a voltage corresponding to the sine-wave voltage from the converter unit with a reference voltage so as to generate the input signal to the converter unit.
The present invention relates to a sine-wave generator. The generator is comprised of a variable frequency signal generator and a frequency divider for producing a plurality of divided output signals by dividing the output frequency of the variable frequency signal generator. A phase comparator is provided for comparing one of the divided output signals from the frequency divider with the AC line voltage and controlling an oscillation frequency of the variable frequency signal generator in response to the comparison result. A
converter unit is provided for converting an input signal into a sine-wave voltage in response to the divided output signals from the frequency divider. A voltage comparator is provided for comparing a voltage corresponding to the sine-wave voltage from the converter unit with a reference voltage so as to generate the input signal to the converter unit.
Description
~,z,~
Sine-__ve ~e__rator This is a division of copending Canadian Patent Application Serial No~ 491,897 which was filed on September 30, 1985.
BACKGROUND_OF TH:E_INVENTION
The present invention relates to an apparatus for measuring characteristics of electronic devices, such as transistors, diodes, etc~
An electronic device measurement apparatus called generally a curve tracer is useful to measure characteristics of electronic devices, such as transistors, diodes, etc.
A typical one of conventional electronic device measure-ment apparatus is .illustrated in FIG. 1., wherein a collector voltage suppl.y circuit 10 includes a variable transformer for increasing or decreasing an AC voltage from an external line voltage source so as to obtain a sine-wave voltage having a desired amplitude. rrhe sine-wave voltage is applied to a primary winding of a trans~ormer 12 which includes a secondary winding having a ~,g 36g~
plurality of taps. A selector/rectifier circuit 14 selects one of the taps in accordance with a measurement range and rectifies the sine-wave voltage from the selected tap. The rectified voltage from the selector/rectifier circuit 14 is applied through a limiter resistor 16 to a collector of a transistor 18 as a device under test(DUT). The value of 'che resistor 16 is changed in accordance with the measurement range. The lowest terminal of the secondary winding of the transformer 12 is connected through a current detectin~ resistor 20 to an emitter o the transistor 18 which is grounded~ A base of the transistor 18 receives a step bias signal from a bias supply circuit 22. The transistor under test may be connected as a common base type or a common collector type to the curve tracer instead of a common emitter type as shown in FIG. 1. A voltage detector circuit 24 having a high input impedance detects a voltage VcE between the collector and the emittar of the transistor 18, divides the detected vol age bv an appropriate factor and applies the divided voltage through an amplifier 26 to a ~L Z L1~86~C~
horizontal de~lection plate of a cathode ray tube (CRT) 28 as a display device. A voltage detector circuit 30 having a high input impedance detects a voltage across the current detecting resistor 20 S corresponding to a collector current IC f the transistor 18 and applies the detected voltage through an amplifier 32 to a vertical deflectio~
plate of the CRT 28. Therefore, the VCE-Ic characteristic of the transistor 18 will be displayed on the CRT 28. It should be noted that a pure sine-wave volta~e consists of only one frequency component and does not apply noise to each of circuits of the measurement apparatus.
Moreover, it is easy-to design each the circuit of the measurement apparatus for the pure sine-wave voltage.
The conventional measurement apparatus as shown in FIG. 1 has many disadvantages. For example, the collector supply circuit 10 uses the external line voltage directly because the line voltage waveform is a substantial sine-wave.
Hoverever, the waveform of-the exter-.al line voltage is not the pure sine-wave, i~e., it is not ~z'~
a symmetrical repeat waveform and it includes various distortions. In other words, the repeat voltage waveform applied to the DUT is not the pure sine-wave or is not symmetrical, so that a forward trace of the characteristic curve displayed on the CRT 28 (during a rising period of the rectified sine-wave voltage) is different from a back trace thereof (during a falling period of the rectified sine-wave volta~e~, Thus, the characteristic of the DUT
cannot be measured exactly. This phenomenon is called a display distortion in this specification. Moreover, the peak amplitude of the line voltage is not correct and varies within a predetermined range. As a result of the variation, the peak amplitude of the repeat waveform voltage to be applied to the DUT varies in response to the line voltage and no correct measurement can be accomplished.
If a digital storage circuit is added to the measurement apparatus shown in FIG. 1 by inserting additional circuits between the voltage detector 24 and the amplifier 26 and between the voltage detector 30 and the amplifier 32, each oE
- s -the additional CiLCUitS consisting of an analog-to-digital converter, a digital memory and a digital-to~analog converter, the outputs from the analog-to-digital converters may be affected by a ripple of the power supply circuit since a clock frequency for the analog-to-digital converter is independent of the line voltage frequency. Therefore, the measurement accuracy may decrease. For synchronizing the clock frequency for the analog-to-digital converter with the ].ine voltage frequency, an additional phase control circuit may be needed and the measurement apparatus ma.y be expensive.
SUMMARY OF THE INVENTION
_____..__________________ In accordance with an aspect of the invention there .is provided a sine-wave generator for providing a sine-wave voltage, including a variable frequency signal generator; a frequency divider for producing a plurality of divided output signals by dividing an output frequency of said variable fre~uency signal generator; connection means for providing AC
line voltage; a phase comparator for comparing the lowest frequency divided output signal from said frequency divider with the AC line voltage and controlling an oscillation frequency of said variable frequency signal generator in response to the comparison result; converter means for converting an input signal into the sine-wave voltage in response to the divided output signals from said frequency divider; and a voltage comparator for comparing a voltage corresponding to the sine~wave voltage from said converter means with a reference voltage so as to generate the input signal ~o said converter means; wherein the sine-wave voltage from said converter means has the same frequency as the AC
line voltage and is synchronized with the AC line voltage.
Since the repeat waveform generator regenerates the repeat waveform voltage, such as a sine-wave voltage, this voltage waveform is symmetrical and does not include a distortion component in comparison with the line voltage wave-form. Thus, the display distortion can be improved. The re-generated repeat waveform voltage is independent from the line voltage, so that the repeat waveform voltage is not affected by the peak voltage variation of the line voltage and acorrect measurement will be accomplished~ since the repeat ~2~8~
waveform voltage rom the repeat wa~eform generator is in phase with the line voltage because of the pulse generating means and the frequency divider, each circuit to receive the repeat waveform voltage is not affected by the ripple, the phase variation, etc. of the line voltage.
The measurement apparatus of this invention may further include a analog-to-digitaL
converter means for converting the voltage across the DUT and the current flowing through the DUT
into digital signals in response to the o~tput pulse from the pulse generating means or the frequency divider and a memory circuit for storing the digital output signals from the analog-to-digital converter means. In this instance, theanalog-to-digital converter means is not affected by the variation of the line voltage because the means samples the voltage and current of the DUT in synchronism with the line voltage. Moreover, the output signals f_om the pulse generating means and the fre~uency divider can be used for both the repeat waveform senera~or anc the analog-to-digital converter, so that the measurement apparatus ~2'~
becomes simple and inexpensive in construction.
It is, therefore, an object of the present invention to provide an apparatus which measures characteristics of electronic devices accurately.
It is another object of the present invention to provide an electronic device measurement apparatus which can eliminate distortion from a displayed characteristic curve of a DUT.
It is a further object of the present invention to provide an electronic device measurement apparatus which eliminates af~ections of a line voltage from a digitizing circuit of the apparatus.
It is an additional object of the present invention to provide a repeat waveform generator which generates a symmetrical and stable waveform voltage repeatedly.
DRA~I~GS
________ The present invention taken in conjllnction with the invention disclosed in copending Canadian Patent Application Serial ~o. ~91,897 which was Eiled on September 30, 1985 will be described in detail hereinbelow with the aid of the accompanying drawings, in which:
~8~
FIG. 1 sho~s a block diagram of a conventional electronic device measurement apparatus;
FIG, 2 shows a circuit diagram of a part of a first preEerred embodiment according to the present invention for explaining a repeat waveform voltage generator employed therein;
FIG. 3 shows a time chart for explaining an operation of the repeat waveform voltage generator shown in FIG. 2;
FIG. 4 shows a block diagram of a part of a second preferred embodiment according to the present invention wherein the first embodiment is applied to an electronic device measurement apparatus having a digital storage function; and FIG~ 5 shows a block diagram of another part of the second embodiment according to the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG. 2, there is shown a circuit diagram of a part of a first preferred embodiment according to the present invention. An AC line voltage is applied through a power switch 34 to a primary winding of a transformer 40 provided in a power supply circuit 36. A plurality of secondary windings of the transformer 40 are connected to DC voltage regulator circuits (not shown) of the power supply circuit 36 for generating regulated DC voltages for each of circuits in the electronic device measurement apparatus. An AC voltge across the lowest position secondary winding of the transformer 40 is divided by resistors 42 and 44. A voltage comparator 46 compares the divided AC voltage with ground voltage for generating a pulse signal fL whose level is inverted every time when the line voltage crosses ground voltage~ It should be noted that this pulse siynal fL is a reference signal having the same --ll--frequency and phase as -the line voltage An oscillation frequency of a variable frequency oscillator (voltage control oscillator:VC0) 50 is 2n (n: positive integer) times as many as the pulse signal fL, e.g., 4096 (-212) times as many as tha pulse signal fL~ An output signal (4096 fL) from the VC0 50 is applied to a clock terminal of a counter 52 operating as a frequency divider. The frequency divider 52 divides the frequency of the output signal from the VC0 50 so as to genereate signals 16f, 8f, 4f, 2f and f whose frequencies are sixteen, eight, four, two and one times as many as the pulse signal fL, .
respectively. Bars of "16f", "8f", "4f" and "2f"
represent that the signals are inverted in phase with respect to the input signal to the fre~quency divider 5Z. A phase comparator 48 compares the phase of the pulse signal fL with that of the output pulse signal f from the frequency divider 52 and controls the oscillation f~equency of the VC0 50 such that the phases of the pulse signals fL and f are equal to each o.her. Thus, a phase lock loop consists of the phase compara-tor 48, the vC0 50 and ~2~8~0~
the frequency divider 52, and each of the output oulses from the frequency divider 52 is synchronized with the AC line voltage.
An encoder circuit for encoding the output pulses from the frequency divider 52 includes four exclusive OR (XOR) gates 54-60, wherein the XOR gate 54 receives the pulse signal 16f and 2f, the XOR gate 56 receives the pulse signals 8f and 2f, the XOR gate 58 receives the pulse signals 4f and 2f, and the XOR gate 60 receives the pulse signals 2f and f. Thus, the phase of the output pulse signal S from the XOR
gate 60 is delayed by ninety degrees with respect to the pulse signal f, namely, the fL, and the output pulses A-C therefrom construct a three-bit digital signal changing sequentially from "000" to "111" and from "111" to "000" every ninety degrees (a quarter period) or the pulse signal S. A phase relation of these signals is shown in FIG. 3.
An analog multiplexer (MUX) 62 as a first selec-tor means connects an input terminal I
to one of output terminals 0-7 selectively in response to the digital signals ~-C from the xorl gates 54-58. In other words, the output terminal 0 is selected when the signals a-t the selection terminals A-C are "000", the output terminal 1 is selected under "001", and the output terminal 2 is selected under "010". Similary, the output terminals 3, 4, 5, 6 and 7 are selected respectively under "011", "100", "110" and "111.
The output terminals 0-7 of the multiplexer 62 are respectively connected to one terminals of resistors 64-78 with the other terminals being connected to an input terminal of an integrator.
This integrator comprises an operational amplifier 80 with a grounded non-inverting input terminal and a capacitor 82 connected between an inverting input terminal and an output terminal of the operational amplifier 80. Thus, the integrator is the Miller integrator whose input resistor is the one of ths resistors 64-78 selected by the multiplexsr 62.
For example, the values of the resistors 64-78 are respec'ively 15.0 K-ohm, 16.9 K--ohm, 19.1 K-ohm, 23.7 X-ohm, 31.6 K-ohm, 51.1 K-ohm and 15.4 K-ohm, and the value of the capacitor 82 is 0.1~ F.
An ou~put signal Q from the integrator 86(~
is applied through a peak value detector to a voltage comparator 84. This peak detector consists of a diode 86, capacitor 88, resistors 90 and 92.
The voltage comparator 84 compares the peak value of the output signal Q from the integrator with a reference voltage VREF, and a difference output voltage therefrom is divided by resistors 94 and 96 and applied to an inverting amplifier 98 and a non-inverting amplifier 100. Values of an input resistor 102 and a feedback resistor 104 are equal to each other. OUtpl1t voltages from the amplifiers 98 and lO0 are applied to the input terminal I of the multiplexer 62 through an electronic switch 106 as a second selection means which is controlled by the pulse signal S. These circuit elements 54-82 and 106 construct a converter means.
As shown in FIG. 3, the switch 106 applies the output signal from the non-inve~ting amplifier 100 to the input-terminal I of the multiplexer 62 during the first quarter of the period between times To and Tl. Since this first quarter of the per o~ is d~vided by eight equally and the resis-tors 6~-78 are selected in sequence in accordance with the pulse signals A-C, the output signal Q from the integrator is a quarter of a sine-wave. In a term between times Tl and T2, the output voltage from the inverting amplifier 98 is applied to the input terminal I of the multiplexer 62. This term i5 divided by eight equally and the resistors 78-64 are selected in sequence. The circuit operates similarly as described hereinbefore and the output signal Q cf the integrator may be the repeat sine-wave voltage which is in phase with the line frequency signal.
Since the input voltage to the integrator is controlled by the peak detector 86-92 and the voltage comparator 84 so as to maintain the peak amplitude of the sine-wave voltage Q constant, this amplitude may not be affected by the variation of the frequency and amplitude of the line voltage.
The output voltage Q from the integrator is applied to the primary winding of the 20 transformer 12 through an electronic switch 108 and a variable gain amplifier (including a low pass filter for eliminating harmonic dis~ortion) 110.
The following s~ge of the secondary winding of the ~2'~36~
transformer 12 may be the same as the circuit shown in FIG. 1. In the circuit of FIG. 2, comparators 112 and 114 compare the output voltage from the phase comparator 48 with reference voltages divided by resistors 116-120. In other words, the comparator 112 determines whether the output voltage from the phase comparator 48 is lower than a predetermined upper limit voltage or not, and the comparator 114 determines whether the output voltage from the phase comparator 48 is higher than a predetermined lower limit voltage or not. When the output voltage from the phase comparator 48 is equal to or higher than the predetermined lower limit voltage and equal to or lower than the predetermined upper limit voltage, the switch 108 selects the amplifier 80. In the other instance, the switch 108 selects ground. Thus, when the phase difference between the sine-wave voltage Q
generated by the converter means and the line voltage is larger than a predetermined value, the sine-wave voltage Q is inAibit~ed to be applied to the follwoing st~ge for avoidinc an uncorrected measurement.
~'~4~
In the circuit of FIG. 2, the front stage of the voltage comparator 84 may be an average detector or a RMS (root-mean-square) detector instead of the peak detector. The inverting and non-inverting output signals from the voltage comparator 84 may be applied directly to the switch 106. Moreover, ona cycle of the sine-wave voltage Q may consist of more components than thirtytwo components by increasing a number of the resistors in the converter means and modif~ing the cons*ructions of the encoder circuit 54-60 and the multiplexer 62.
As understood from the foregoing discussion, the present invention can generate the sine-wave voltage having less distortion and the predetermined amplitude in synchronism with the line voltage reyardless of the line voltage waveform. Thus, the invention can eliminate the display distortion, is not afiected by the line voltage ri.pple and can measure the electronic device accuratly.
FIGs. 4 and 5 are block diagrams cf a second embodiment according to the present ~z'~o~
invention wherein the circuit of FIG. 5 receives output signals from the circuit of FIG. 4 and the electronic device measurement appartus consists o f the circuits of FIGs. 4 and 5. This second embodiment is that a digital storage function is applied to the first embodiment shown in FIG. 2.
Constructions and operations of circuit elements and blocks 34 through 52 are the same as the elements and blocks indicated by the corresponding reference numbers in FIG. 2, but the frequency divider 52 further generates a pulse signal 2048f having a half frequency of the output pulse from the VC0 50. A repeat waveform generator 154 corresponds to the generator consisting of the circuit elements 54 through 106 shown in FIG. 2.
Thus, the repeat waveform generator 154 generates the sine-wave voltage having the same frequency and phase as -the AC line voltge and the constant amplitude regardless of the amplitude of the AC
line voltage.
The sine-wave voltage from the repeat wave_orm generator 154 is applied to the primary wind_ng of the transformer 12 through the~r~able gain amplifier 156 or an appropriate analog multiplier. The secondary winding side of the transformer 12 is similar to the prior art shown in FIG. 1 wherein a selector/rectifier circuit 14 includes the switch and the diode. The selector/rectifier circuit 14 selects one of the taps of the secondary winding and rectifies the sine-wave voltage from the selected tap. The rectified voltage from the selector/rectifier circuit 14 is applied through the limiter resistor 16 to the collector of the transistor 18 as the DUT. The transformer 12 and selector/rectifier circuit 14 act as a voltage supply means. The lowest position terminal of the secondary winding of the transformer 12 is connected through the current detecting resistor 20 to the grounded emitter of the transistor 18. The base of the transistor 18 receives the bias signal from the bias supply circuit 22 which changes as a step pulse in synchronism with the output pulse f from the frequency divider 52. The transistor 18 unde_ tes' is co~nected as the common-emitte_ tvpe to the electronic device measruement apparatus, namely, ~1 2~ 0 the curve tracer in FIG. 4, however, it may be connected as the common base type or the common collector type. A voltage detector circuit 124 having a high input impedance detects the collector-emitter voltage VcE of the transistor 18 and divides the detect~d voltage VcE by an appropriate factor. A voltage detector circuit 130 having a high input impe~ance detects the voltage across the resistor 20, namely, the collector current Ic. The voltage detector circuit 124 may consist of the switch, the voltage dividers and the buffer amplifier, and the voltage detector circuit 130 may be the differential amplifier.
This embodiment of the present invention includes an analog-to-digital (A/D) converter means for converting the voltages detected by the voltage detectors 124 and 130 into digital signals. It should be noted that the detector 130 detects the current converted to the voltage. The A/D
converter means may consist of sample/hold (S/H) circuits and an A/D converter. The sample/hold circuits 15~ and 160 respec-ively sample the output voltages from the voltage detectors 124 and 130 and 1;Z~8~
hold the sampled voltages in response to the output pulse 1024f from the frequency divider 52. Since one period of the sine-wave voltage from the repeat waveform generator 154 is 1/f, the sample/hold circuits 158 and 160 sample 1024 points within the one period. An electronic switch 162 selects the sample/hold circuits 158 and 160 alternately every a half period of the output pulse 1024f from the freque~gy)divider-52, and the output signal from the switch 162 is applied to the A/D converter 164.
Since the switch 162 selects the sample/hold circuits 158 and 160 alternately, the A/D converter 164 receives as a clock signal the output pulse Z048f (having a double frequency of the pulse ___ 1024f) from the frequency divider 52 and converts the analog voltages from the sample/hold circuit 158 and 160 alternately into the digital signals.
It sould be not0d that both the pulse 102~f and 2048f are synchronized with the AC line voltage.
Z0 The digital output signal from the A/D
converter 164 is stored in a memory circuit 166 of FIG. 5 in accordance wit:~ an address signal from a control circuit 16a. T~e ccntrol circu~it 168 :~L2 L~8600 controls a writing mode and a reading mode of the memory circuit 166, generates a writing address signal in the writing mode by counting the output pulse 2048f from the voltage divider SZ and generates a reading address signal in the reading mode by counting a clock signal from a readout clock generator 170. Thus, the output signal (V
from the sample/hold circuit 158 is stored in, for example, odd address locations of the memory circuit^l66 and the output signal (Ic) from the sample/hold circuit 160 is stored in, for example, even address locations thereof in the writing mode.
As described hereinbefore, the voltage applied to the DUT 18 is in phase with the AC line voltage but the amplitude and the waveform thereof are independent of the AC line voltage. In addition, the sample/hold circuits 15~ and 160, the electronic switch 162 and the A/D converter 164 operate in synchronism with the AC line voltage.
Consequently, the memory circuit 166 stores the digital values representing the characteristics o~
the DUT without be ng affected by the voltage and/or phase variat~on of the line voltage and -the :~2~
waveform -thereof.
In the reading mode, a latch circuit 172 latches the contents of the even address locations of the memory circuit 166 sequentially in response to the LSB (Least Significant Bit) of the address signal, and a latch circul-t 174 latches the contents of the odd address locations of the memory circuit 166 sequentially in response to the LSB of the address signal inverted by an inverter 176.
Since a latch circuit 178 latches the contents o the latch circuit 172 simultaneously with the latch operation of the latch circuit 174, digital-to-analog (D/A) converters 180 and 182 simultaneously receive the digital value Ic of the latch circuit 178 and the digital value VcE of the latch circuit 174, respectively and convert them into analog signals. These analog signals are applied to the vertical and horizontal deflection plates of the CRT 28 through amplifiers 26 and 32 for displaying the Ic-VcE characteristic of the DUT 18. The digital signal read from the memory circuit 166 mzy be applied to a comou~ar or the like for p~ocessins it.
~Z~36~
While I have shown and described herein the preferred embodiments of my invention, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from our invention in its broader aspects. Therefore, the scope of the present invention should be determined only by the following claims.
Sine-__ve ~e__rator This is a division of copending Canadian Patent Application Serial No~ 491,897 which was filed on September 30, 1985.
BACKGROUND_OF TH:E_INVENTION
The present invention relates to an apparatus for measuring characteristics of electronic devices, such as transistors, diodes, etc~
An electronic device measurement apparatus called generally a curve tracer is useful to measure characteristics of electronic devices, such as transistors, diodes, etc.
A typical one of conventional electronic device measure-ment apparatus is .illustrated in FIG. 1., wherein a collector voltage suppl.y circuit 10 includes a variable transformer for increasing or decreasing an AC voltage from an external line voltage source so as to obtain a sine-wave voltage having a desired amplitude. rrhe sine-wave voltage is applied to a primary winding of a trans~ormer 12 which includes a secondary winding having a ~,g 36g~
plurality of taps. A selector/rectifier circuit 14 selects one of the taps in accordance with a measurement range and rectifies the sine-wave voltage from the selected tap. The rectified voltage from the selector/rectifier circuit 14 is applied through a limiter resistor 16 to a collector of a transistor 18 as a device under test(DUT). The value of 'che resistor 16 is changed in accordance with the measurement range. The lowest terminal of the secondary winding of the transformer 12 is connected through a current detectin~ resistor 20 to an emitter o the transistor 18 which is grounded~ A base of the transistor 18 receives a step bias signal from a bias supply circuit 22. The transistor under test may be connected as a common base type or a common collector type to the curve tracer instead of a common emitter type as shown in FIG. 1. A voltage detector circuit 24 having a high input impedance detects a voltage VcE between the collector and the emittar of the transistor 18, divides the detected vol age bv an appropriate factor and applies the divided voltage through an amplifier 26 to a ~L Z L1~86~C~
horizontal de~lection plate of a cathode ray tube (CRT) 28 as a display device. A voltage detector circuit 30 having a high input impedance detects a voltage across the current detecting resistor 20 S corresponding to a collector current IC f the transistor 18 and applies the detected voltage through an amplifier 32 to a vertical deflectio~
plate of the CRT 28. Therefore, the VCE-Ic characteristic of the transistor 18 will be displayed on the CRT 28. It should be noted that a pure sine-wave volta~e consists of only one frequency component and does not apply noise to each of circuits of the measurement apparatus.
Moreover, it is easy-to design each the circuit of the measurement apparatus for the pure sine-wave voltage.
The conventional measurement apparatus as shown in FIG. 1 has many disadvantages. For example, the collector supply circuit 10 uses the external line voltage directly because the line voltage waveform is a substantial sine-wave.
Hoverever, the waveform of-the exter-.al line voltage is not the pure sine-wave, i~e., it is not ~z'~
a symmetrical repeat waveform and it includes various distortions. In other words, the repeat voltage waveform applied to the DUT is not the pure sine-wave or is not symmetrical, so that a forward trace of the characteristic curve displayed on the CRT 28 (during a rising period of the rectified sine-wave voltage) is different from a back trace thereof (during a falling period of the rectified sine-wave volta~e~, Thus, the characteristic of the DUT
cannot be measured exactly. This phenomenon is called a display distortion in this specification. Moreover, the peak amplitude of the line voltage is not correct and varies within a predetermined range. As a result of the variation, the peak amplitude of the repeat waveform voltage to be applied to the DUT varies in response to the line voltage and no correct measurement can be accomplished.
If a digital storage circuit is added to the measurement apparatus shown in FIG. 1 by inserting additional circuits between the voltage detector 24 and the amplifier 26 and between the voltage detector 30 and the amplifier 32, each oE
- s -the additional CiLCUitS consisting of an analog-to-digital converter, a digital memory and a digital-to~analog converter, the outputs from the analog-to-digital converters may be affected by a ripple of the power supply circuit since a clock frequency for the analog-to-digital converter is independent of the line voltage frequency. Therefore, the measurement accuracy may decrease. For synchronizing the clock frequency for the analog-to-digital converter with the ].ine voltage frequency, an additional phase control circuit may be needed and the measurement apparatus ma.y be expensive.
SUMMARY OF THE INVENTION
_____..__________________ In accordance with an aspect of the invention there .is provided a sine-wave generator for providing a sine-wave voltage, including a variable frequency signal generator; a frequency divider for producing a plurality of divided output signals by dividing an output frequency of said variable fre~uency signal generator; connection means for providing AC
line voltage; a phase comparator for comparing the lowest frequency divided output signal from said frequency divider with the AC line voltage and controlling an oscillation frequency of said variable frequency signal generator in response to the comparison result; converter means for converting an input signal into the sine-wave voltage in response to the divided output signals from said frequency divider; and a voltage comparator for comparing a voltage corresponding to the sine~wave voltage from said converter means with a reference voltage so as to generate the input signal ~o said converter means; wherein the sine-wave voltage from said converter means has the same frequency as the AC
line voltage and is synchronized with the AC line voltage.
Since the repeat waveform generator regenerates the repeat waveform voltage, such as a sine-wave voltage, this voltage waveform is symmetrical and does not include a distortion component in comparison with the line voltage wave-form. Thus, the display distortion can be improved. The re-generated repeat waveform voltage is independent from the line voltage, so that the repeat waveform voltage is not affected by the peak voltage variation of the line voltage and acorrect measurement will be accomplished~ since the repeat ~2~8~
waveform voltage rom the repeat wa~eform generator is in phase with the line voltage because of the pulse generating means and the frequency divider, each circuit to receive the repeat waveform voltage is not affected by the ripple, the phase variation, etc. of the line voltage.
The measurement apparatus of this invention may further include a analog-to-digitaL
converter means for converting the voltage across the DUT and the current flowing through the DUT
into digital signals in response to the o~tput pulse from the pulse generating means or the frequency divider and a memory circuit for storing the digital output signals from the analog-to-digital converter means. In this instance, theanalog-to-digital converter means is not affected by the variation of the line voltage because the means samples the voltage and current of the DUT in synchronism with the line voltage. Moreover, the output signals f_om the pulse generating means and the fre~uency divider can be used for both the repeat waveform senera~or anc the analog-to-digital converter, so that the measurement apparatus ~2'~
becomes simple and inexpensive in construction.
It is, therefore, an object of the present invention to provide an apparatus which measures characteristics of electronic devices accurately.
It is another object of the present invention to provide an electronic device measurement apparatus which can eliminate distortion from a displayed characteristic curve of a DUT.
It is a further object of the present invention to provide an electronic device measurement apparatus which eliminates af~ections of a line voltage from a digitizing circuit of the apparatus.
It is an additional object of the present invention to provide a repeat waveform generator which generates a symmetrical and stable waveform voltage repeatedly.
DRA~I~GS
________ The present invention taken in conjllnction with the invention disclosed in copending Canadian Patent Application Serial ~o. ~91,897 which was Eiled on September 30, 1985 will be described in detail hereinbelow with the aid of the accompanying drawings, in which:
~8~
FIG. 1 sho~s a block diagram of a conventional electronic device measurement apparatus;
FIG, 2 shows a circuit diagram of a part of a first preEerred embodiment according to the present invention for explaining a repeat waveform voltage generator employed therein;
FIG. 3 shows a time chart for explaining an operation of the repeat waveform voltage generator shown in FIG. 2;
FIG. 4 shows a block diagram of a part of a second preferred embodiment according to the present invention wherein the first embodiment is applied to an electronic device measurement apparatus having a digital storage function; and FIG~ 5 shows a block diagram of another part of the second embodiment according to the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG. 2, there is shown a circuit diagram of a part of a first preferred embodiment according to the present invention. An AC line voltage is applied through a power switch 34 to a primary winding of a transformer 40 provided in a power supply circuit 36. A plurality of secondary windings of the transformer 40 are connected to DC voltage regulator circuits (not shown) of the power supply circuit 36 for generating regulated DC voltages for each of circuits in the electronic device measurement apparatus. An AC voltge across the lowest position secondary winding of the transformer 40 is divided by resistors 42 and 44. A voltage comparator 46 compares the divided AC voltage with ground voltage for generating a pulse signal fL whose level is inverted every time when the line voltage crosses ground voltage~ It should be noted that this pulse siynal fL is a reference signal having the same --ll--frequency and phase as -the line voltage An oscillation frequency of a variable frequency oscillator (voltage control oscillator:VC0) 50 is 2n (n: positive integer) times as many as the pulse signal fL, e.g., 4096 (-212) times as many as tha pulse signal fL~ An output signal (4096 fL) from the VC0 50 is applied to a clock terminal of a counter 52 operating as a frequency divider. The frequency divider 52 divides the frequency of the output signal from the VC0 50 so as to genereate signals 16f, 8f, 4f, 2f and f whose frequencies are sixteen, eight, four, two and one times as many as the pulse signal fL, .
respectively. Bars of "16f", "8f", "4f" and "2f"
represent that the signals are inverted in phase with respect to the input signal to the fre~quency divider 5Z. A phase comparator 48 compares the phase of the pulse signal fL with that of the output pulse signal f from the frequency divider 52 and controls the oscillation f~equency of the VC0 50 such that the phases of the pulse signals fL and f are equal to each o.her. Thus, a phase lock loop consists of the phase compara-tor 48, the vC0 50 and ~2~8~0~
the frequency divider 52, and each of the output oulses from the frequency divider 52 is synchronized with the AC line voltage.
An encoder circuit for encoding the output pulses from the frequency divider 52 includes four exclusive OR (XOR) gates 54-60, wherein the XOR gate 54 receives the pulse signal 16f and 2f, the XOR gate 56 receives the pulse signals 8f and 2f, the XOR gate 58 receives the pulse signals 4f and 2f, and the XOR gate 60 receives the pulse signals 2f and f. Thus, the phase of the output pulse signal S from the XOR
gate 60 is delayed by ninety degrees with respect to the pulse signal f, namely, the fL, and the output pulses A-C therefrom construct a three-bit digital signal changing sequentially from "000" to "111" and from "111" to "000" every ninety degrees (a quarter period) or the pulse signal S. A phase relation of these signals is shown in FIG. 3.
An analog multiplexer (MUX) 62 as a first selec-tor means connects an input terminal I
to one of output terminals 0-7 selectively in response to the digital signals ~-C from the xorl gates 54-58. In other words, the output terminal 0 is selected when the signals a-t the selection terminals A-C are "000", the output terminal 1 is selected under "001", and the output terminal 2 is selected under "010". Similary, the output terminals 3, 4, 5, 6 and 7 are selected respectively under "011", "100", "110" and "111.
The output terminals 0-7 of the multiplexer 62 are respectively connected to one terminals of resistors 64-78 with the other terminals being connected to an input terminal of an integrator.
This integrator comprises an operational amplifier 80 with a grounded non-inverting input terminal and a capacitor 82 connected between an inverting input terminal and an output terminal of the operational amplifier 80. Thus, the integrator is the Miller integrator whose input resistor is the one of ths resistors 64-78 selected by the multiplexsr 62.
For example, the values of the resistors 64-78 are respec'ively 15.0 K-ohm, 16.9 K--ohm, 19.1 K-ohm, 23.7 X-ohm, 31.6 K-ohm, 51.1 K-ohm and 15.4 K-ohm, and the value of the capacitor 82 is 0.1~ F.
An ou~put signal Q from the integrator 86(~
is applied through a peak value detector to a voltage comparator 84. This peak detector consists of a diode 86, capacitor 88, resistors 90 and 92.
The voltage comparator 84 compares the peak value of the output signal Q from the integrator with a reference voltage VREF, and a difference output voltage therefrom is divided by resistors 94 and 96 and applied to an inverting amplifier 98 and a non-inverting amplifier 100. Values of an input resistor 102 and a feedback resistor 104 are equal to each other. OUtpl1t voltages from the amplifiers 98 and lO0 are applied to the input terminal I of the multiplexer 62 through an electronic switch 106 as a second selection means which is controlled by the pulse signal S. These circuit elements 54-82 and 106 construct a converter means.
As shown in FIG. 3, the switch 106 applies the output signal from the non-inve~ting amplifier 100 to the input-terminal I of the multiplexer 62 during the first quarter of the period between times To and Tl. Since this first quarter of the per o~ is d~vided by eight equally and the resis-tors 6~-78 are selected in sequence in accordance with the pulse signals A-C, the output signal Q from the integrator is a quarter of a sine-wave. In a term between times Tl and T2, the output voltage from the inverting amplifier 98 is applied to the input terminal I of the multiplexer 62. This term i5 divided by eight equally and the resistors 78-64 are selected in sequence. The circuit operates similarly as described hereinbefore and the output signal Q cf the integrator may be the repeat sine-wave voltage which is in phase with the line frequency signal.
Since the input voltage to the integrator is controlled by the peak detector 86-92 and the voltage comparator 84 so as to maintain the peak amplitude of the sine-wave voltage Q constant, this amplitude may not be affected by the variation of the frequency and amplitude of the line voltage.
The output voltage Q from the integrator is applied to the primary winding of the 20 transformer 12 through an electronic switch 108 and a variable gain amplifier (including a low pass filter for eliminating harmonic dis~ortion) 110.
The following s~ge of the secondary winding of the ~2'~36~
transformer 12 may be the same as the circuit shown in FIG. 1. In the circuit of FIG. 2, comparators 112 and 114 compare the output voltage from the phase comparator 48 with reference voltages divided by resistors 116-120. In other words, the comparator 112 determines whether the output voltage from the phase comparator 48 is lower than a predetermined upper limit voltage or not, and the comparator 114 determines whether the output voltage from the phase comparator 48 is higher than a predetermined lower limit voltage or not. When the output voltage from the phase comparator 48 is equal to or higher than the predetermined lower limit voltage and equal to or lower than the predetermined upper limit voltage, the switch 108 selects the amplifier 80. In the other instance, the switch 108 selects ground. Thus, when the phase difference between the sine-wave voltage Q
generated by the converter means and the line voltage is larger than a predetermined value, the sine-wave voltage Q is inAibit~ed to be applied to the follwoing st~ge for avoidinc an uncorrected measurement.
~'~4~
In the circuit of FIG. 2, the front stage of the voltage comparator 84 may be an average detector or a RMS (root-mean-square) detector instead of the peak detector. The inverting and non-inverting output signals from the voltage comparator 84 may be applied directly to the switch 106. Moreover, ona cycle of the sine-wave voltage Q may consist of more components than thirtytwo components by increasing a number of the resistors in the converter means and modif~ing the cons*ructions of the encoder circuit 54-60 and the multiplexer 62.
As understood from the foregoing discussion, the present invention can generate the sine-wave voltage having less distortion and the predetermined amplitude in synchronism with the line voltage reyardless of the line voltage waveform. Thus, the invention can eliminate the display distortion, is not afiected by the line voltage ri.pple and can measure the electronic device accuratly.
FIGs. 4 and 5 are block diagrams cf a second embodiment according to the present ~z'~o~
invention wherein the circuit of FIG. 5 receives output signals from the circuit of FIG. 4 and the electronic device measurement appartus consists o f the circuits of FIGs. 4 and 5. This second embodiment is that a digital storage function is applied to the first embodiment shown in FIG. 2.
Constructions and operations of circuit elements and blocks 34 through 52 are the same as the elements and blocks indicated by the corresponding reference numbers in FIG. 2, but the frequency divider 52 further generates a pulse signal 2048f having a half frequency of the output pulse from the VC0 50. A repeat waveform generator 154 corresponds to the generator consisting of the circuit elements 54 through 106 shown in FIG. 2.
Thus, the repeat waveform generator 154 generates the sine-wave voltage having the same frequency and phase as -the AC line voltge and the constant amplitude regardless of the amplitude of the AC
line voltage.
The sine-wave voltage from the repeat wave_orm generator 154 is applied to the primary wind_ng of the transformer 12 through the~r~able gain amplifier 156 or an appropriate analog multiplier. The secondary winding side of the transformer 12 is similar to the prior art shown in FIG. 1 wherein a selector/rectifier circuit 14 includes the switch and the diode. The selector/rectifier circuit 14 selects one of the taps of the secondary winding and rectifies the sine-wave voltage from the selected tap. The rectified voltage from the selector/rectifier circuit 14 is applied through the limiter resistor 16 to the collector of the transistor 18 as the DUT. The transformer 12 and selector/rectifier circuit 14 act as a voltage supply means. The lowest position terminal of the secondary winding of the transformer 12 is connected through the current detecting resistor 20 to the grounded emitter of the transistor 18. The base of the transistor 18 receives the bias signal from the bias supply circuit 22 which changes as a step pulse in synchronism with the output pulse f from the frequency divider 52. The transistor 18 unde_ tes' is co~nected as the common-emitte_ tvpe to the electronic device measruement apparatus, namely, ~1 2~ 0 the curve tracer in FIG. 4, however, it may be connected as the common base type or the common collector type. A voltage detector circuit 124 having a high input impedance detects the collector-emitter voltage VcE of the transistor 18 and divides the detect~d voltage VcE by an appropriate factor. A voltage detector circuit 130 having a high input impe~ance detects the voltage across the resistor 20, namely, the collector current Ic. The voltage detector circuit 124 may consist of the switch, the voltage dividers and the buffer amplifier, and the voltage detector circuit 130 may be the differential amplifier.
This embodiment of the present invention includes an analog-to-digital (A/D) converter means for converting the voltages detected by the voltage detectors 124 and 130 into digital signals. It should be noted that the detector 130 detects the current converted to the voltage. The A/D
converter means may consist of sample/hold (S/H) circuits and an A/D converter. The sample/hold circuits 15~ and 160 respec-ively sample the output voltages from the voltage detectors 124 and 130 and 1;Z~8~
hold the sampled voltages in response to the output pulse 1024f from the frequency divider 52. Since one period of the sine-wave voltage from the repeat waveform generator 154 is 1/f, the sample/hold circuits 158 and 160 sample 1024 points within the one period. An electronic switch 162 selects the sample/hold circuits 158 and 160 alternately every a half period of the output pulse 1024f from the freque~gy)divider-52, and the output signal from the switch 162 is applied to the A/D converter 164.
Since the switch 162 selects the sample/hold circuits 158 and 160 alternately, the A/D converter 164 receives as a clock signal the output pulse Z048f (having a double frequency of the pulse ___ 1024f) from the frequency divider 52 and converts the analog voltages from the sample/hold circuit 158 and 160 alternately into the digital signals.
It sould be not0d that both the pulse 102~f and 2048f are synchronized with the AC line voltage.
Z0 The digital output signal from the A/D
converter 164 is stored in a memory circuit 166 of FIG. 5 in accordance wit:~ an address signal from a control circuit 16a. T~e ccntrol circu~it 168 :~L2 L~8600 controls a writing mode and a reading mode of the memory circuit 166, generates a writing address signal in the writing mode by counting the output pulse 2048f from the voltage divider SZ and generates a reading address signal in the reading mode by counting a clock signal from a readout clock generator 170. Thus, the output signal (V
from the sample/hold circuit 158 is stored in, for example, odd address locations of the memory circuit^l66 and the output signal (Ic) from the sample/hold circuit 160 is stored in, for example, even address locations thereof in the writing mode.
As described hereinbefore, the voltage applied to the DUT 18 is in phase with the AC line voltage but the amplitude and the waveform thereof are independent of the AC line voltage. In addition, the sample/hold circuits 15~ and 160, the electronic switch 162 and the A/D converter 164 operate in synchronism with the AC line voltage.
Consequently, the memory circuit 166 stores the digital values representing the characteristics o~
the DUT without be ng affected by the voltage and/or phase variat~on of the line voltage and -the :~2~
waveform -thereof.
In the reading mode, a latch circuit 172 latches the contents of the even address locations of the memory circuit 166 sequentially in response to the LSB (Least Significant Bit) of the address signal, and a latch circul-t 174 latches the contents of the odd address locations of the memory circuit 166 sequentially in response to the LSB of the address signal inverted by an inverter 176.
Since a latch circuit 178 latches the contents o the latch circuit 172 simultaneously with the latch operation of the latch circuit 174, digital-to-analog (D/A) converters 180 and 182 simultaneously receive the digital value Ic of the latch circuit 178 and the digital value VcE of the latch circuit 174, respectively and convert them into analog signals. These analog signals are applied to the vertical and horizontal deflection plates of the CRT 28 through amplifiers 26 and 32 for displaying the Ic-VcE characteristic of the DUT 18. The digital signal read from the memory circuit 166 mzy be applied to a comou~ar or the like for p~ocessins it.
~Z~36~
While I have shown and described herein the preferred embodiments of my invention, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from our invention in its broader aspects. Therefore, the scope of the present invention should be determined only by the following claims.
Claims (3)
1. A sine-wave generator for providing a sine-wave voltage, including:
a variable frequency signal generator;
a frequency divider for producing a plurality of divided output signals by dividing an output frequency of said variable frequency signal generator;
connection means for providing AC line voltage;
a phase comparator for comparing the lowest frequency divided output signal from said frequency divider with the AC line voltage and controlling an oscillation frequency of said variable frequency signal generator in response to the comparison result;
converter means for converting an input signal into the sine-wave voltage in response to the divided output signals from said frequency divider; and a voltage comparator for comparing a voltage corresponding to the sine-wave voltage from said converter means with a reference voltage so as to generate the input signal to said converter means;
wherein the sine-wave voltage from said converter means has the same frequency as the AC line voltage and is synchronized with the AC line voltage.
a variable frequency signal generator;
a frequency divider for producing a plurality of divided output signals by dividing an output frequency of said variable frequency signal generator;
connection means for providing AC line voltage;
a phase comparator for comparing the lowest frequency divided output signal from said frequency divider with the AC line voltage and controlling an oscillation frequency of said variable frequency signal generator in response to the comparison result;
converter means for converting an input signal into the sine-wave voltage in response to the divided output signals from said frequency divider; and a voltage comparator for comparing a voltage corresponding to the sine-wave voltage from said converter means with a reference voltage so as to generate the input signal to said converter means;
wherein the sine-wave voltage from said converter means has the same frequency as the AC line voltage and is synchronized with the AC line voltage.
2. A sine-wave generator according to claim 1, wherein said converter means includes:
an encoder for encoding the divided output signals from said frequency divider;
a multiplexer having input and output terminals, said multiplexer connecting selectively an input terminal thereof to one of the output terminals thereof in response to output signals of said encoder, said input terminal receiving the input signal to said converter means;
a plurality of resistors having first terminals connected to the output terminals of said multiplexer, respectively; and an integrator having an input terminal connected to the other terminals of said plurality of resistors, the sine-wave voltage generating at an output terminal of said integrator.
an encoder for encoding the divided output signals from said frequency divider;
a multiplexer having input and output terminals, said multiplexer connecting selectively an input terminal thereof to one of the output terminals thereof in response to output signals of said encoder, said input terminal receiving the input signal to said converter means;
a plurality of resistors having first terminals connected to the output terminals of said multiplexer, respectively; and an integrator having an input terminal connected to the other terminals of said plurality of resistors, the sine-wave voltage generating at an output terminal of said integrator.
3. A sine-wave generator according to claim 1 further includes a peak detector connected between said converter means and said voltage comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000547089A CA1248600A (en) | 1984-10-04 | 1987-09-16 | Sine-wave generator |
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59-208792 | 1984-10-04 | ||
| JP59208791A JPS6187429A (en) | 1984-10-04 | 1984-10-04 | Generating circuit of repetitive voltage |
| JP59-208791 | 1984-10-04 | ||
| JP20879284A JPS6186664A (en) | 1984-10-04 | 1984-10-04 | Apparatus for measuring element |
| CA000491897A CA1242813A (en) | 1984-10-04 | 1985-09-30 | Apparatus for measuring characteristics of electronic devices |
| CA000547089A CA1248600A (en) | 1984-10-04 | 1987-09-16 | Sine-wave generator |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000491897A Division CA1242813A (en) | 1984-10-04 | 1985-09-30 | Apparatus for measuring characteristics of electronic devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1248600A true CA1248600A (en) | 1989-01-10 |
Family
ID=27167554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000547089A Expired CA1248600A (en) | 1984-10-04 | 1987-09-16 | Sine-wave generator |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1248600A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107291148A (en) * | 2016-03-31 | 2017-10-24 | 大唐恩智浦半导体有限公司 | Sinusoidal wave generating device |
-
1987
- 1987-09-16 CA CA000547089A patent/CA1248600A/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107291148A (en) * | 2016-03-31 | 2017-10-24 | 大唐恩智浦半导体有限公司 | Sinusoidal wave generating device |
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