CA1245731A - Failsafe decision circuit - Google Patents
Failsafe decision circuitInfo
- Publication number
- CA1245731A CA1245731A CA000452865A CA452865A CA1245731A CA 1245731 A CA1245731 A CA 1245731A CA 000452865 A CA000452865 A CA 000452865A CA 452865 A CA452865 A CA 452865A CA 1245731 A CA1245731 A CA 1245731A
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- Canada
- Prior art keywords
- output
- input
- circuit
- signal
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000000295 complement effect Effects 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 7
- 241000272470 Circus Species 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 230000008929 regeneration Effects 0.000 description 2
- 238000011069 regeneration method Methods 0.000 description 2
- 238000005513 bias potential Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
- H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
- H03K3/2885—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit the input circuit having a differential configuration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
- H03K17/603—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors with coupled emitters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/12—Shaping pulses by steepening leading or trailing edges
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/20—Repeater circuits; Relay circuits
- H04L25/24—Relay circuits using discharge tubes or semiconductor devices
- H04L25/242—Relay circuits using discharge tubes or semiconductor devices with retiming
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Dc Digital Transmission (AREA)
Abstract
ABSTRACT.
IMPROVEMENTS IN OR RELATING TO DECISION CIRCUITS.
A decision circuit (20) is responsive to digital input signals (22) and to timing signals (21) for reshaping and retiming the input signals into reshaped and retimed output signals. The decision circuit also is responsive to the digital input signals and absence of the timing signals for reshaping but not retiming the digital input signals into reshaped output signals which are transmitted. Thus the circuit produces and transmits reshaped output signals even upon failure to apply the timing signals as required by previous decision circuits.
IMPROVEMENTS IN OR RELATING TO DECISION CIRCUITS.
A decision circuit (20) is responsive to digital input signals (22) and to timing signals (21) for reshaping and retiming the input signals into reshaped and retimed output signals. The decision circuit also is responsive to the digital input signals and absence of the timing signals for reshaping but not retiming the digital input signals into reshaped output signals which are transmitted. Thus the circuit produces and transmits reshaped output signals even upon failure to apply the timing signals as required by previous decision circuits.
Description
~L2~3~
R.M. PASKI 2 IMPROVEMENTS IN OR RELATING TO DECISION CIRCUITS
This invention relates to decision circuits.
In the prior art a ~egenerator in a digital transmission system S extracts timing or clock signals from a received data stream. The extracted timing signals are used for controlling the regeneration, that is, the reshaping and retiming of data bits being received. The regenerator makes, for example, a binary decision concerning the amplitude of a received digital signal with respect to a predetermined threshold level at an optimum sampling instant. In response to the received data signal and the extracted timing signal9 a decision circuit in the regenerator reshapes and retimes the received signal into a regenerated, or reshaped and retimed, output signal. This regenerated output signal, with as little distortion as possible, is applied to a modulator for shaping an output signal to be transmitted further a~ong the transmisslon l~ne. If the timing e~traction arrangement fails for any reason, a problem arises ~n that the decision c~rcuit ceases to re~enerate the recelved data b~ts. No output signals are transmitted further along the line.
According to this invention a decision circuit includes means responsive to an input data signal and an input timing signal for reshaping and retiming the input data signals into reshaped and retimed output data signals, the means being responsive to the input data signal in the absence of an input timing signal for reshaping the input data signal into a reshaped but not retimed output data signal.
The invention will now be described by way of example with reference to the accompanying drawings, in which:
FIG. 1 is a block diagram of a decision circuit embodying the i invention;
FIG. 2 is a schematic diagram of a data quantizer used in the circuit of FIG. 1, FIG. 3 is a waveform showing an exemplary input data stream being applied to the quantizer of FIG. 2;
FIG. 4 is a waveform of a quantized version of the exemplary inpuk da~a stream o~ FIG. 3 which is being applied to the ~L~ 73 ~L
quantizer of FIG. 2;
FIG. 5 is a schematic diagram o~ a latch circuit used in the circuit of FIG. 1;
FIG. 6 is a waveform of a delayed, or regenerated, version of the quantized data stream;
FIG. 7 is a waveform of an output data stream produced by the decision circuit of FIG. 1, FIG. 8 is a clock quantizer circuit used in the decision circuit of FIG. 1;
FIG. 9 is a waveform of an input clock signal that is applied to the clock quantizer of FIG. 8;
FIG.10 is the quantized version of the input clock signal of FIG.
9;
FIG. 11 is an output clock signal produced by the clock quantizer of FIG. 8;
FIG. 12 is a schematic diagram of a multiplier circuit used in the circuit of FIG. 1;
FlG. 13 is a waveform of the output of the multlpl~er circuit used in the deciston circuit of FIG. 1;
FIG. 14 is a schematic diagram of a comparator circuit used in the circuit of FIG. 1; and FIG. 15 is a schematic diagram of a buffer circuit used in the circuit of FIG. 1.
Referring now to FIG. 1, a decision circuit 20 is responsive to either single-ended or balanced input signals applied to data input terminals 22, and also to recovered input clock, or timing, signals which are applied to input clock terminals 21. The decision circuit 20 is arranged for reshaping and retiming the Input data signals into regenerated output data signals which are produced on output data terminals 29.
Decision circuit 20 not only regenerates the input data signals during normal operation, but it also continues to produce an output data stream in the event that the recovered input clock signals are not applied to the circuit 20. Thus the decision circuit safely continues to produce a reshaped but not a retimed output 573~.
data stream when the clock, or timing, signals fail to be applied.
This is ver~ advantageous for use in a very long relatively inaccessible cable system requiring regeneration, such as in an undersea optical fiber transmission system.
The decision circuit includes a data quantizer 30, a delay flip-flop 40, and an output buffer 60 for reshaping and retiming the input data signals into the regenerated output data signals produced at output terminals 29. The output data signals are produced so that they are useable as either single-ended or balanced output signals.
The several circuit blocks are shown in greater detail in other figures of the drawing. h1so included in the decision circuit 20 are a clock quantizer 70, a multiplier 100, a low-pass filter l20, and a comparator 130 for retiming the input data signals when the clock pulse is being applied and for ensuring a continued reshaping of the input pulses when no timing pulses are applied.
Referring now to FIG. 2, the input data signals are applied to the data input terminals 22 of data quantizer 30. Quantized signals are produced on output terminals 23 of the data quantizer.
As shown in FIG. 3, a waveform represen-tative of an input data strearn is in a non-return~to-zero format having a Nyquist pulse shape.
Binary digits are presented in FIG. 3 to clearly define the binary data being represented by the waveform during the different time slot intervals.
In operation the data quantizer of FIG. 2 functions as two emitter-coupled pairs of transistors. An input pair of NPN
transistors 24 and 25 is biased to operate for full amplitude input signals in the nonlinear region of its characteristic curves without putting either of those transistors into saturation. The input pair of transistors produces at nodes 32 and 33 complementary signals which are applied to an output pair of PNP transistors 26 and 27.
Transistors 26 and 27 also are biased to operate in a nonlinear region of their characteristic curves without going into saturation.
FIG. 4 shows a waveform which is produced at the outp~t terminals 23 of the data quantizer 30 of FIG. 2 and which represents a quantiæed version of the input data stream. It is noted that some slight delays occur between the waveform of FIG. 3 and the waveform of FIG. 4.
Referring now to FIG. 5, balanced si~nals from the out-put terminals 23 of the data quantizer 30 of FIG. 2 are applied to input terminals 43 of a latch circuit 41 which is suitable for use for both the first latch circuit 41 and the second latch circuit 42 in the delay flip-flop 40 of FIG. 1.
There are three operating sections of the latch circuit 41. An input pair of emitter-coupled NPN transistors 44 and 45 has a nonlatch current I~ as its common emitter current source. Output transimpedance circuits including PNP tran-sistors 47 and 4~, which are opposite conductivity typedevices ~rom the input pair oE transistors, produce complementary ouptut siqnals on a pair Oe output terminals in response to the ~u~n~ize~ ver~ion of the input data stream. A latching pair o emitter-coupled NPN transistors 51 and 52 has a latch current IL as its common emitter current source. The arrangement and operation of the latch circuit 41 are disclosed in greater detail in Canadian Patent Application Serial No. ~53,139 which was filed on April 30, 1984.
Referring once again to FIG. 1, the second latch circuit 42, is similar to the first latch circuit 41 just described.
In the delay flip-flop 40, the signals produced on the output terminals o~ the ~irst latch circuit 41 are applied as bal-anced input signals to the input terminals o~ the second latch circuit 42. Output signals produced by the second latch circuit 42 also are the balanced output of the delay flip-flop 40. Because complementary bipolar transistors are used in the latching circuits, no level shifting circuitry is required.
- 4a _ ~2'`~73~
Referring now to FIG. 6, there is shown a waveform of the output bit stream from the delay flip-flop 40 of FIG. 1 in response to the stream of data bits applied from the out-put of the data quantizer 30 and in response to clock signals from the clock quantizer 70, to be described subsequently herein. It is noted that the quantized output is delayed a half of a bit time slot so that the input data signal, ~'~
~2~57;3~
applied to the delay flip-flop, is not directly available at the output terminals 55 of the delay flip-flop while the clock is running.
The output data stream from the delay fllp-flop 40 represents a reshaped and retimed version of the input data signals applied to the data input terminals 22.
Most of the time during operation of the dec;sion circuit 20~ a clock input signal is extracted from the received stream of data bits.
This clock input signal is applied to the input terminals 21 of the clock quantizer circuit 70 for the purpose of controlling the retiming of the output data signals which are produced by the delay flip-flop 40 of FIG. 1.
Referring now to FIG. 8, there is shown a schematic diagram of a clock quantizer circuit 70 that is suitable for use in the decision circuit 20. This circuit 70 is similar in many respects to the data quantizer of FIG. 2. The clock quantizer c~rcuit 70 of FIG. 8 ~ncludes an ~nput pair of emitter-coupled NPN trans~stors 71 and 72 and an output pair of em~tter-coup1ed transistors 73 and 74.
In FIG. 9 there is shown a waveform representing a clock input signal being applied to the clock input terminals 21 of FIGS. 1 and 8.
The output pair of transistors 73 and 74 produce a quantized clock signal current at their collector electrodes. The collector currents of the transistors 73 and 74 are conducted into the inputs of current mirrors 75 and 77, respectively.
Since the currents in the collectors of the output pair of transistors 73 and 74 are complementary, the output currents through the diode and resistor combinations produce complementary output currents through two groups of transistors and output terminals 81, 82 and 83, 84. Each clock output current ICL or ICL from the clock quantizer 70 is produced by a current mirror arrangement that reflects the current from one side of the output pair of emitter coupled transistors 73 and 74.
These clock output currents provide the complementary clock drive currents to the common emitter circuits of the input and output pairs of emitter-coupled transistors in the first and second latch circuits.
These complementary clock drive currents ICL and ICL
~2~L~i7~
are conducted alternately through the common emitter circuits of the input and output pairs of transistors in the lal:ch circuits 41 and 42.
While the input clock signals are functioning correctly, there are two latch circuits 41 and 42 that are sampl~ng and holding the input data that is applied through the terminals 43. Those latch circuits retime and reshape the data into a regenerated output data stream. Both latch circuits repeatedly switch between their latched and unlatched states;however, they are in opposite phase from each other.
In operation each latch circuit retimes and reshapes one half of every data bit. During a first half tlme slot when the first latch circuit 41 is in its unlatched state, an unretimed and unreshaped half of a first data pulse is passed to the second latch circuit 42. At that timé the second latch circu~t 42 ~s in ~ts latch state which retains a prior input data pulse. Dur~ng a second half time slot, the first latch circu~t 41 is in its latching state so ~t ret~mes and reshapes the second half of the first data pulse. Concurrently during the second half time slot, the second latch circuit 42 is in its unlatched state so it passes to the output terminals the retimed and reshaped second half of the first data pulse. During a third half time slot, the first latch circuit 41 is unlatched. It passes one half of a second input data pulse to the second latch circuit 42. At that time, the second latch circuit 42 is in its latched state which retains the output of the first data pulse for another half of a time slot.
Thus the second latch circuit 42 produces ~ully retimed and reshaped output pulses from its output terminals 55. One half of each output pulse is retimed and reshaped in the first latch circuit 41 and is simply passed through the second latch circuit 42. The other half of each output pulse is retimed and reshaped by the second latch circuit 42 thus extending the output pulse width.
Referring now to FIG. 11, there is shown, as a solid line, a representative waveform of the output clock signal ICL. The complementar~ output clock signal ICL is shown dotted also in FIG. 11.
The foregoing description presents the operation of the decision circuit during normal operation while the input clock signal is being applied to the terminals 21 in FIGS. 1 and 8.
In FIG. 1 the multiplier 100, the filter 120 and the comparator 130 are arranged to respond to the quantized clock signal currents produced by the input pair of transistors 71 and 72 of the clock quantizer 70 and applied by the clock quantizer 70 to the multiplier 100, as shown in FIG. 1. These quantized clock currents are mirrored within the clock quantizer to the inputs of the multiplier 100, as shown in FIG. 8.
FIG.10 shows a representative waveform of the quantized clock currents applied to the multiplier 100.
Referring now to FIG. 12, the multiplier 100 is shown as an arrangement for producing an output current IouT which is the product of two ~nput currents Ia and Ib, Substantially all of the current Ia ~s conducted through a pa~r of diodes 102 to a source 103 of negative polarity bias potential. The voltage produced across the diodes 102 is a logarithmic function of the current Ia.Substantially all of the current Ib is conducted through a diode 104 and a transistor 105 to the bias source 103. The voltage produced across the diode 104 and the emitter-base junction of the transistor 105 is a logarithmic functlon of the current Ib.
The two logarithmic function voltages are summed between nodes 106 and 107.
An output c;rcuit arrangement of a pair of transistors 111 and 112 and a pair of diodes 113 produce the output current IouT
which is an antilogarithmic function of the voltage between the nodes . 106 and 107. A resistor 115 is selected so that the current through the diodes 113 allows the diodes to operate in their logarithmic range.
Because of the sum of the logarithmic functions on the input side of the multiplier and the antilogarithmic function on the output side of the circuit, the output current IouT is a function of the product of the input currents Ia and Ib. A more detailed description of the multiplier circuit is presented in U.S. patent ~5~3~
No. 4,~82,977 which issued on November 13, 1984.
! Referrjn~ now to FIG. 13, there is shown a typical output waveform 116 produced by the multiplier 100 of FIG. 1. This waveform is applied to low-pass Filter 120, which produces a mean value signal 117 from the multiplier output waveform 116.
Referring now to FIG. 14, there is shown a schematic of the comparator 130 of FIG. 1 which responds to the amplitude of the mean value signal 117 from the filter 120 comparing the mean value si~nal to a reference voltage VR. During normal operation, the amp7itude of the mean value signal is shown at a steady value below the reference volt3ge VR in FIG. 13. No output current is conducted through output leads 131 and 132 to the first and second latch circuits of FIG. 1. When the input clock signal fails in part or entirely, the filtered multiplier output swings to a failure value shown as a dotted waveform 118 in FIG. 13. Comparator 130 of FIG.14, which supplies no current throu~h output leads 131 and 132 to the first and second latch circuits 41 and ~2 durin~ normal clock op~ration, now st~pplies emi-tter curr~nt to the in~ut, or nonlatchinq, pairs of transistors oF both latch circu~ts 41 and 42.
When the clock signal fails, there is in FIG. 8 a change in a cl ock control current Ic produced by the comparator 130 of FIG. 1 and connected with the common emitter circuits of the output pair of transistors 73 and 74 of the clock quantizer 70. During normal operation, control current Ic is conducted throuqh a lead 135 from the Outpllt of the comparator 130 to the clock quantize~r 70 of FIG. 8.
The control current Ic is conducted when a clock signal of predetermined sufficient amplitude is applied to the cl ock i nput terminals 21. The mean value of the output waveform 117 from the multiplier remains below the reference voltage VR as shown in FIG. 13. When the clock signal applied to the terminals 21 falls below the predetermined level, no clock control current Ic is conducted from the comparator to the clock quantizer. As shown in FIG. l3, the filtered multiplier output crosses above the reference level VR upon failure of the input clock signal.
Ad~antageously when the input clock signal fails, the decision ~5~
g circuit continues to reshape any stream of data pulses applied to the ! data input terminals 22. The clock quantizer no longer supplies emitter current to the input, or latching, pairs of transistors in the latches 41 and 42. By way of the output leads 131 and 132, the comparator 130 supplies emitter current to the input, or nonlatching, pairs of transistors in the latches 41 and 42~ lJnder these circumstances, each latch circuit no longer latches the data but operates some~hat like the quantizer circuit of FIG. 2 with less gain.
The previously mentioned half a time slot delay in the OlltpUt of the delay flip-flop 40 does not occur.
Input data signals are reshaped effectively through a cascade of the ~uantizer circuit 30 and the two latch circuits 41 and 42 operatin~ somewhat like the quantizer circuit. 0utput signals produced on terminals 55 by the latch circuit 42 are buffered through the output huffer circuit fi0 to the data output terminals 29.
FIG. 7 sho~s a representative waveform of regenerated output signals which appear on output terminals 29 of FIG. 1.
FIG. 15 shows a buffer circuit arrangement suitable for use as the output buffer 60 of FIG. 1. The resulting output signals thus are reshaped but not retimed while the clock signal is failed. Although the quality of the data stream is reduced by the lack of retiming, the output data stream can be applied to a transmitter for continuing operation ~f the transmission system in spite of the clock failure.
The transmitted data stream received at the next subsequent regenerator will be both reshaped and retimed therein.
lt is advantageous to fabricate the failsafe decision circuit 20 as an integrated circuit. There are known processes for fabricating the opposite conductivity type transistors as a monolithic intearated circuit capable of operating at frequencies as high as the microwave frequency range.
~; .
R.M. PASKI 2 IMPROVEMENTS IN OR RELATING TO DECISION CIRCUITS
This invention relates to decision circuits.
In the prior art a ~egenerator in a digital transmission system S extracts timing or clock signals from a received data stream. The extracted timing signals are used for controlling the regeneration, that is, the reshaping and retiming of data bits being received. The regenerator makes, for example, a binary decision concerning the amplitude of a received digital signal with respect to a predetermined threshold level at an optimum sampling instant. In response to the received data signal and the extracted timing signal9 a decision circuit in the regenerator reshapes and retimes the received signal into a regenerated, or reshaped and retimed, output signal. This regenerated output signal, with as little distortion as possible, is applied to a modulator for shaping an output signal to be transmitted further a~ong the transmisslon l~ne. If the timing e~traction arrangement fails for any reason, a problem arises ~n that the decision c~rcuit ceases to re~enerate the recelved data b~ts. No output signals are transmitted further along the line.
According to this invention a decision circuit includes means responsive to an input data signal and an input timing signal for reshaping and retiming the input data signals into reshaped and retimed output data signals, the means being responsive to the input data signal in the absence of an input timing signal for reshaping the input data signal into a reshaped but not retimed output data signal.
The invention will now be described by way of example with reference to the accompanying drawings, in which:
FIG. 1 is a block diagram of a decision circuit embodying the i invention;
FIG. 2 is a schematic diagram of a data quantizer used in the circuit of FIG. 1, FIG. 3 is a waveform showing an exemplary input data stream being applied to the quantizer of FIG. 2;
FIG. 4 is a waveform of a quantized version of the exemplary inpuk da~a stream o~ FIG. 3 which is being applied to the ~L~ 73 ~L
quantizer of FIG. 2;
FIG. 5 is a schematic diagram o~ a latch circuit used in the circuit of FIG. 1;
FIG. 6 is a waveform of a delayed, or regenerated, version of the quantized data stream;
FIG. 7 is a waveform of an output data stream produced by the decision circuit of FIG. 1, FIG. 8 is a clock quantizer circuit used in the decision circuit of FIG. 1;
FIG. 9 is a waveform of an input clock signal that is applied to the clock quantizer of FIG. 8;
FIG.10 is the quantized version of the input clock signal of FIG.
9;
FIG. 11 is an output clock signal produced by the clock quantizer of FIG. 8;
FIG. 12 is a schematic diagram of a multiplier circuit used in the circuit of FIG. 1;
FlG. 13 is a waveform of the output of the multlpl~er circuit used in the deciston circuit of FIG. 1;
FIG. 14 is a schematic diagram of a comparator circuit used in the circuit of FIG. 1; and FIG. 15 is a schematic diagram of a buffer circuit used in the circuit of FIG. 1.
Referring now to FIG. 1, a decision circuit 20 is responsive to either single-ended or balanced input signals applied to data input terminals 22, and also to recovered input clock, or timing, signals which are applied to input clock terminals 21. The decision circuit 20 is arranged for reshaping and retiming the Input data signals into regenerated output data signals which are produced on output data terminals 29.
Decision circuit 20 not only regenerates the input data signals during normal operation, but it also continues to produce an output data stream in the event that the recovered input clock signals are not applied to the circuit 20. Thus the decision circuit safely continues to produce a reshaped but not a retimed output 573~.
data stream when the clock, or timing, signals fail to be applied.
This is ver~ advantageous for use in a very long relatively inaccessible cable system requiring regeneration, such as in an undersea optical fiber transmission system.
The decision circuit includes a data quantizer 30, a delay flip-flop 40, and an output buffer 60 for reshaping and retiming the input data signals into the regenerated output data signals produced at output terminals 29. The output data signals are produced so that they are useable as either single-ended or balanced output signals.
The several circuit blocks are shown in greater detail in other figures of the drawing. h1so included in the decision circuit 20 are a clock quantizer 70, a multiplier 100, a low-pass filter l20, and a comparator 130 for retiming the input data signals when the clock pulse is being applied and for ensuring a continued reshaping of the input pulses when no timing pulses are applied.
Referring now to FIG. 2, the input data signals are applied to the data input terminals 22 of data quantizer 30. Quantized signals are produced on output terminals 23 of the data quantizer.
As shown in FIG. 3, a waveform represen-tative of an input data strearn is in a non-return~to-zero format having a Nyquist pulse shape.
Binary digits are presented in FIG. 3 to clearly define the binary data being represented by the waveform during the different time slot intervals.
In operation the data quantizer of FIG. 2 functions as two emitter-coupled pairs of transistors. An input pair of NPN
transistors 24 and 25 is biased to operate for full amplitude input signals in the nonlinear region of its characteristic curves without putting either of those transistors into saturation. The input pair of transistors produces at nodes 32 and 33 complementary signals which are applied to an output pair of PNP transistors 26 and 27.
Transistors 26 and 27 also are biased to operate in a nonlinear region of their characteristic curves without going into saturation.
FIG. 4 shows a waveform which is produced at the outp~t terminals 23 of the data quantizer 30 of FIG. 2 and which represents a quantiæed version of the input data stream. It is noted that some slight delays occur between the waveform of FIG. 3 and the waveform of FIG. 4.
Referring now to FIG. 5, balanced si~nals from the out-put terminals 23 of the data quantizer 30 of FIG. 2 are applied to input terminals 43 of a latch circuit 41 which is suitable for use for both the first latch circuit 41 and the second latch circuit 42 in the delay flip-flop 40 of FIG. 1.
There are three operating sections of the latch circuit 41. An input pair of emitter-coupled NPN transistors 44 and 45 has a nonlatch current I~ as its common emitter current source. Output transimpedance circuits including PNP tran-sistors 47 and 4~, which are opposite conductivity typedevices ~rom the input pair oE transistors, produce complementary ouptut siqnals on a pair Oe output terminals in response to the ~u~n~ize~ ver~ion of the input data stream. A latching pair o emitter-coupled NPN transistors 51 and 52 has a latch current IL as its common emitter current source. The arrangement and operation of the latch circuit 41 are disclosed in greater detail in Canadian Patent Application Serial No. ~53,139 which was filed on April 30, 1984.
Referring once again to FIG. 1, the second latch circuit 42, is similar to the first latch circuit 41 just described.
In the delay flip-flop 40, the signals produced on the output terminals o~ the ~irst latch circuit 41 are applied as bal-anced input signals to the input terminals o~ the second latch circuit 42. Output signals produced by the second latch circuit 42 also are the balanced output of the delay flip-flop 40. Because complementary bipolar transistors are used in the latching circuits, no level shifting circuitry is required.
- 4a _ ~2'`~73~
Referring now to FIG. 6, there is shown a waveform of the output bit stream from the delay flip-flop 40 of FIG. 1 in response to the stream of data bits applied from the out-put of the data quantizer 30 and in response to clock signals from the clock quantizer 70, to be described subsequently herein. It is noted that the quantized output is delayed a half of a bit time slot so that the input data signal, ~'~
~2~57;3~
applied to the delay flip-flop, is not directly available at the output terminals 55 of the delay flip-flop while the clock is running.
The output data stream from the delay fllp-flop 40 represents a reshaped and retimed version of the input data signals applied to the data input terminals 22.
Most of the time during operation of the dec;sion circuit 20~ a clock input signal is extracted from the received stream of data bits.
This clock input signal is applied to the input terminals 21 of the clock quantizer circuit 70 for the purpose of controlling the retiming of the output data signals which are produced by the delay flip-flop 40 of FIG. 1.
Referring now to FIG. 8, there is shown a schematic diagram of a clock quantizer circuit 70 that is suitable for use in the decision circuit 20. This circuit 70 is similar in many respects to the data quantizer of FIG. 2. The clock quantizer c~rcuit 70 of FIG. 8 ~ncludes an ~nput pair of emitter-coupled NPN trans~stors 71 and 72 and an output pair of em~tter-coup1ed transistors 73 and 74.
In FIG. 9 there is shown a waveform representing a clock input signal being applied to the clock input terminals 21 of FIGS. 1 and 8.
The output pair of transistors 73 and 74 produce a quantized clock signal current at their collector electrodes. The collector currents of the transistors 73 and 74 are conducted into the inputs of current mirrors 75 and 77, respectively.
Since the currents in the collectors of the output pair of transistors 73 and 74 are complementary, the output currents through the diode and resistor combinations produce complementary output currents through two groups of transistors and output terminals 81, 82 and 83, 84. Each clock output current ICL or ICL from the clock quantizer 70 is produced by a current mirror arrangement that reflects the current from one side of the output pair of emitter coupled transistors 73 and 74.
These clock output currents provide the complementary clock drive currents to the common emitter circuits of the input and output pairs of emitter-coupled transistors in the first and second latch circuits.
These complementary clock drive currents ICL and ICL
~2~L~i7~
are conducted alternately through the common emitter circuits of the input and output pairs of transistors in the lal:ch circuits 41 and 42.
While the input clock signals are functioning correctly, there are two latch circuits 41 and 42 that are sampl~ng and holding the input data that is applied through the terminals 43. Those latch circuits retime and reshape the data into a regenerated output data stream. Both latch circuits repeatedly switch between their latched and unlatched states;however, they are in opposite phase from each other.
In operation each latch circuit retimes and reshapes one half of every data bit. During a first half tlme slot when the first latch circuit 41 is in its unlatched state, an unretimed and unreshaped half of a first data pulse is passed to the second latch circuit 42. At that timé the second latch circu~t 42 ~s in ~ts latch state which retains a prior input data pulse. Dur~ng a second half time slot, the first latch circu~t 41 is in its latching state so ~t ret~mes and reshapes the second half of the first data pulse. Concurrently during the second half time slot, the second latch circuit 42 is in its unlatched state so it passes to the output terminals the retimed and reshaped second half of the first data pulse. During a third half time slot, the first latch circuit 41 is unlatched. It passes one half of a second input data pulse to the second latch circuit 42. At that time, the second latch circuit 42 is in its latched state which retains the output of the first data pulse for another half of a time slot.
Thus the second latch circuit 42 produces ~ully retimed and reshaped output pulses from its output terminals 55. One half of each output pulse is retimed and reshaped in the first latch circuit 41 and is simply passed through the second latch circuit 42. The other half of each output pulse is retimed and reshaped by the second latch circuit 42 thus extending the output pulse width.
Referring now to FIG. 11, there is shown, as a solid line, a representative waveform of the output clock signal ICL. The complementar~ output clock signal ICL is shown dotted also in FIG. 11.
The foregoing description presents the operation of the decision circuit during normal operation while the input clock signal is being applied to the terminals 21 in FIGS. 1 and 8.
In FIG. 1 the multiplier 100, the filter 120 and the comparator 130 are arranged to respond to the quantized clock signal currents produced by the input pair of transistors 71 and 72 of the clock quantizer 70 and applied by the clock quantizer 70 to the multiplier 100, as shown in FIG. 1. These quantized clock currents are mirrored within the clock quantizer to the inputs of the multiplier 100, as shown in FIG. 8.
FIG.10 shows a representative waveform of the quantized clock currents applied to the multiplier 100.
Referring now to FIG. 12, the multiplier 100 is shown as an arrangement for producing an output current IouT which is the product of two ~nput currents Ia and Ib, Substantially all of the current Ia ~s conducted through a pa~r of diodes 102 to a source 103 of negative polarity bias potential. The voltage produced across the diodes 102 is a logarithmic function of the current Ia.Substantially all of the current Ib is conducted through a diode 104 and a transistor 105 to the bias source 103. The voltage produced across the diode 104 and the emitter-base junction of the transistor 105 is a logarithmic functlon of the current Ib.
The two logarithmic function voltages are summed between nodes 106 and 107.
An output c;rcuit arrangement of a pair of transistors 111 and 112 and a pair of diodes 113 produce the output current IouT
which is an antilogarithmic function of the voltage between the nodes . 106 and 107. A resistor 115 is selected so that the current through the diodes 113 allows the diodes to operate in their logarithmic range.
Because of the sum of the logarithmic functions on the input side of the multiplier and the antilogarithmic function on the output side of the circuit, the output current IouT is a function of the product of the input currents Ia and Ib. A more detailed description of the multiplier circuit is presented in U.S. patent ~5~3~
No. 4,~82,977 which issued on November 13, 1984.
! Referrjn~ now to FIG. 13, there is shown a typical output waveform 116 produced by the multiplier 100 of FIG. 1. This waveform is applied to low-pass Filter 120, which produces a mean value signal 117 from the multiplier output waveform 116.
Referring now to FIG. 14, there is shown a schematic of the comparator 130 of FIG. 1 which responds to the amplitude of the mean value signal 117 from the filter 120 comparing the mean value si~nal to a reference voltage VR. During normal operation, the amp7itude of the mean value signal is shown at a steady value below the reference volt3ge VR in FIG. 13. No output current is conducted through output leads 131 and 132 to the first and second latch circuits of FIG. 1. When the input clock signal fails in part or entirely, the filtered multiplier output swings to a failure value shown as a dotted waveform 118 in FIG. 13. Comparator 130 of FIG.14, which supplies no current throu~h output leads 131 and 132 to the first and second latch circuits 41 and ~2 durin~ normal clock op~ration, now st~pplies emi-tter curr~nt to the in~ut, or nonlatchinq, pairs of transistors oF both latch circu~ts 41 and 42.
When the clock signal fails, there is in FIG. 8 a change in a cl ock control current Ic produced by the comparator 130 of FIG. 1 and connected with the common emitter circuits of the output pair of transistors 73 and 74 of the clock quantizer 70. During normal operation, control current Ic is conducted throuqh a lead 135 from the Outpllt of the comparator 130 to the clock quantize~r 70 of FIG. 8.
The control current Ic is conducted when a clock signal of predetermined sufficient amplitude is applied to the cl ock i nput terminals 21. The mean value of the output waveform 117 from the multiplier remains below the reference voltage VR as shown in FIG. 13. When the clock signal applied to the terminals 21 falls below the predetermined level, no clock control current Ic is conducted from the comparator to the clock quantizer. As shown in FIG. l3, the filtered multiplier output crosses above the reference level VR upon failure of the input clock signal.
Ad~antageously when the input clock signal fails, the decision ~5~
g circuit continues to reshape any stream of data pulses applied to the ! data input terminals 22. The clock quantizer no longer supplies emitter current to the input, or latching, pairs of transistors in the latches 41 and 42. By way of the output leads 131 and 132, the comparator 130 supplies emitter current to the input, or nonlatching, pairs of transistors in the latches 41 and 42~ lJnder these circumstances, each latch circuit no longer latches the data but operates some~hat like the quantizer circuit of FIG. 2 with less gain.
The previously mentioned half a time slot delay in the OlltpUt of the delay flip-flop 40 does not occur.
Input data signals are reshaped effectively through a cascade of the ~uantizer circuit 30 and the two latch circuits 41 and 42 operatin~ somewhat like the quantizer circuit. 0utput signals produced on terminals 55 by the latch circuit 42 are buffered through the output huffer circuit fi0 to the data output terminals 29.
FIG. 7 sho~s a representative waveform of regenerated output signals which appear on output terminals 29 of FIG. 1.
FIG. 15 shows a buffer circuit arrangement suitable for use as the output buffer 60 of FIG. 1. The resulting output signals thus are reshaped but not retimed while the clock signal is failed. Although the quality of the data stream is reduced by the lack of retiming, the output data stream can be applied to a transmitter for continuing operation ~f the transmission system in spite of the clock failure.
The transmitted data stream received at the next subsequent regenerator will be both reshaped and retimed therein.
lt is advantageous to fabricate the failsafe decision circuit 20 as an integrated circuit. There are known processes for fabricating the opposite conductivity type transistors as a monolithic intearated circuit capable of operating at frequencies as high as the microwave frequency range.
~; .
Claims (4)
1. A decision circuit including means responsive to an input data signal and an input timing signal for reshaping and retiming the input data signal into a reshaped and retimed output data signal, the means being responsive to the input data signal in the absence of an input timing signal for reshaping the input data signal into a reshaped but not retimed output data signal.
2. A circuit as claimed in claim 1 wherein the means includes means responsive to the input timing signal for controlling whether or not the reshaped output data signal is retimed.
3. A circuit as claimed in claim 2, wherein the controlling means includes means responsive to the input timing signal for producing a quantized timing signal and its complement, means responsive to the quantized timing signal and its complement for producing a product signal, means responsive to the product signal and a reference potential for determining whether or not the timing signal is a valid timing signal, and means for terminating the retiming of the reshaped output data signal when the timing signal is not valid.
4. A circuit as claimed in claim 1, 2 or 3, fabricated with opposite conductivity type transistors as a monolithic integrated circuit capable of operating at frequencies as high as the microwave frequency range.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US49506783A | 1983-05-13 | 1983-05-13 | |
| US495,067 | 1990-03-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1245731A true CA1245731A (en) | 1988-11-29 |
Family
ID=23967127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000452865A Expired CA1245731A (en) | 1983-05-13 | 1984-04-26 | Failsafe decision circuit |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS59212057A (en) |
| CA (1) | CA1245731A (en) |
| FR (1) | FR2546013B1 (en) |
| GB (1) | GB2139857B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0270296A3 (en) * | 1986-12-01 | 1990-02-07 | Fujitsu Limited | Semiconductor logic circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3440337A (en) * | 1966-12-28 | 1969-04-22 | Bell Telephone Labor Inc | Synchronous data repeater having noncompatible signal bypass |
-
1984
- 1984-04-26 CA CA000452865A patent/CA1245731A/en not_active Expired
- 1984-05-01 GB GB08411124A patent/GB2139857B/en not_active Expired
- 1984-05-09 FR FR8407119A patent/FR2546013B1/en not_active Expired
- 1984-05-12 JP JP9390584A patent/JPS59212057A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| GB2139857B (en) | 1986-06-18 |
| FR2546013B1 (en) | 1987-12-18 |
| FR2546013A1 (en) | 1984-11-16 |
| GB2139857A (en) | 1984-11-14 |
| GB8411124D0 (en) | 1984-06-06 |
| JPS59212057A (en) | 1984-11-30 |
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| MKEX | Expiry |