CA1242528A - Data processing card system and method of forming same - Google Patents
Data processing card system and method of forming sameInfo
- Publication number
- CA1242528A CA1242528A CA000488560A CA488560A CA1242528A CA 1242528 A CA1242528 A CA 1242528A CA 000488560 A CA000488560 A CA 000488560A CA 488560 A CA488560 A CA 488560A CA 1242528 A CA1242528 A CA 1242528A
- Authority
- CA
- Canada
- Prior art keywords
- data processing
- card system
- processing card
- recited
- circuit chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07743—External electrical contacts
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Credit Cards Or The Like (AREA)
Abstract
DATA PROCESSING CARD SYSTEM AND
METHOD OF FORMING SAME
ABSTRACT
A data processing card system (10) which is mounted within the general geometrical contoured dimensions of a card-like housing (46). The data processing card system (10) includes a plurality of circuit chip devices (14) mounted to a flexible film carrier (16). The flexible film carrier member (16) is electrically and mechanically coupled to a substrate carrier member (30). The substrate carrier member (30) includes an electrical pattern (40) at least formed on a first surface (34) thereof for elec-trical coupling to predetermined input leads of the circuit chip devices (14). The combination of the flexible film carrier member (16) and the substrate carrier member (30) are sandwiched between a pair of upper and lower plastic layers (42 and 44) in a substantially hermetic sealing type environment. An edge face (38) of the substrate carrier member (30) provides for a heat dissipation surface area as well as an area wherein electrical connecting pin members (36) are extended to the edge of face (38) for coupling with external devices. The data processing card system (10) is portable and may be carried by the user for insert into external terminal devices for actua-tion of the data processing card system (10).
METHOD OF FORMING SAME
ABSTRACT
A data processing card system (10) which is mounted within the general geometrical contoured dimensions of a card-like housing (46). The data processing card system (10) includes a plurality of circuit chip devices (14) mounted to a flexible film carrier (16). The flexible film carrier member (16) is electrically and mechanically coupled to a substrate carrier member (30). The substrate carrier member (30) includes an electrical pattern (40) at least formed on a first surface (34) thereof for elec-trical coupling to predetermined input leads of the circuit chip devices (14). The combination of the flexible film carrier member (16) and the substrate carrier member (30) are sandwiched between a pair of upper and lower plastic layers (42 and 44) in a substantially hermetic sealing type environment. An edge face (38) of the substrate carrier member (30) provides for a heat dissipation surface area as well as an area wherein electrical connecting pin members (36) are extended to the edge of face (38) for coupling with external devices. The data processing card system (10) is portable and may be carried by the user for insert into external terminal devices for actua-tion of the data processing card system (10).
Description
~L2~
DATA PROCESSING CARD SYSTEM AND
METHOD OF FORMING SAME
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
This invention pertains to data processing systems.
In particular, this invention directs itself to a data processing system packaged within the confines of the geometrical dimensions of a card-like member. More in particular, this invention relates to a data~processing system which includes a plurality of circuit chip devices mounted on at least one flexible carrier member.
. . .
PRIOR ART
In some prior art data processing systems, such as that shown in U.S. Patent #4,295,041, there i9 provided a portable data carrier including a microprocessor. How~
ever, in such prior art systems, there are provided read only memory circuitry and such does not direct itself to electrically alterable program read only memory sys-tems. Additionally, such prior art systems are not able to enclose standard type credit card housing sufficient circuitry to provide for an overall data processing sys-tem, as is provided by the subject invention concept.
In other prior art systems such as that shown in U.S. Patent #4,211,919, there is provided a portable data c~rrier which also includes microprocessing systems. ~ow-ever, in such prior art systems, dense packaging of logic circuitry cannot be accomplished within the card-like housing geometrical constraints. Such prior art systems do not provide for a substrate carrier layer which is integrated into the electrical logic system, as is pro-vided in the subject invention concept.
SUMMARY OF THE Il~VENTION
A data processing card s1ystem which includes a mecha-nism for mounting at least one circuit chip device thereon.
A substrate carrier mechanism is located adjacent the circuit chip device mounting mechanism. The substrate carrier mechanism has at least a first predetermined elec-trical lead pattern formed thereon and the electrical pattern is electrically coupled to predetermined contact areas of the circuit chip device. There is also provided a mechanism for substantially isolating the combined sub-strate carrier mechanism and the circuit chip device mounting mechanism from an external environment.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a perspective view of the data process-ing card system;
FIG. 2 is a perspective, exploded and partially cut-away view of the data processing card system showing the substrate carrier member and the flexible carrier member sandwiched between opposing isolating plastic layer members;
FIG. 3 is a sectional view of the data processing card system taken alon~ the section line 3-3 of FIG. 1;
FIG. 4 is a perspective, and exploded view of an embodiment of the data processing card system showing a substrate carrier member sandwiched between first and second flexible carrier members each having a plurality of circuit chip devices mounted thereon for electrical interaction with lead patterns formed on opposing surfaces of the substrate carrier member;
FIG. 5 is a perspective view of the second flexible carrier member showing the surface having circuit chip devices mounted thereon;
FIG. 6 is a perspective and exploded view of a por-tion of the first or second carrier members and the posi-tional alignment of the circuit chip thereon;
FIG. 7 is a sectional view of the first or second flexible film carrier members taken along the section lines 7-7 of FIG. 6;
FIG. 8 is a perspective view of a chip coupling flexible carrier member; and, FIG. 9 is a sectional view of an embodiment of the data processing card system showing an extended substrate carrier member.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to FIGS. 1-3, there is shown data processing card system 10 which provides for an electronic logic circuit packaging technique to produce.overall data processina card system 10 in an encapsulated manner within a substantially hermetically sealed housing 46 which takes on the overall geometrical contour of card member 12.
As seen in FIG. 1, data processing card system 10 is encapsulated and packaged into thin housing 46 in the form of card member 12 or another type planar member.
As will be seen in following paragraphs, data processing card system 10 as provided in the overall packaging tech-nique and structure as herein described, is substantially hermetically sealed with respect to the external environ-ment in order that data processing system 10 may be used in a wide variety of external environments, some of which may be deleterious to the logic circuitry contained therein.
In ovexall concept, data processing system 10 provides for a plurality of logic chip circuits in a thin, minia-turized packaging scheme which provides for substantially hermetic sealing of the chip electronic circuitry in a dense packaging concept. Integrated circuit chips 14, shown in FIG. 2, are well kno~wn in the art and may be logic circuit chips, chip memory devices, and/or combinations thereof. Circuit chip devices 14 may be of the electri-cally erasable programmable read-only memory type such as that commercially produced by INTEL~Corp. having a de-signation number 2816. This type of chip memory device 14 is operable from a 5.0 volt power supply in the read mode and the write/erase modes are accomplished by pro-viding a voltage pulse approximating 21.0 volts. The elec-trical erase/write capability of the INTEL model number 2816 memory chip device 14 allows for a variety of appli-cations requiring non-volatile erase and write modes.
In the embodiments shown in FIGS. 1-3, data process-ing system 10 includes a plurality of circuit chip devices 14 coupled to a mechanism for mounting chip devices 14 within data processing system 10. Circuit chip devices 14 are mounted onto first flexible film carrier 16 through use of one of a number of well known techniques. One tech-nique of mounting chips 14 to first flexible film carrier ` ! `
- ~ -16 is clearly shown and descri.bed in U.S. Patent #3,689,991 with an apparent improvement shown and described in U.S
Patent #4,380,042. Chip devices 14 are lead bonded to first flexible fiim carrier 16 which includes a unique circuit design to allow circuit chips 14 to be inter-connected into an overall data processing system 10.
Referring now to FIGS. 6 and 7, there is shown the mounting mechanism and structure for circuit chips 14.
As can be seen in FIG. 6, in partial cut-away and perspec-tive view, first flexible film carrier 16 is shown with one chip device 14 removed therefrom for clarity purposes.
As shown in FIG. 6, chip device 14 is alignable with a lower portion of first flexible film carrier 16, however, chip device 14 may be mounted on a top surface as is well known in the art.
Flexible film carrier 16 includes electrically in-sulating tape 18 which is electrically insulated and a thin foil strip or Iayer member ~0 which is electrically conducting and secured to insulating layer 18 by adhesive lamination or some like technique, not important to the overall concept.
FIGS. 6 and 7 are exaggered in thickness for clarity of ~isual observation, however, the overall thick-ness of insulating and conductive layers 18 and 20 in combination may be within the approximating dimensional thickness range of 0.005 to 0.01 inches with an overall preferred dimensional thickness of first flexible film carrier member 16 approximating 0.0075 inches. Electrically conducting layer 20 may be a thickness in the approximating range of 0.0001 to 0.0005 inches. Additionally, in order to provide a quantitative dimension to overall first flexible film carrier 16, chip circuit devices 14 of the type herein described may include a dimensional thickness within the approximating range of 0.01 to 0.04 inches with a preferred dimensional thickness approximating 0.02 inches. First flexible film carrier member 16 is of the type shown and described in U.S. Patent #3,689,991 and #4,380,042.
Apertures 22 extend through first flexible film carrier 16 and are aligned with logic chip devic~ 14 for -insert therein. As shown in FIG. 6, portions of electri-cally conducting layer 20 may be removed from overall flexible film carrier 16 to form a plurality of metallic or conducting leads 24 for contacting predetermined active regions 26 of circuit chip device 14. Removal of elec~
trically conducting layer member 20 in a predetermined pattern may be accomplished by photolithographic masking and etching, or other well known techniques in the art.
Subsequent to removal of predetermined portions of elec-trically conductive foil layer 20, lead members 24 are formed and extend internal to aperture 22 to provide for contact bonding of chip devices 14 to electrical lead members 24.
In the manufacturing process for first flexible film carrier member 16 having a plurality of chip devices 14 adhered thereto, a strip of insulating tape layer 18 in --ll--combination with electrically conducting layer 20 is ini-tially provided. ~entral aperture 22 passing through layers 18 and 20 locate the inner portion of metallic lead mem-bers 24 which are formed by etching away predetermined portions of electrically conductive layer 20 external to the predetermined geometrical configuration of leads 24.
The inner end portions of metallic leads 24 extend in a generally radial outward direction from the central portion of aperture 22 as shown in FIG. 6. The inner end portions of leads 24 terminate internal to aperture 22 and terminate in registry or alignment with contact regions 26 of chip devices 14. Logic chip devices 14 may then be placed in alignment with aperture 22 and the inner ends of leads 24 are secured to chip devices 14 at contact re-gions 26.
Prior to logic or memory chip devices 14 being coupled to leads 22, first fle~ible film carrier member 16 may be unwound from a reel, as is known in the art, and leads 24 formed thereon through appropriate pattern etching tech-niques. First flexible film carrier 16 may then be immersed in a tin plating solution to plate the exposed portions of lead 24 with a solderable ~etal. Thus, both sides of the exposed portions of leads 24 within aperture 22 are tin coated.
Semi-conductor devices 14 may then be bonded to leads 24 by application of an electrical conductor wherein logic and/or memory devices 14 may include metallic contacts attached to electrically active regions 26. To effect the bonding of the contacts to the leads 24, the tin plated leads 24 are pressed against the contacts by a displace-ment of a he2table bonding tip system which is well known in the art. Bonding may then be achieved by applying elec-trical resistance heating current to the tip and such is raised to a sufficiently high temperature to cause the tin plated leads 24 to be bonded to the gold contacts of the contact regions 26.
Additionally, in order to couple a plurality of chip devices 14 in consesutive manner on ~irst flexible film carrier 16, there is provided metallic buss bar foil member 28, as is shown in FIGS. 1 and 6, to which chip devices 14 are electrically coupled. In this manner, a plurality of chip devices 14 may be coup:Led each to the other, depen-dent upon a particular circuit design requirement, not part of the subject invention concept.
Data processing card system 10 as herein described replaces a standard printed circuitboard using generally photo-etched copper circuit patterns with flexible film carriers which interconnect logic andfor memory chips 14 into a singular operating data processing card system 10. A plurality of chip devices 14 mounted on consecutive frames of first film carrier 16 provide for a total system pattern which is repeated on first film carrier member 16 in a manner such that overall data processing system 10 may be easily bonded as well as tested.
Substrate carrier member 30 of data processing system 10 is formed as part of the overall logic circuitry to carry parallel bussing for each chip device 14. Addi-tionally, substrate carrier member 30 may be used to inter-connect chip circuits dependent upon the particular logic involved. Further, substrate carrier member 30 is generally formed of a substantially rigid type composition to provide a mechanical support for first flexible film carrier 16 and associated circuit chips 14 and finally is used as a heat dissipation device for data processing system 10 during the operational mode. Thus, substrate carrier member 30 in addition to heat dissipation uses, provides for an electrical interconnection system to couple circuit chip 14 into an overall operating data processing system 10 and is interrelated and a part of the electrical design concept.
In order to provide for an electrically insulative material composition in combination with a thermally con~
ductive composition, substrate carrier member 30 may be formed of ceramic, Kovar~ or some like material which will aid in the heat dissipation of system 10 during opera-tion while simultaneously maintaining a substantially electrically insulative barrier. Additionally~ such ma-terials also give some rigidity to system 10 which is important since it is understood that film carrier 16 is extremely flexible in structural rigidity and overall card system 10 must be of sufficient rigidity to allow operational use in a number of user environments~
As can be clearly seen in FIG. 2, substrate carrier leads 32 are formed into an overall first predetermined electrical lead pattern 40 formed on upper or top surface 34 of substrate carrier member 30. First substrate elec-trical pattern 40 may be formed through photo-resist etching or some like technique not important to theinventive con-cept as herein described. The overall pattern of elec-trical substrate carrier leads 32 match the circuit pattern required to interconnect the address data busses of cir-cuit chip devices 14 into an overall operating system.
As can be seen in FIGS. 2 and 3, a plurality of sub-strate carrier leads 32 of first substrate electrical pattern 40 may expand to substrate carrier edge face 38 where such terminate in electrically connective pin members 36. Electrically connective pin members 36 mounted on edge face 38 provide for the electrical coupling of data processing system 10 to an external terminal device not part of the subject invention concept.
As seen in FIG. 3, chip pin members 48 are used to couple predetermined substrate carrier leads 32 within the overall Eirst predetermined electrical lead pattern 40 as well as to individual circuit chips 14. Chip pin member 48 may be electrically coupled to predetermined electrical lead members 24 on one end thereof and extend into electrical contact with predetermined substrate carrier leads 32 as is necessitated by the particular design logic.
It is to be understood that chip pin members 48 may be discrete chip pin members or may simply be extensions of foil electrical lead members 24 which are directed in a downward manner through first flexible film carrier 16 into contact with predetermined substrate carriPr leads 32. ~he manner and mode of particularly couplirg circuit chips 14 to first predetermined electrical lead pattern 40 may be through a number of techniques with the use of chip pin members 48 being shown and described for illus-trative purposes.
Still referring to the embodiment of data processing card system 10 as shown in FIGS. 1-3, there is further provided a mechanism for substantially isolating substrate carrier member 30 and first flexible film carrier 16 from an external environment. Referring to FIGS. 2 and 3, the isolating mechanism includes a pair of substantially planar layer members 42 and 44 which are coupled to combined ~ ~3~ ~3 substrate c~rrier member 30 and first flexible film carrier 16 on opposing sides thereof. Planar layer members 42 and 44 are generally formed of a plastic composition ma-terial. Plastic layer members 42 and 44 are applied above and beneath the combination of flexible film carrier 16 and substrate carrier 30 and are generally bonded thereto by appropriate heat and pressure techniques well ~nown in the art.
As has been stated, substrate carrier member 30 may be formed of a ceramic~ glass, silicon oxide composition, or Kovar, which is generally a steel carrier having a porcelain coating. Dependent upon the other material composition of card system 10, substrate carrier member 30 is generally designed to be formed of a material which is substantially matched to the temperature coefficient of expansion/contraction of chip devices 14 which may be generally silicon based.
First substrate electrical pattern 40 formed by elec-trically connecting or lead members 32 interconnect the plurality of attached flexible film carrier member systems in order that a plurality of circuit chip devices 14 may be system integrated. Each of the carriers may then be interconnected together in a unique format dependent upon the logic systems involved to provide an overall elec-tronic system. Thus, as has been stated, an important purpose and objective of substrate carrier member 30 is to provide a basis for interconnecting the plurality of system level carriers and circuits into an overall operat-ing circuit. Additionally, substrate carrler member 30 mechanically supports the circuits and further dissipates the heat generated by each of chip devices 14 when in an operational mode.
In overall operation in manufacturing data processing card system 10, a plurality of chip circuit devices 14 may be mounted to first flexible film carrier 16 in a manner cleaxly shown and described in U.S. Patents #3,689,991 and/or ~4,380,042. Electrical pattern 40 may be formed through photo-resistive etching on substrate carrier member 30 in a manner well known in the art. First flexible film carrier 16 may then be bonded to substrata carrier me~ber 30 in a registered manner by adhesive bonding.
It is to be understood that the adhesive used in such a bonding process has a temperature coefficient of expan sion/contraction which substantially matches the composition material of circuit chip devices 14 as well as the parti-cular material composition of substrate carrier member 30. In this manner, first flexible film carrier 16 is adhesively mounted in secured manner to substrate carrier member 30 which in itself is generally and substantially non-electrically conductive, however, is substantially thermally conductive for the dissipation of heat generated by circuit chips 14 during their operational mode. Heat and pressure are applied to weld the appropriate patterns carried on flexible film carrier 16 to attachment points on the matrix or first substrate electrical pattern 40 formed on substrate member 30. Finally, plastic layers 42 and 44 are applied above and beneath the combination o first flexible film carrier 16 and substrate carrier member 30 and such layers 42 and 44 are bonded thereto by appropriate heat and pressure techniques well known in khe art.
Referring now to FIGS. 4 and 5, there is shown data processing card system 10' which is an embodiment of data processing card system 10 previously described in FIGS.
1-3. For clarity, elements of card system 10' which are substantially the same as elements provided for card sys-tem 10, are given like numbers. The concept of data pro-cessing card system 10' is to provide a layered system which is utilized for providing additional circuit chip devices 14 with increased logic circuitry while simul-taneously maintaining a relatively thin overall housing structure.
As was the case in data processing card system 10, embodiment data processing card system 10' includes first flexible film carrier member 16 which interfaces and is contiguously located with respect to substrate carrier top surface 34. As seen in FIG. 4, first flexible film carrier 16 includes first flexible film carrier lower surface 50 through which there is shown connective open-ings 52 for coupling of circuit chip devices 14 to first substrate electrical pattPrn 40 (shown in FIG. 2). It is to be understood that substrate carrier top surface 34 shown in FIG. 4 contains first substrate electrical pattern 40 which has been described in connection with data processing card system 10 as shown in FIGS. 1-3.
As shown in FIG. 4, substr.ate carrier member 30 includes substrate carrier member lower surface 54 which has formed thereon lower surface electrical leads 56 formed into second substrate electrical pattern 58 in a manner similar to that provided for data processing card system 10 as previously described. Lower surface leads 56 of second substrate electrical pattern 58 extend to substrate carrier edge face 38 and terminate in electrically connective pin member 36 for electrical coupling to external devices.
Second flexible film carrier 60 carrying and having mounted thereon a plurality of circuit chip devices 14 as shown in FIG. 5 is mated to substrate carrier lower surface 54. Second flexible film carrier 60 includes connective openings 62 for interfacing and connecting circuit chips 14 to second substrate electrical pattern 58. Upper surface 64 of second flexible film carrier member 60 is matingly engaged with substrate carrier lower surface 54 in the substantially identical manner that first flexible film carrier lower surface 50 is matingly engaged with substrate carrier top surface 34. It is to be understood that electrical coupling of circuit devices 14 on first film carrier member 16 may be electrically coupled to circuit devices 14 on second flexible film carrier 60 through interconnection openings or other conn-ectable means passing through substrate carrier member 30.
Thus, first and second electrical patterns 40 and 58 may be formed on opposing surfaces 34 and 54 of substrate carrier member 30 to provide a dual sided interconnect system. In this manner, a plurality of flexible film carrier members such as 16 and 60 may be seen to be mounted on opposing surfaces of substrate carrier member 30 to provide increased design logic considerations for data processing card system 10'.
Referxing now to FIG. 8, there is shown a mechanism for electrically coupling at least a pair of circuit chip devices 14 each to the other between a predetermined contact area 26. As will be seen in following paragraphs, the chip electrical coupling mechanism is sandwiched between substrate carrier member 30 and first and second flexible carrier members 16 and 60. The electrical coupling mecha-nism shown in FIG. 8 may be utilized where the diminished area and distances of between circuit chips 14 do not permit all of the necessary electrical contacts being completed.
Referring now to FIG. 8, there is shown a mechanism for electrically coupling at least a pair of circuit chip devices 14 each to the other between a predetermined con-tact area 26. As will be seen in following paragraphs, the chip electrical coupling mechanism is sandwiched between substrate carrier member 3G and first and second flexible carrier members 16 and 60. The electrical coupling mecha-nism shown in FIG. 8 may be utilized where the diminished area and distances between circuit chips 14 do not permit all of the necessary electrical contacts being completed.
In the case where additional contact and electrical leads are necessitated, there is provided chip coupling flexible carrier member 66 for electrically coupling prede-termined contact regions 26 of separate circuit chips 14 each to the other. As was the case with first and second flexible carrier members 16 and 60, chip coupling flexible carrier member 66 incluaesan electrically insulat-ing tape member having opposed first and second surfaces 68 and 70. Chip coupling carrier member 66 further includes a plurality of electrically conductive chip coupling lead members 72 which are secured to first surface 68 of the electrically insulating tape member. Chip coupling lead members 72 may be generally of the same foil layer construc-tion as that provided and described for electrically conductive foil layer 20 and leads 24 of first carrier member 16.
First surface 68 of chip coupling flexible carrier member 66 is mounted adjacent to surface 50 of first flexible carrier member 16 and/or adjacent surface 64 of second carrier member 60. Pin members passing through opening 62 and/or 52 of associated carriers 60 and 16 contact chip coupling lead members 72 and such pin members may be connected to a predetermined electrical lead 24 to provide electrical coupling between individual circuit chips 14. Thus, in the ~mbodiment shown in FIGS~ 1-3, chip coupling flexible carrier member 66 would be sandwiched between first flexible film carrier member 16 and substrate carrier member 30. In the embodiments shown in FIGS.
4 and 5, data processing card system 10' would include a pair of chip coupling flexible carrier members 66 sand-wiched between first flexible carrier member 16 and sub-strate planar member 30 as well as second flexible carrier member 60 and substrate planar member 30 respectively.
In order to provide coupling between chip devices 14 on carrier members 16 and 60 and associated portions of first and second substrate electrical patterns 40 and 58, chip coupling openings 74 may be provided to allow other lead pin members to extend therethrough.
Referring now to FIG. 9~ there is shown an embodiment of data processing card system 10 as provided in FIGS.
1-3. It is to be understood that the embodiment shown in FIG. 9 is equally applicable to data processing card system 10' as it is to card system 10. In the cross-section shown in FIG. 9, substrate carrier member 30 is seen to be extended beyond the peripheral boundaries of upper and lower plastic layers of 42 and 44 as well as beyond first $1exible film carrier member 16. As can be understood, substrate carrier member 30 provides for additional surface area 76 to aid in any additional heat dissipation which may be necessitated. As was the calcu-lation of substrate carrier surface edge thickness 38, additional surface areas 76 may be calculated based upon the heat dissipation requirements necessitated by the particular heat generating logic circuitry contained within card system 10 or card system 10'.
DATA PROCESSING CARD SYSTEM AND
METHOD OF FORMING SAME
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
This invention pertains to data processing systems.
In particular, this invention directs itself to a data processing system packaged within the confines of the geometrical dimensions of a card-like member. More in particular, this invention relates to a data~processing system which includes a plurality of circuit chip devices mounted on at least one flexible carrier member.
. . .
PRIOR ART
In some prior art data processing systems, such as that shown in U.S. Patent #4,295,041, there i9 provided a portable data carrier including a microprocessor. How~
ever, in such prior art systems, there are provided read only memory circuitry and such does not direct itself to electrically alterable program read only memory sys-tems. Additionally, such prior art systems are not able to enclose standard type credit card housing sufficient circuitry to provide for an overall data processing sys-tem, as is provided by the subject invention concept.
In other prior art systems such as that shown in U.S. Patent #4,211,919, there is provided a portable data c~rrier which also includes microprocessing systems. ~ow-ever, in such prior art systems, dense packaging of logic circuitry cannot be accomplished within the card-like housing geometrical constraints. Such prior art systems do not provide for a substrate carrier layer which is integrated into the electrical logic system, as is pro-vided in the subject invention concept.
SUMMARY OF THE Il~VENTION
A data processing card s1ystem which includes a mecha-nism for mounting at least one circuit chip device thereon.
A substrate carrier mechanism is located adjacent the circuit chip device mounting mechanism. The substrate carrier mechanism has at least a first predetermined elec-trical lead pattern formed thereon and the electrical pattern is electrically coupled to predetermined contact areas of the circuit chip device. There is also provided a mechanism for substantially isolating the combined sub-strate carrier mechanism and the circuit chip device mounting mechanism from an external environment.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a perspective view of the data process-ing card system;
FIG. 2 is a perspective, exploded and partially cut-away view of the data processing card system showing the substrate carrier member and the flexible carrier member sandwiched between opposing isolating plastic layer members;
FIG. 3 is a sectional view of the data processing card system taken alon~ the section line 3-3 of FIG. 1;
FIG. 4 is a perspective, and exploded view of an embodiment of the data processing card system showing a substrate carrier member sandwiched between first and second flexible carrier members each having a plurality of circuit chip devices mounted thereon for electrical interaction with lead patterns formed on opposing surfaces of the substrate carrier member;
FIG. 5 is a perspective view of the second flexible carrier member showing the surface having circuit chip devices mounted thereon;
FIG. 6 is a perspective and exploded view of a por-tion of the first or second carrier members and the posi-tional alignment of the circuit chip thereon;
FIG. 7 is a sectional view of the first or second flexible film carrier members taken along the section lines 7-7 of FIG. 6;
FIG. 8 is a perspective view of a chip coupling flexible carrier member; and, FIG. 9 is a sectional view of an embodiment of the data processing card system showing an extended substrate carrier member.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to FIGS. 1-3, there is shown data processing card system 10 which provides for an electronic logic circuit packaging technique to produce.overall data processina card system 10 in an encapsulated manner within a substantially hermetically sealed housing 46 which takes on the overall geometrical contour of card member 12.
As seen in FIG. 1, data processing card system 10 is encapsulated and packaged into thin housing 46 in the form of card member 12 or another type planar member.
As will be seen in following paragraphs, data processing card system 10 as provided in the overall packaging tech-nique and structure as herein described, is substantially hermetically sealed with respect to the external environ-ment in order that data processing system 10 may be used in a wide variety of external environments, some of which may be deleterious to the logic circuitry contained therein.
In ovexall concept, data processing system 10 provides for a plurality of logic chip circuits in a thin, minia-turized packaging scheme which provides for substantially hermetic sealing of the chip electronic circuitry in a dense packaging concept. Integrated circuit chips 14, shown in FIG. 2, are well kno~wn in the art and may be logic circuit chips, chip memory devices, and/or combinations thereof. Circuit chip devices 14 may be of the electri-cally erasable programmable read-only memory type such as that commercially produced by INTEL~Corp. having a de-signation number 2816. This type of chip memory device 14 is operable from a 5.0 volt power supply in the read mode and the write/erase modes are accomplished by pro-viding a voltage pulse approximating 21.0 volts. The elec-trical erase/write capability of the INTEL model number 2816 memory chip device 14 allows for a variety of appli-cations requiring non-volatile erase and write modes.
In the embodiments shown in FIGS. 1-3, data process-ing system 10 includes a plurality of circuit chip devices 14 coupled to a mechanism for mounting chip devices 14 within data processing system 10. Circuit chip devices 14 are mounted onto first flexible film carrier 16 through use of one of a number of well known techniques. One tech-nique of mounting chips 14 to first flexible film carrier ` ! `
- ~ -16 is clearly shown and descri.bed in U.S. Patent #3,689,991 with an apparent improvement shown and described in U.S
Patent #4,380,042. Chip devices 14 are lead bonded to first flexible fiim carrier 16 which includes a unique circuit design to allow circuit chips 14 to be inter-connected into an overall data processing system 10.
Referring now to FIGS. 6 and 7, there is shown the mounting mechanism and structure for circuit chips 14.
As can be seen in FIG. 6, in partial cut-away and perspec-tive view, first flexible film carrier 16 is shown with one chip device 14 removed therefrom for clarity purposes.
As shown in FIG. 6, chip device 14 is alignable with a lower portion of first flexible film carrier 16, however, chip device 14 may be mounted on a top surface as is well known in the art.
Flexible film carrier 16 includes electrically in-sulating tape 18 which is electrically insulated and a thin foil strip or Iayer member ~0 which is electrically conducting and secured to insulating layer 18 by adhesive lamination or some like technique, not important to the overall concept.
FIGS. 6 and 7 are exaggered in thickness for clarity of ~isual observation, however, the overall thick-ness of insulating and conductive layers 18 and 20 in combination may be within the approximating dimensional thickness range of 0.005 to 0.01 inches with an overall preferred dimensional thickness of first flexible film carrier member 16 approximating 0.0075 inches. Electrically conducting layer 20 may be a thickness in the approximating range of 0.0001 to 0.0005 inches. Additionally, in order to provide a quantitative dimension to overall first flexible film carrier 16, chip circuit devices 14 of the type herein described may include a dimensional thickness within the approximating range of 0.01 to 0.04 inches with a preferred dimensional thickness approximating 0.02 inches. First flexible film carrier member 16 is of the type shown and described in U.S. Patent #3,689,991 and #4,380,042.
Apertures 22 extend through first flexible film carrier 16 and are aligned with logic chip devic~ 14 for -insert therein. As shown in FIG. 6, portions of electri-cally conducting layer 20 may be removed from overall flexible film carrier 16 to form a plurality of metallic or conducting leads 24 for contacting predetermined active regions 26 of circuit chip device 14. Removal of elec~
trically conducting layer member 20 in a predetermined pattern may be accomplished by photolithographic masking and etching, or other well known techniques in the art.
Subsequent to removal of predetermined portions of elec-trically conductive foil layer 20, lead members 24 are formed and extend internal to aperture 22 to provide for contact bonding of chip devices 14 to electrical lead members 24.
In the manufacturing process for first flexible film carrier member 16 having a plurality of chip devices 14 adhered thereto, a strip of insulating tape layer 18 in --ll--combination with electrically conducting layer 20 is ini-tially provided. ~entral aperture 22 passing through layers 18 and 20 locate the inner portion of metallic lead mem-bers 24 which are formed by etching away predetermined portions of electrically conductive layer 20 external to the predetermined geometrical configuration of leads 24.
The inner end portions of metallic leads 24 extend in a generally radial outward direction from the central portion of aperture 22 as shown in FIG. 6. The inner end portions of leads 24 terminate internal to aperture 22 and terminate in registry or alignment with contact regions 26 of chip devices 14. Logic chip devices 14 may then be placed in alignment with aperture 22 and the inner ends of leads 24 are secured to chip devices 14 at contact re-gions 26.
Prior to logic or memory chip devices 14 being coupled to leads 22, first fle~ible film carrier member 16 may be unwound from a reel, as is known in the art, and leads 24 formed thereon through appropriate pattern etching tech-niques. First flexible film carrier 16 may then be immersed in a tin plating solution to plate the exposed portions of lead 24 with a solderable ~etal. Thus, both sides of the exposed portions of leads 24 within aperture 22 are tin coated.
Semi-conductor devices 14 may then be bonded to leads 24 by application of an electrical conductor wherein logic and/or memory devices 14 may include metallic contacts attached to electrically active regions 26. To effect the bonding of the contacts to the leads 24, the tin plated leads 24 are pressed against the contacts by a displace-ment of a he2table bonding tip system which is well known in the art. Bonding may then be achieved by applying elec-trical resistance heating current to the tip and such is raised to a sufficiently high temperature to cause the tin plated leads 24 to be bonded to the gold contacts of the contact regions 26.
Additionally, in order to couple a plurality of chip devices 14 in consesutive manner on ~irst flexible film carrier 16, there is provided metallic buss bar foil member 28, as is shown in FIGS. 1 and 6, to which chip devices 14 are electrically coupled. In this manner, a plurality of chip devices 14 may be coup:Led each to the other, depen-dent upon a particular circuit design requirement, not part of the subject invention concept.
Data processing card system 10 as herein described replaces a standard printed circuitboard using generally photo-etched copper circuit patterns with flexible film carriers which interconnect logic andfor memory chips 14 into a singular operating data processing card system 10. A plurality of chip devices 14 mounted on consecutive frames of first film carrier 16 provide for a total system pattern which is repeated on first film carrier member 16 in a manner such that overall data processing system 10 may be easily bonded as well as tested.
Substrate carrier member 30 of data processing system 10 is formed as part of the overall logic circuitry to carry parallel bussing for each chip device 14. Addi-tionally, substrate carrier member 30 may be used to inter-connect chip circuits dependent upon the particular logic involved. Further, substrate carrier member 30 is generally formed of a substantially rigid type composition to provide a mechanical support for first flexible film carrier 16 and associated circuit chips 14 and finally is used as a heat dissipation device for data processing system 10 during the operational mode. Thus, substrate carrier member 30 in addition to heat dissipation uses, provides for an electrical interconnection system to couple circuit chip 14 into an overall operating data processing system 10 and is interrelated and a part of the electrical design concept.
In order to provide for an electrically insulative material composition in combination with a thermally con~
ductive composition, substrate carrier member 30 may be formed of ceramic, Kovar~ or some like material which will aid in the heat dissipation of system 10 during opera-tion while simultaneously maintaining a substantially electrically insulative barrier. Additionally~ such ma-terials also give some rigidity to system 10 which is important since it is understood that film carrier 16 is extremely flexible in structural rigidity and overall card system 10 must be of sufficient rigidity to allow operational use in a number of user environments~
As can be clearly seen in FIG. 2, substrate carrier leads 32 are formed into an overall first predetermined electrical lead pattern 40 formed on upper or top surface 34 of substrate carrier member 30. First substrate elec-trical pattern 40 may be formed through photo-resist etching or some like technique not important to theinventive con-cept as herein described. The overall pattern of elec-trical substrate carrier leads 32 match the circuit pattern required to interconnect the address data busses of cir-cuit chip devices 14 into an overall operating system.
As can be seen in FIGS. 2 and 3, a plurality of sub-strate carrier leads 32 of first substrate electrical pattern 40 may expand to substrate carrier edge face 38 where such terminate in electrically connective pin members 36. Electrically connective pin members 36 mounted on edge face 38 provide for the electrical coupling of data processing system 10 to an external terminal device not part of the subject invention concept.
As seen in FIG. 3, chip pin members 48 are used to couple predetermined substrate carrier leads 32 within the overall Eirst predetermined electrical lead pattern 40 as well as to individual circuit chips 14. Chip pin member 48 may be electrically coupled to predetermined electrical lead members 24 on one end thereof and extend into electrical contact with predetermined substrate carrier leads 32 as is necessitated by the particular design logic.
It is to be understood that chip pin members 48 may be discrete chip pin members or may simply be extensions of foil electrical lead members 24 which are directed in a downward manner through first flexible film carrier 16 into contact with predetermined substrate carriPr leads 32. ~he manner and mode of particularly couplirg circuit chips 14 to first predetermined electrical lead pattern 40 may be through a number of techniques with the use of chip pin members 48 being shown and described for illus-trative purposes.
Still referring to the embodiment of data processing card system 10 as shown in FIGS. 1-3, there is further provided a mechanism for substantially isolating substrate carrier member 30 and first flexible film carrier 16 from an external environment. Referring to FIGS. 2 and 3, the isolating mechanism includes a pair of substantially planar layer members 42 and 44 which are coupled to combined ~ ~3~ ~3 substrate c~rrier member 30 and first flexible film carrier 16 on opposing sides thereof. Planar layer members 42 and 44 are generally formed of a plastic composition ma-terial. Plastic layer members 42 and 44 are applied above and beneath the combination of flexible film carrier 16 and substrate carrier 30 and are generally bonded thereto by appropriate heat and pressure techniques well ~nown in the art.
As has been stated, substrate carrier member 30 may be formed of a ceramic~ glass, silicon oxide composition, or Kovar, which is generally a steel carrier having a porcelain coating. Dependent upon the other material composition of card system 10, substrate carrier member 30 is generally designed to be formed of a material which is substantially matched to the temperature coefficient of expansion/contraction of chip devices 14 which may be generally silicon based.
First substrate electrical pattern 40 formed by elec-trically connecting or lead members 32 interconnect the plurality of attached flexible film carrier member systems in order that a plurality of circuit chip devices 14 may be system integrated. Each of the carriers may then be interconnected together in a unique format dependent upon the logic systems involved to provide an overall elec-tronic system. Thus, as has been stated, an important purpose and objective of substrate carrier member 30 is to provide a basis for interconnecting the plurality of system level carriers and circuits into an overall operat-ing circuit. Additionally, substrate carrler member 30 mechanically supports the circuits and further dissipates the heat generated by each of chip devices 14 when in an operational mode.
In overall operation in manufacturing data processing card system 10, a plurality of chip circuit devices 14 may be mounted to first flexible film carrier 16 in a manner cleaxly shown and described in U.S. Patents #3,689,991 and/or ~4,380,042. Electrical pattern 40 may be formed through photo-resistive etching on substrate carrier member 30 in a manner well known in the art. First flexible film carrier 16 may then be bonded to substrata carrier me~ber 30 in a registered manner by adhesive bonding.
It is to be understood that the adhesive used in such a bonding process has a temperature coefficient of expan sion/contraction which substantially matches the composition material of circuit chip devices 14 as well as the parti-cular material composition of substrate carrier member 30. In this manner, first flexible film carrier 16 is adhesively mounted in secured manner to substrate carrier member 30 which in itself is generally and substantially non-electrically conductive, however, is substantially thermally conductive for the dissipation of heat generated by circuit chips 14 during their operational mode. Heat and pressure are applied to weld the appropriate patterns carried on flexible film carrier 16 to attachment points on the matrix or first substrate electrical pattern 40 formed on substrate member 30. Finally, plastic layers 42 and 44 are applied above and beneath the combination o first flexible film carrier 16 and substrate carrier member 30 and such layers 42 and 44 are bonded thereto by appropriate heat and pressure techniques well known in khe art.
Referring now to FIGS. 4 and 5, there is shown data processing card system 10' which is an embodiment of data processing card system 10 previously described in FIGS.
1-3. For clarity, elements of card system 10' which are substantially the same as elements provided for card sys-tem 10, are given like numbers. The concept of data pro-cessing card system 10' is to provide a layered system which is utilized for providing additional circuit chip devices 14 with increased logic circuitry while simul-taneously maintaining a relatively thin overall housing structure.
As was the case in data processing card system 10, embodiment data processing card system 10' includes first flexible film carrier member 16 which interfaces and is contiguously located with respect to substrate carrier top surface 34. As seen in FIG. 4, first flexible film carrier 16 includes first flexible film carrier lower surface 50 through which there is shown connective open-ings 52 for coupling of circuit chip devices 14 to first substrate electrical pattPrn 40 (shown in FIG. 2). It is to be understood that substrate carrier top surface 34 shown in FIG. 4 contains first substrate electrical pattern 40 which has been described in connection with data processing card system 10 as shown in FIGS. 1-3.
As shown in FIG. 4, substr.ate carrier member 30 includes substrate carrier member lower surface 54 which has formed thereon lower surface electrical leads 56 formed into second substrate electrical pattern 58 in a manner similar to that provided for data processing card system 10 as previously described. Lower surface leads 56 of second substrate electrical pattern 58 extend to substrate carrier edge face 38 and terminate in electrically connective pin member 36 for electrical coupling to external devices.
Second flexible film carrier 60 carrying and having mounted thereon a plurality of circuit chip devices 14 as shown in FIG. 5 is mated to substrate carrier lower surface 54. Second flexible film carrier 60 includes connective openings 62 for interfacing and connecting circuit chips 14 to second substrate electrical pattern 58. Upper surface 64 of second flexible film carrier member 60 is matingly engaged with substrate carrier lower surface 54 in the substantially identical manner that first flexible film carrier lower surface 50 is matingly engaged with substrate carrier top surface 34. It is to be understood that electrical coupling of circuit devices 14 on first film carrier member 16 may be electrically coupled to circuit devices 14 on second flexible film carrier 60 through interconnection openings or other conn-ectable means passing through substrate carrier member 30.
Thus, first and second electrical patterns 40 and 58 may be formed on opposing surfaces 34 and 54 of substrate carrier member 30 to provide a dual sided interconnect system. In this manner, a plurality of flexible film carrier members such as 16 and 60 may be seen to be mounted on opposing surfaces of substrate carrier member 30 to provide increased design logic considerations for data processing card system 10'.
Referxing now to FIG. 8, there is shown a mechanism for electrically coupling at least a pair of circuit chip devices 14 each to the other between a predetermined contact area 26. As will be seen in following paragraphs, the chip electrical coupling mechanism is sandwiched between substrate carrier member 30 and first and second flexible carrier members 16 and 60. The electrical coupling mecha-nism shown in FIG. 8 may be utilized where the diminished area and distances of between circuit chips 14 do not permit all of the necessary electrical contacts being completed.
Referring now to FIG. 8, there is shown a mechanism for electrically coupling at least a pair of circuit chip devices 14 each to the other between a predetermined con-tact area 26. As will be seen in following paragraphs, the chip electrical coupling mechanism is sandwiched between substrate carrier member 3G and first and second flexible carrier members 16 and 60. The electrical coupling mecha-nism shown in FIG. 8 may be utilized where the diminished area and distances between circuit chips 14 do not permit all of the necessary electrical contacts being completed.
In the case where additional contact and electrical leads are necessitated, there is provided chip coupling flexible carrier member 66 for electrically coupling prede-termined contact regions 26 of separate circuit chips 14 each to the other. As was the case with first and second flexible carrier members 16 and 60, chip coupling flexible carrier member 66 incluaesan electrically insulat-ing tape member having opposed first and second surfaces 68 and 70. Chip coupling carrier member 66 further includes a plurality of electrically conductive chip coupling lead members 72 which are secured to first surface 68 of the electrically insulating tape member. Chip coupling lead members 72 may be generally of the same foil layer construc-tion as that provided and described for electrically conductive foil layer 20 and leads 24 of first carrier member 16.
First surface 68 of chip coupling flexible carrier member 66 is mounted adjacent to surface 50 of first flexible carrier member 16 and/or adjacent surface 64 of second carrier member 60. Pin members passing through opening 62 and/or 52 of associated carriers 60 and 16 contact chip coupling lead members 72 and such pin members may be connected to a predetermined electrical lead 24 to provide electrical coupling between individual circuit chips 14. Thus, in the ~mbodiment shown in FIGS~ 1-3, chip coupling flexible carrier member 66 would be sandwiched between first flexible film carrier member 16 and substrate carrier member 30. In the embodiments shown in FIGS.
4 and 5, data processing card system 10' would include a pair of chip coupling flexible carrier members 66 sand-wiched between first flexible carrier member 16 and sub-strate planar member 30 as well as second flexible carrier member 60 and substrate planar member 30 respectively.
In order to provide coupling between chip devices 14 on carrier members 16 and 60 and associated portions of first and second substrate electrical patterns 40 and 58, chip coupling openings 74 may be provided to allow other lead pin members to extend therethrough.
Referring now to FIG. 9~ there is shown an embodiment of data processing card system 10 as provided in FIGS.
1-3. It is to be understood that the embodiment shown in FIG. 9 is equally applicable to data processing card system 10' as it is to card system 10. In the cross-section shown in FIG. 9, substrate carrier member 30 is seen to be extended beyond the peripheral boundaries of upper and lower plastic layers of 42 and 44 as well as beyond first $1exible film carrier member 16. As can be understood, substrate carrier member 30 provides for additional surface area 76 to aid in any additional heat dissipation which may be necessitated. As was the calcu-lation of substrate carrier surface edge thickness 38, additional surface areas 76 may be calculated based upon the heat dissipation requirements necessitated by the particular heat generating logic circuitry contained within card system 10 or card system 10'.
Claims (31)
1. A data processing card system, comprising:
(a) means for mounting at least one circuit chip device, said circuit chip mounting means including first flexible carrier means comprising an electrically insulating tape layer member having at least one aperture formed therethrough for registry with predetermined elec-trically active areas of said chip device and a plurality of electrically conductive load members secured to said insulating tape member and extending within said aperture for coupling to said active areas of said chip device;
(b) substrate carrier means formed of a substan-tially rigid, electrically insulated and thermally conductive member composition located adjacent said circuit chip device mounting means, said substrate carrier means having at least a first predetermined electrical lead pattern formed thereon, said first electrical lead pattern being electrically coupled to predetermined contact areas of said circuit chip device; and, (c) means for substantially isolating said com-bined substrate carrier means and said circuit chip device mounting means from an external environment.
(a) means for mounting at least one circuit chip device, said circuit chip mounting means including first flexible carrier means comprising an electrically insulating tape layer member having at least one aperture formed therethrough for registry with predetermined elec-trically active areas of said chip device and a plurality of electrically conductive load members secured to said insulating tape member and extending within said aperture for coupling to said active areas of said chip device;
(b) substrate carrier means formed of a substan-tially rigid, electrically insulated and thermally conductive member composition located adjacent said circuit chip device mounting means, said substrate carrier means having at least a first predetermined electrical lead pattern formed thereon, said first electrical lead pattern being electrically coupled to predetermined contact areas of said circuit chip device; and, (c) means for substantially isolating said com-bined substrate carrier means and said circuit chip device mounting means from an external environment.
2. The data processing card system as recited in Claim 1 including a plurality of circuit chip devices coupled to said circuit chip device mounting means.
3. The data processing card system as recited in Claim 2 where a predetermined set of circuit chip devices are electrically coupled to said first electrical lead pattern formed on said substrate carrier means.
4. The data processing card system as recited in Claim 2 where at least one of said circuit chip devices is a chip memory device.
5. The data processing card system as recited in Claim 4 where at least one of said chip memory devices is an electrically erasable programmable read only memory device.
6. The data processing card system as recited in Claim 1 where at least one of said electrically conductive lead members is coupled to said circuit chip device on an upper surface and is coupled to said first electrical lead pattern on a lower surface.
7. The data processing card system as recited in Claim 1 where said electrically conductive lead members are formed of an electrically conductive foil layer.
8. The data processing card system as recited in Claim 1 where said circuit chip memory is an electrically erasable programmable read only memory device.
9. The data processing card system as recited in Claim 1 where said substrate carrier means is formed of a substantially electrically insulative material composi-tion.
10. The data processing card system as recited in Claim 9 where said substrate carrier means is formed of a substantially thermally conductive material compo-sition.
11. The data processing card system as recited in Claim 1 where said substrate member is substantially planar and includes an upper surface having said first predetermined electrical lead pattern formed thereon.
12. The data processing card system as recited in Claim 11 where said first predetermined electrical lead pattern is photo-etched into said upper surface of said substantially planar substrate member.
13. The data processing card system as recited in Claim 11 including means for electrically coupling at least a pair of circuit chip devices each to the other between predetermined contact areas, said chip electrical coupling means being sandwiched between said substrate carrier means and said circuit chip mounting means.
14. The data processing card system as recited in Claim 13 where said chip electrical coupling means in-cludes first chip coupling flexible carrier means for electrically coupling said predetermined chip contact areas each to the other.
15. The data processing card system as recited in Claim 14 where said first chip coupling flexible carrier means includes:
(a) an electrically insulating tape member having opposed first and second surfaces; and, (b) a plurality of electrically conductive chip coupling lead members secured to said first surface of said electrically insulating tape member, said second surface of said electrically insulating tape member being positionally located adjacent said upper surface of said substantially planar substrate member.
(a) an electrically insulating tape member having opposed first and second surfaces; and, (b) a plurality of electrically conductive chip coupling lead members secured to said first surface of said electrically insulating tape member, said second surface of said electrically insulating tape member being positionally located adjacent said upper surface of said substantially planar substrate member.
16. The data processing card system as recited in Claim 12 where said first predetermined electrical lead pattern includes at least one electrical coupling line extending to a peripheral boundary of said substantially planar substrate member for electrically connecting said data processing system to an external electrical device.
17. The data processing card system as recited in Claim 11 including at least a second predetermined elec-trical lead pattern formed on a lower surface of said substantially planar substrate member.
18. The data processing card system as recited in Claim 11 where said substantially planar substrate member includes an edge boundary surface area substantially ex-posed to said external environment for dissipation of heat therefrom.
19. The data processing card system as recited in Claim 1 where said isolation means includes a pair of substantially planar layer members coupled to said com-bined substrate carrier means and said memory chip device mounting means on opposing sides thereof.
20. A method of forming a data processing card sys-tem including the steps of:
(a) securing at least one circuit chip device to at least a first flexible carrier member;
(b) forming a first predetermined electrical lead pattern on an upper surface of a substantially rigid, electrically insulative, and thermally conductive substrate carrier member; and, (c) electrically coupling said circuit chip device to said first electrical lead pattern formed on said substrate carrier member.
(a) securing at least one circuit chip device to at least a first flexible carrier member;
(b) forming a first predetermined electrical lead pattern on an upper surface of a substantially rigid, electrically insulative, and thermally conductive substrate carrier member; and, (c) electrically coupling said circuit chip device to said first electrical lead pattern formed on said substrate carrier member.
21. The method of forming a data processing card system as recited in Claim 20 where the step of securing said circuit chip device is preceded by the step of pro-viding said first flexible carrier member having an elec-trically insulating tape layer member and an electrically conductive layer member secured each to the other.
22. The method of forming a data processing card system as recited in Claim 21 where the step of providing said first flexible carrier member includes the step of removing predetermined portions of said electrically con-ductive layer member to form a plurality of electrically conductive lead members.
23. The method of forming a data processing card system as recited in Claim 20 where the step of securing said circuit chip device includes the step of aligning said circuit chip device with at least one aperture formed through said first flexible carrier member.
24. The method of forming a data processing card system as recited in Claim 23 where the step of aligning said circuit chip device is followed by the step of bond-ing said circuit chip device to at least one electrically conductive lead member extending internal the perimetrical boundary of said aperture.
25. The method of forming a data processing card system as recited in Claim 20 where the step of securing includes the step of coupling a plurality of circuit chip devices to said first flexible carrier member.
26. The method of forming a data processing card system as recited in Claim 20 where the step of forming said first predetermined electrical lead pattern on said upper surface includes the step of etching said first predetermined electrical lead pattern into said upper surface of said substrate carrier member.
27. The method of forming a data processing card system as recited in Claim 20 where the step of forming said first predetermined electrical lead pattern is followed by the step of forming a second predetermined electrical lead pattern on a lower surface of said substrate carrier member.
28. The method of forming a data processing card system as recited in Claim 27 where the step of forming said second predetermined electrical lead pattern includes the step of extending at least one lead line from said lead pattern to a peripheral boundary of said substrate carrier member for electrical coupling to an external electrical device.
29. The method of forming a data processing card system as recited in Claim 27 where the step of forming said second predetermined electrical lead pattern includes the step of etching said second predetermined electrical lead pattern into said lower surface of said substrate carrier member.
30. The method of forming a data processing card system as recited in Claim 20 including the step of se-curing a plurality of circuit chip devices to at least a second flexible carrier member.
31. The method of forming a data processing card system as recited in Claim 20 including the step of sub-stantially encapsulating said combined first flexible carrier member and said substrate carrier member.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/567,743 US4539472A (en) | 1984-01-06 | 1984-01-06 | Data processing card system and method of forming same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1242528A true CA1242528A (en) | 1988-09-27 |
Family
ID=24268464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000488560A Expired CA1242528A (en) | 1984-01-06 | 1985-08-12 | Data processing card system and method of forming same |
Country Status (2)
| Country | Link |
|---|---|
| AU (1) | AU574824B2 (en) |
| CA (1) | CA1242528A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE301127T1 (en) * | 1987-07-31 | 1989-08-24 | Texas Instruments Deutschland Gmbh, 8050 Freising | TRANSPONDER ARRANGEMENT. |
| EP0408588A4 (en) * | 1988-03-11 | 1991-08-21 | Magellan Corporation (Australia) Pty. Ltd. | Inductive element and method of manufacture |
| FR2631200B1 (en) * | 1988-05-09 | 1991-02-08 | Bull Cp8 | FLEXIBLE PRINTED CIRCUIT, IN PARTICULAR FOR ELECTRONIC MICROCIRCUIT CARDS, AND CARD INCORPORATING SUCH A CIRCUIT |
-
1985
- 1985-08-12 CA CA000488560A patent/CA1242528A/en not_active Expired
- 1985-08-15 AU AU46237/85A patent/AU574824B2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| AU4623785A (en) | 1987-02-19 |
| AU574824B2 (en) | 1988-07-14 |
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