CA1198221A - Digital data processing system with memory control - Google Patents

Abstract

ABSTRACT

A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability.
The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a malfunction nibble shifter, and a high speed look-aside memory control.

Description

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DIGITAL DAT~ PROCESSING SYSTEM/420 Cross Reference To Related Applications The present applica-tion is related, in part, to copending Canadian Patent Applica-tions Serial Numbers 439,755, 439,798, 439,799, 439,800~ 439,801, 439,802 and 439,803 all filed October 26, 1983.
1. Field of the Invention The present invention relates to a hlgh speed, compact data processing system an~, more particularly, to circuitry therein to enhance operating speed, efficiency and capabilities of such a system.

2. Description of ~rior Art A common practice in the computer industry is for a manufacturer to ~rovide a family of related computer, or data processing, systems. Various computers in such a family will be distlnguished by size, complexity, capability and cost. Because of cost and, therefore, complexity constraints, lower level sys-tems in such a family are usually not able to ~rovide the capabilities and functions of the higher level systems. A lower level system may not, for example, provide as high a speed of operation or as large a memory space as a higher level system. In addition, a lower level system of-ten may not be able to execute a prog.ram written for a r~

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higher level system because the lower level s~s-tem does not offer the full functions and capabilities oE the higher level system. Such a family of systems may therefore have upward compatibility, that is, programs written on lower level systems may be executed on higher level systems, but will not provide corresponding downward compatibility. For full compatibility withln a computer system family, the lower level systems should offer, in general, the functionality and capabilities oE the higher level systems.
The present invention provides computer system improvements which bear upon the above noted computer system capabilities, thus improving computer system speed, efficiency and ca~ability, and also providing a solution for the aforementioned problems and limitations of the prior art, as will be discussed in detail herein below.
SUM~RY OF THE INVENTION
The present invention relates to computer system elements providing increased capability and efficiency, and more particularly to a computer svstem having associated with its memory means a memory control means including an cr/"~) .
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internal bus for data and check bits, check bit checking and providing means, and a bidirectional buffer It is thus advantageous to incorporate the present invention into a computer system because capability and efficiency is increasedO
It is thus an object of the present invention to provide an improved computer system.
It is another object of the present invention to provide an improved computer system providing increased speed and efficiency of operation.
It is yet another object of the present invention to provide an improved computer system providing increased capability and functionality.
Other objects and advantages of the present invention will be unders-tood by those of ordinary skill in the ar-t, after referring to the following detailed cr/~

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description of a preferred embodi.ment and drawings wherein:
Bl~IEF DESCRIPTION OF DRAWINGS
Fig. 1 is a block diagram of a computer system incorporating the present invention;
Fig. 2 is an illustration of certain~ typical instructions;
Fig. 3 is a diagrammic representation of a single level address translation;
FigO 4 is a diagrammic representation of a two level address translation;
Figs. 5 and 5A are a detailed block diagram of the present system control unit;
Figs. 6 and 6A are a detailed block diagram o the present system processor unit, and Fig ~ is a detailed block diagram of a portion of a memory control unit.

~ESCRIPTIn~_QE_T~E PREFERREP EM~ODIMENT

The following description presents the structure and operation of a computer system incorporating a ~' ~9~

presently preerred embodiment o the present invention7 In the following description~ the general structure and operation of the present system will first be described in an introductory overview. Next, certain basic features of the present system will be further described as a further introduction to following detailed descriptions of the system The system will then be described in detail, followed by yet further detailed descriptions of certain features of the present syStem as necessary.
Certain conventions are used throughout the following descriptions to enhance clarity of presentation. First, each figure element referred to in the following descriptions will be referred to by a three or four ~igit reference number. The most significant digit of a three digit reference number or most significant two digits of a four digit reference number identify the particular figure in which an element referred to by that reference number first appears. The two least significant digits of a particular r~ference number identify the particular element appearing in that figure. For example, ~9~3Z~L

reference number 319 refers to the ninteenth element appearing in Figure 3 while reference number 1020 refers to the twentieth element appearing in Figure 10. A
particular reference number assigned to a particuLar figure element is therefore always used to refer to that particular figure element. Therefore, element 319~
which first appears as element 19 in Figure 3, will thereafter be referred to by reference number 319 in all figures or descriptions.
Ne~t, certain of the figures presented in conjunct1on with the following descriptions may occupy more than one drawing page. In such instances, a common figure number will be assigned to the drawing pages comprising that figure, and a letter designation will be appended to identify a particular drawing page of the figure. For example, figure 3 may occupy three drawing pages. The ~irst page will be identiied as Fig. 3, the second as Fig. 3A, and the third as Fig. 3B.
Finally, interconnections between related circuitry or system elements may be represented in two ways.
First, inter~onnections between~ system elements may be represented by common signal names or references rather than by drawn representations of wires or buses.
Second, common connections between circuitry or system elements may be indicated by a bracket terminating a lead and enclosing a designation o~ the form "A-b". IIAII
indicates other igures having a connection to the same common point while "b" designates a particular connection point.

INTRQ~T~Q~Y OVERVIEW

- The following introductory overview will first identify and briefly describe the major elements of the present digital computer system. Certain Xeatures of operation of the present system will then be described in furthe-r detail as an introduction to ~ollowing detailed descriptions of the present system.
A. ~ em Overyiew (Fiq. 1) Referring to fig. 1, a block diagram of Computer System (CS) 101 is shown. Major elements of CS 101 are Memory (MEM) 10~, Control Unit (CU) 104, and ~rocessor Unit (~U~ 106. MEM 102 is used to store, for example, user programs comprising data and instructions. MEM 102 is described in detail in related copending Canadian Patent Application Serial No. 441,238, filed October 26, 1983.
MEM 102 will not be described in further detail herein except as necessary for understanding of the structure and operation of the remaining elements of CS 101. CU 104 and PU 106, which will be descrihed in de-tail in the following descriptions, respectively perform system control and program execution functions.
Major buses of CS 101 include Memory Address (MAD) Bus 108, which conducts memory read and write addresses from PU 106 and CU 104 to MEM 102. Memory Data ~A~ Bus 110 conducts data and instructions from MEM 102 to CU 104 and PU 106. Data (D) Bus 112 is connected between CU 104 and PU 106 as a primary path of information exchange between CU 104 and PU 106.
Referring to CU 104, major elements of CU 104 are Instruction Prefetch and Decoder (IPD) 114, Microsequencer (US) 116, Memory Control (MC) 118, and System Clock Generator ~SCG) 120. IPD 114 is connected from MDA Bus 110 to receive instructions from MEM 102.

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, ., ~d IPD 114 operates in conjunction with certain elements o~
PU 106 to perform instruct.ion prefetch operations/ in addition, IPD 114 performs certain initial instruetion deeode operations, for example, with respect to instruetion and data type, to initially determine eertain subsequent o~erations to be performed by CU 104 and PU 106 with respeet to exeeution of reeeived instruetions. IP~ 114 provides eertain outputs to D Bus 112, for example, inforination used by PU 106 in addressing and fetehing data from MEM 102. IPD 114 also provides instruction outputs to US 116 for use by US 116 in eontrolling operations of CS 101.
As will be deseribed in detail in following deseriptions, US 116 ineludes memory and logic or ~roviding mieroinstruetion eontrol of CS 101. In addition to eertain outputs described below to D Bus 112, US 116 provides eontrol outputs to other elements of CS 101 and aeeepts eontrol inputs from other elements of CS 101.
~ inally, SCG 120 comprises a central eloek generator whieh prcvides elock outputs to all elemenl:s o CS 101. For elarity of presentation, the cloek _g_ :

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outputs of SCG 120 are not shown individually, but will be described in the following detailed descriptions as appropriate.
Referring to PU 106, as described above PU 106 performs functions directly associated with execution of user's programs~ In this respect, Central Processing Unit Processor (CPUP) 122 performs arithmetic and logic functions and is connected between D Bus 112 and Y Bus ~24. Y Bus 124 is an inormation transfer path within PU 106. Nibble Shifter (NIBS~ 126, also connected between D Bus ~12 and Y Bus 124, operates in conjunction with CPUP 122 and other elements o CS 101 to per~orm, or example, nib~le shifting, memory address and data alignment operations.
Scratch Pad and Address Translation Unit (SPAD) 128 is a multifunction element also connected between D Bus 112 and Y Bus 124. SPAD 128 operates as a scratch pad memory for PU 106 and also perorms certain address mapping operations, as will be described in detail in the following descriptions.
Memory ~ddress Unit (MAD) 130 is connected from SPAD 128 and has outputs connected to MA~ Bus 108 MAD

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130 provides read and write addresses to MEM 102. In addition to other functions, MAD 130 operates in conjunction with IPD 114 to perform instruction prefetch operations~
Memory Data Buffer (MDB) 132 is connected be~ween MDA Bus 110 and D Bus 112 and Y ~us 124 and is a primary path for data transfer between PU 106 and ME~I 102.
Finally, Serial I/O (SIO) 134 and Data and Burst Multiplexer Channel I/O (DBIO) 136 operate as principal paths of information exchange between CS 101 and external devices~ such as terminals and bulk memory storage units. SIQ 134 is used for communication of serial information between CS101 and, for example, a ter~inal DBIO 136 provides, for example, three modes of parallel information transfer, such as, Programmed I/O, Data Channel I/O, and a Burst Multiplexer Channelr As indicated in Fig. 1, SIO 134 has a bi-directional connection from D Bus 112 while DBIO has an input path from D Bus 112 and an output path to Y Bus 124.
Having briefly described the overall structure and functional elements of CS 101 with reference to Fig. 1, , . .. .

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certain basic features of CS 101 will be described next below.
B. ~o1~1I=u~ e~--The present implementation of CS 101 is as a 32 bit computer system; that is, CS 101 generates and manipulates 32 bit addresses and 32 bit data elements.
CS 101 is desisned to be compatible with t~o earlier generations of data processing systems, that is, capable of executing programs created for use on the earlier data processing systems. One earlier family of data processing systems is a 16 bit system, for example~ the Data General Corporation ECLIPSE~ computer systems. A
second earlier family of computer systems are 8 bit systems, for example, Data General Corporation NOVA~
computer systems. As such, CS 101 is capable of executing three different instruction sets, the NO~A
instruction set, the ECLIPSE instruction set, and a new instruction set/ that for the Data General Corporation LECLIPSE MV/8000~ systemsO Each of these instruction sets contain two classes of instructions: Arithmetic and Logic Class (ALC) instructions,~ which define an ~, .
arithmetic or logic operation to be performed, and memory reference instructions, which define operations to be performed with data to be written into or read from memory~ ALC instructions in general include only an operation code (opcode~ field defining the operation to be performed. In kmemory reference instructions, a displacement field containing information relating to the location, or address, of the data to be operated upon is added to the opcode field. NOVA instructions use 8 bit opcode fields ~hile ECLIPSE and MV/8000 instructions use 16 bit opcode fields. NOVA and ECLIPSE
in~tructions use, respectively, 8 and 16 bit displacement fields, while ~V/8000 instructions use 16 or 32 bit displacement fields. NOVA and ECLIPSE
instructions are referred to as "narrow" instructions and ,~V/8000 instructions as ~wide n instructions~
CS 101's instruction set allows CS 101 to manipulate data elements having widths of 8, 16, or 32 bits, In addition, and as will be described further below, CS 101 is capable of generating addresses .n two ranges. The first range, using 32 bit addresses, allows CS 101 to address a logical address space of 4.3 billion bytes, or four gigabytes. The second, using 16 bit .. . .
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addresses~ allows CS 101 to utilize a 64 kilabyte addressing range. - 3 During the following descriptions, a byte is defined as 8 bits of information, a word is defined as 16 bits (2 bytes)~ and a double word is defined as 32 bits ~2 words, or 4 bytes). In general, most operations performed by CS 101, for e~ample, generation of addresses and manipulation of data, are performed in double word (32 bit) elements.
c. ~n~ l As described above, CS 101 may utilize 32 bit addresses for byte addressing, or 31 bits in word addressing,and thereby has a logical address space, that is, a user visible address space, of four gigabytes.
This logical address space is partitioned for purposes of memory management into eight 512 megabyte sections called segments and referred to as segments O to 7.
Each logical address contains, in the three most significant bits, information identifying a particular segment in which a data item is located. The remaining 29 bits identify the location of the data item in the segment.

The size of CS lOl's logical address space means that not all logical address locations can be represented in MEM 102 at the same time. For this reason, CS lOl's logical address space is further divided into pages. Each page is a two ~ilobyte block of contiguous logical or physical addresses. A demand paging system moves pages between MEM 102 and external storage devices upon demand and tracks pages currently in MEM 102. An address translation unit, described in detail below, translates logical addresses into corresponding physical addresses in MEM 102 for pages represented in M~M 102.
Logical a~dresses may use to reference two types of information, data and instructions. To reference instructions, PU 106 uses logical addresses generated by a program counter (PC), located in PU 106, which is incremented to read sequential instructions from memory.
As described above, bits 1 to 3 o the PC specify a cur~ent segment from which instructions are being read, while bits 4 to 31 specify an address within that seg~ent. It should be noted that logical addresses generated by the PC contain 31 bits of address rather ~15-I

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than 32 as CS lCl performs addressinng on the word level~ As will be described further below, CS 101 actually reads or writes only double words to and from MEM lQ2, thus requiring 30 bits of address rather than 31 or 32 bits.
- In contrast to instructions, which are addressed directly, data is addressed indirectly through instructions. C5 101 utili~es information coded in the referencing instructions to construct the logical addresses of the data so referenced. Among other factors~ data appears in different types and le~gths and the structure of the data effects the generation of logical addresses referencing data~ The Data types may include, for example fixed point numbers, floa~ing point numbers, decimal numbers, alphanumeric character strings, and bit strings. Data lengths may,for example, include bits, bytes (8 bits), words (16 bits), and double words (32 bits). In addition~ the locations of various data items may be specified as a displacement, or offset, relative to various base addresses, as will be described below.

To reference an element of information in logical memory, therefore, a referencing instruction will provide information used by CS 101 to construct a logical address of the referenced data item. Various typical instruction formats used in CS lOl and containing such information are illustrated in Fig. 2.
The instruction illustrated on line A represents a narrow instruction of 8 bits, while the inst~uc,ions illustrated on the remaining lines represent typical 16 and 32 bit instructionsr as previously described. As shown in ~ig. 2, each instruction includes an Operation, (OP) Code indicating an operation to be performed with the referenced data, and an Accumulator (AC) Field designating a source or destination accumulator as appropriate.
Each instruction includes a displacement ield of 8, 15, 16, 31, or 32 bits, depending upon whether the instruction is referencing a byte or a word of data.
Each instruction further includes an inde~ bit field (e) identifying the source of the base address from which the displacement ~offset) speci`fied in the displacement field is taken to determine the ~ogical address. The ' I

8~

inde~ bits are capable of specifying rour different addressing modes, that is, four different sources for a base address from which displacement is taken to locate the data referred to by the instruction displacement fiel~. A first mode lis Absolute mode and uses logical address z2ro as base address. A second mode is Program Count ~PC~ relative wherein the present PC address is used as base address. The remaining two modes select as base address the contents of either of two accumulator regis~ers residing in PU 106. Both the instructions and the logical addresses resulting from the operation described above contain a single bit ~ield which identifies whether the logical address i9 a final logical address, or whether indirect addressing has been specified. In indirect addressing, a logical address resulting from resolution of the instruction is treated as a pointer to yet another address. The address pointed to may, in turn, be a final logical address or, as indicated by its indirect bit field, may be an indirect pointer to yet another logical address.
Finally! as previously described the logical address space of CS 101 is larger than the physical 382~.

address space of MEM 107 As such, two Rbyte pages of information storage containing instructions or data, or both, are transferred between MEM 102 and external storage devices as required. As a result, logical addresses generated by CS 101 must thexefore be translated into equivalent physical addresses in MEM 102 of pages residlnq therein.
CS 101 performs logical to physical address translation operations through the use of Page Tables (PTs) and Segment Ease Registers (SBRs), A PT is a table of entries containing information for translating logical addresses to a physical addresses~ Each entry in a PT, referred to as a Page Table Entry (PTE~, contains the necessary information relevant to one page of storage residi.ng in MEM 102. In conjunction, there exists a SBR for each sesment of CS 101's logical address space. Each 5BR contains the physical base address of a PT containing entries for those pages of the corresponding segment residing MEM 102. The contents of each SBR indicates whether the corresponding segment is c~rrently defined, t~at is, usuable by CS
101, the number of PT levels necessary for logical address translation, as will be described further below, and the address translation information.
Each PTE contain~ information indicating whether a particular page is currently defined, that is, accessible to CS 101, and whether the corresponding page is presently residing in ME~I 102. Each PTE also contains information regarding access rights to the information stored in the corresponding page; that is, whether a reference to the corresponding page may perform a read operation, a write operationt or execute instructions contained therein9 Each PTE also contains physical page address information defining the physical address or location in MEM 102 of the page corresponding to a particular logical address. The physical address contained in each PTE may reference either o. two items, depending upon whether a one level PT translation is to be performed or a two level PT translation is to be perormed. If a one level translation is to be performed, the PTE physical address contains the physcial address of the page referenced by the corresponding logical address. If a two level translation is to be perormed, the PTE address field -2()-z~

contains the address of a second PT, which in turn contains the final physical address of the page referenced by the logical address. The utilization of both one and two level PT translations allows CS lOl's address space to be tailored to a particular user programO For a smaller progrzm, a one level mechanism would be utilized, while for largex programs two level translations would be performed.
Referring to Fig. 3~ a diagramic representation of a one level page table translation is shown.
Represented therein is a logical address to be tra~lslated, one of CS lOl's SBRs, and a typical page table containing a plurality of P~Es.
As indicated in Fig. 3, the logical address includes an SBR Field identifying a particular one of CS
lOl's SBRs, in this case the SBR represented in Fig. 3, a single level page table address field, and a page of~set field. CS 101 utilizes the SBR field of the logical address to select a corresponding one of CS
lOl's eight SBRs. CS 101 reads from that SBR a physical address field which identifies the start, or base address, of a corresponding page table, that is, the 3Z2::L

page table represented in Fig. 3. The single level page table address field of the logical address represents an offset, from the start of the page table located by the physical address field of the SBR, to the particular PTE
containing the physical address information corresponding to the logical address to be translated.
Together, therefore, the physical address ield of .he SBR identified by the SBR field of the logical address and the single level page table field of the logical address identify the physical address of a corresponding PT~ in the page table.
A PTE so identified includes, as indicated in Fig.
3, a valid resident physical address field which identifies the physical starting address of a particular page residing in MEM 102. The page offset field of the logical address specifies an offsetl relative to the start of the page in MEM 102 identified by the valid resident physical address field, of the PTE of the particular word to be addressed. The physcial address field of the PTE and the page offset field of the logical address thereby together comprise the physical address in MEM 102 of the word referenced by the logical ~132Z~

address represented in Fig. 3 and the logical to physical address translation has been completed~
Referring to Fig. 4, a two level page table translation is represented. As indicated therein the general procedure for a two level page table translation is si~ilar to that of a one level page table translation except that an additional re-erence through a second page table is performed. The logical address includes, in addition to the single level page table address field, a double level page table address field. The double level page table address field of the logical address is utilized, together with the physical address field of the 5BR identified by the SBR field of th,e logical address, to generate a physical address of a particular PTE in a first page table. The valid resident physical address ield of the PTE of the first page table is then combined with the single level page table address field of the logical address to geneIate a physical address of a second PTE in a second page table.
In this case, the valid resident physical address field o the PTE of the first page table identifies the physical starting address of the second page table. r~he ~23-~v~

single level page table addxess field of the logical word address identifies an offset, relative to the start of the second page table, of the second PTE. The physical address field of the second PTE is then combined with the page offset fleld of the logical address to generate the final physical address reerred to by the logical address~

Finally, as descri~ed above, CS 101 transfers pages between MEM 152 and extenal storage as necessary. This operation is performed by CS lOl's memory management system, of which CS lOl's address translation mechanism is a part. CS lOl's address translation mechanism performs, in particular, two functions with regard to CS
lOl's memory management mechanismO First, CS lOl's address translation mechanism monitors which of the pages resident in MEM 102 are re~erenced in read or write operations, and which pages are most frequen~ly referenced. When it is necessary to transf~r a page out of MEM 102 to external storage in order to transfer in another page, CS lOl's memory management system utilizes this reference in~ormation to determine which pages have not been referenced or have been least frequently referenced in determining which pages resident in MEM
102 can be xeplaced~ Secondly, CS lOl's address translation mechanism monitors which of the pages in MEM
102 have been referenced by write operations, that is, which pages in MEM 102 have been modified and are no longer identical to the copies Or those pages residing in external storage. If a particular page has been referenced in a write operation, it is necessary for CS
lQ1 to copy that page back external storage when that page is replaced by another page from external storage.
If that particular page has not, however, been referenced in a write operation, CS 101 may simply discard that page by writing a new page from external storage into the same address locations in MEM 102, thereby red~cing the execution time ~equired for a page swap. CS lOl's address translation mechanism stores the above described memory management information, in the form o~ re~erenced/modified bits, in MC 118, which will be described in greater detail below.

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Having described the overall structure and operation and certain basic features of CS 101 above, CS
101 will be described below in further detail. CU 104 will be described first, followed by PU 106.
Referring to Figs. 5, 5A, 6 and 6A, these figures comprise a detailed block diagram of CU 104 and PU 106-Figures 5 and 5A present C~ 104 and Figures 6 and 6A
present PU 106. Figures 5, 5A, 6 and 6~ may be placed side to side, in that order from left to right, to comprise a complete detailed block diagram o CU 104 and PU 106. For purposes of certain of the following discussions, it will be assumed that the reader has so assembled Figures 5 and 6 into such a block diagram.
A. C~ lO~ (~igs 5 an~ 5O
Referring to CU 104 in Figs. 5 and SA, as previously described the major elements of CU 104 are Microsequencer (US) 116, Instruction Prefetch and Decode (IPD) 114~ Memory Control ~MC) 118, and System Clock Generator (SCG) 120. These elements will be described next ~elow in that Re~erring to US 116, US 116 contains CS lOl's microcode control lo~ic, including microcode memories ~L~L9~

for storing microinstruction sequences for controlling operation of CS 101, microcode sequencing control logic for selecting and manipulating microinstruction sequences, and condition logic for providing-microinstruction control o CS 101 in response to certain conditions occurring therein and, for example, branches in microinstruction sequences. Microcode control functions provided by US 116 also include microcode state save and restore mechanisms for use in executing microcode traps and interrupts. In addition to the above functions directly concerned with execu~ion of users programs, US 116 also provides all console control functions through the provision of microcode therein directly responsive to commands entered through a soft console, that is, a user keyboard as opposed to front panel switches.
As will be described further below, US 116 microcode resides in three microcode memories, reflecting the microcode organization of CS 101. A
first microcode set, referred to as kernel microcode~
resides permenently in US 116, as does horizontal microcode. Vertical microcode is not permanently . ,i ~1 322~

resident in US 116. That is, vextical microcode is stored in Random Access Memories (RAMs~ comprising writable control store and are loaded into CS 101 ~t system star~up. Briefly, kernel microcode reside~
permenently in VS 116, and in addition to providing console and other functions~ is available at system startup to perform system initialization, including loading of vertical microcode. Typically, vertical microcode will reside in external memory devices, such as-disk memories. At time s~stem's initializationr vertical microcode is read from external memory and, under control of kernel microcode, is transferred into ME~ 102 a file to reside therein. Then, still under control of kernel microcode, vertical microcode is read from MEM 102 and loaded into vertical microcode memory in US 116. At that time, the full functionality o~ CS
101 is available.
The core of US 116's microsequencer is comprlsed o~
Microsequence Con~rol Logic (USCL) 500. USCL 500 is comprised, for example, of 4 AMD AM2930 bit-slice program control units connected in parallel. USCL 500 includes logic to implement Microprogram Count (UPC) PP

322~L

increment, a seventeen word deep last in first out stack, a separate register as a source of microinstruction addressesv an input port for j~mping out cf sequential microprogram execution, and an output port for providing microinstruction addresses to US
116's microcode memories. USCL 500 also includes an lnternal microprogr~m control unit for control]ing operation of USCL 500.
USCL 500's microinstruction address output is provided from the output of Microinstruction Address Multiplexer (UAM) 502. UAM 50~ is provided ~ith a first input from USCL 500's input, which is connected from Microinstruction Input (UIN) Bus 504. A second input of UAM 502 is connected from Microinstruction Address Register (UAR) 506, whose input is connected from Microinstruction Address Register Multiplexer (UARM) 508. UARM 508 is provided with a first input connected from USCL 500's input, that is~ from UIN Bus 504, and a second input from output of U~ 502. UAM 502's third input is connected from output of Microstack (USTACK) 510; as described above, USTACK~510 is a seventeen word deep last in first out stack. USTACK 510 has a first ~313'~

input connected from UIN Bus 504 and a second input connected USCL 500's microprogram counter, described next below. UAM 502's fourth input is simi1arly sonnected from the output of USCL S00's microprogram counterO
USCL 500's microprogram counter includes Microprogram Counter Register (UPCR) 514 whose output is cQnnected to inputs of UAM 502 and USM 512. Input of UPCR 514 is connected from output of Microprogram Count Increment (UPCI~ 516, which has an input connected from k2icroprogr~m Count Multiplexer (UPCM) 518~ Inputs of UPC~ 518 are connected from the output of UAM 502 and from the output o UPCR 514. UPCM 518 allows ~n initial microcode starting address to be loaded from output of UAM 502 and into UPCR S14 through UPCI 516. Thereafter, Microprogram Count (UPC) may be sequentially incremented by transferring current UPC from output of UPCR 514 and through second input of UPCM 518 to UPCI 516; current UPC may then be incremented by one by UPCI 516 and the resulting next sequential UPC loaded into UPCR 514.
Other operations of USCL 500 i~ generating ~30-.
.

3B2Zl microinstruction addresses for US 116's microcode memories will ke describecl further below.
Flnally, USCL 500 includes internal microcode cantrol logic USCLC, which USCLC receives and decodes control and instruction inputs from Microinstruction Decode (UID) 522, which will be described below, to control oper2tion of VSCL 500.
Referring to the output of USCL 500, 16 bit microcode address outpu~ of UAM 502 is connected to UY
Bus 5~4. UY Bus S24 in turn provides a single bit input to Microprogram Counter Save Register (UPCSR) 52~ and a sixteen bit input to UY Register (UYR~ 528. UYR 528 in turn pro~ides a sixteen bit output to D ~us 108r Sixteen bit UY Bus 524 is connected, through a buffer, to si~teen bit Next Microprogram Counter (NXUPC) Bus 530. NXUPC Bus 530 also receives, t~rou~h a buffer, a sixteen bit input from UIN Bus 504. NXUPC Bus 530 provides sixteen bit address inputs to Rernel Microcode Memor~ (~UM) 532 and Vertical Microcode Memory (W M) 534. NXUPC Bus 530 also provides a fifteen bit input to UPCSR S26.

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Referring to KUM 532 and VUM 534, thirty-two bit microinstruction outputs o~ kernel and vertical microcode memories are provided to Microcode Output ~UC0) Bus 536. Thirty-two bit input of Microinstruction Register ~VIR) S38 is sonnected from UC0 Bus 536, and thirtv-two bit output of UIR 538 is connected to Microinstruction Register (UIR) Bus 540. As will be described further below, kernel and vertical microinstructions are distributed to other portions of CS 101 from UIR Bus 540.
P~eturning to UC0 Bus S36, UC0 Bus 536 provides sixteen bit microinstruction inputs to Microinstruction Save High Register (UIRSHI) 542 and to Microinstruction Save Low Register ~UIRSL0) 544. Sixteen bit microinstruction outputs of UIRSHI 542 and VIRSL0 544 are connected to D Bus 1120 Certain bits of thirty-two bit UCD Bus 546 are provided as data input to VUM 534 through Bufger 535.
Returning to UUR Bus 540, UIR Bus 540 provides an address illpUt to Hori~ontal Microcode Memory (HUM) 548, As described above, and describ`ed in further detail below, HUM 548 stores and provides horizontal extensions . -32-z~

to vertical microcode dealing with random control of CU
104, IPD 114, and D Bus 112, among other functions. UIR
540 also provides certain selected microinstruction bits as inputs to UID 522. UID 522 in turn provides instruction and control outputs to USCL 500 and to SCG
120~
UI~ Bus 540 also provides control inputs to Condition Multiplexer (CONM) 550~ Data input~ to CONM
550 are registered and unregistered conditions occurring at various points throughout CS 101. CONM 550's output is provided as an input to UID 522 and as an input to Condition Save Register (CONSR) 552. An output of UPCSR
526 is connected through a buffer to the output of CONM
550 so that UPCSR 526lS output may be provided to the same inputs of UID 522 and CONSR 552 as the output of CONM 550.
Finally, certain of UIR Bus 540's thirty-two microinstruction bits are provided as one of five inputs to Microinsturction Multiplexer (UIM) 554. UIR Bus 540~s input to UIM 554 is, as will be described further below, provided to implement o~t of sequence jumps to ~9822~

new microinstruction addresses while executing microinstruction sequences~
, Referring to UUM 554, UIM 554's output is connected to UIN Bus 504 and UIM 554's inputs are connected to various sources used, as described below, to select microinstruction sequences to be executed by US 116 and~
therefore, CS 101. As just described, one input of UIM
554 is connected from certain bits of UIR Bus 540~
Another input of UIM 554 is connected from D Bus 112, yet another input is connected from CONSR S52, and another input connected from UPCSR 526. Finally, a last input o UIM 554 is, as will be described in detail below, connected from an output IPD 114.
Referring finally to the upper portion of US 116, therein are represented three registers having outputs connected to D Bus 112. These registers are provided to store certain conditions and flags occurring in CS 101, for s~bsequent trans~er on to D Bus 112. A first register is Error Log Register (~RRLR) 556, a second register is Diagnostic Register (DIAGR) S58, and a third register is ~lag Register (FLAGR) 560.

:

:~1913Z;~

Having described the overall structure of US 116 and certain features of the operatlon thereof, the operation of US 116 will be described in further detail next below.

b. US 116_Qpera~ion 1~ ~
As described above, USCL 500 provides functionality for microprogram control and selection operations.
Input to USCL 500 is through UIM S54 and UIM Bus 504 while USCL 500's output is through N.~UPC Bus 524.
Referring first to USCL 500's input through UIM
554 and UIN Bus 504, UIM 554 is provided with inputs from five sources~ A first input source for UIM 55~ is from D ~us 108 and provides, for example, instruction from IPD 114. A second source is from UIR 3us 540 and is utilized for jumping to nonsequential microinstruction addresses in microcode memory. A third source is from IPD 11~, described below, and is used for certain instruction pre-execution operations and certaln preliminary operations regarding addressing from instruction. A fourth source is a microcode conditional ~9~ Zl input comprised of selected portions of UIM 554's inputs rom UPCSR S26 and UIR ~us 540. Finallyr the fifth source is again a conditional input provided by the output of UPCSR 526.
Referring to NXU~C Bus 530, either UY Bus 524, which i~ USCL 500's direct OUtpUtf or VIM Bus 504 may be selected to drive NXUPC Bus 530 and thereby directly aadress ~UM 532 and VUM 534~
For a microinstruction fetrh, that is, a microinstruction read from microinstruction memory, either RUM 532 or W M 534 is enabledr based upon the state of a Kernel Flag (RFLAG) stored in FLAGR 560 and asserted during-fetch operations. If RFLAG is asserted, fetch is from KUM 532 and, i RFLAG is not asserted, fetch is from VUM 534. RFLAG may be setr or asserted, for example, on system initialization or upon occurrence o~ a microparity error, as described below. RFLAG may be loaded into RFLAGR 560 as a bit output from VIR Bus 540 through operation of an NCU random control output provided ~rom HUM 548.
The 3~-bit outputs of KUM 532 and W M 534 are ORed together on UCO Bus 536 and are loaded into UIR 538 at 9~

the end of each microinstruc~ion read cycle to appear on UIR Bus 540. KUM 532 and W M 534 outputs may each be selectively disabled for this ORing operation. A11 microcode visible operations of C~ 101 are controlled by the 3~ bit microinstruction appea~ing on UIR Bus 540 from UIR 538.
In addition to being loaded into UIR 538, microinstruction outputs apprearing on UCO Bus 536 may be loaded into and saved in UIRSHI 542 and UIRSLO 544.
Outputs of UIRS~I 542 and UIRSLO 544 may then be transferred onto D Bus 112 to allow reading of kernel and vertical microcode memories.
As will be described further below, all microinstructions appearing at UIR 538 output on VIR Bus 540 are checked for error by operation of Microparity Checker ~UPARC) 562, which is connected from UIR Bus ~40.
As described above, each microinstruction autput appearing,on UIR Bus 540 from UIR 538 contains 32 bits of microcode control information. Although there is certain overlap of functions controlled by various microinstruction fields, certain portions of each ~lg8Z~

microinstruction may be generally described as controlling certain CS 101 unctions. For example, in general UIR Bus 540 bits 0 and 3 through 30 are provided to PU 106 to control all PU 106 microcode visible functions. UIR Bus 540 bits 7 through 13 may be used to select a detected and registered condition occurring in CS 101 to be tested during a current microinstruction cycle. For this purpose, bits 7 through 13 from VIR Bus 540 are provided as control inputs to CONM 550~ which in turn selects conditions to be tested. Other microcode controlled ~unctions will be described further in the following descriptions.
Having described the general operation of US 116~
certain features of US 116 operation will be described in further detail next below9 ~. ~e~
A microinstruction cycle is defined, for purposes of the following descriptions, as the time between consecutive CS 101 clock cycles and is the period of time during which single microinstruction functions are executed. In general, during each ~icroinstruction cycle the microinstruction is fetched ~rom either KUM

-3~-~9~32;~

532 or VUM 534 and a previously fetched microinstruction store2 in UIR 538 is executed.
The following presents a typical sequence of steps occurring in US 116 during consecutive microinstruction cycles:
1) USCL 500 has placed on UY Bus 524 a microinstruction memory address speci~ied by decode of the certain bits (0-6) currently appearing on UIR Bus 540 and the output of CONM 550~ Information appearing on CONM 550's output from CONM 550 and UPCSR 526, may include the contents of UPCSR 526, information indicating the current top of USTAC 510~ the contents of UAR 506, or OD input appearing on UIN Bus 504.
2) The microcode address appearing on UY Bus 524 is incremented by UPCI 516 and the incremented microprogram count loaded into UPCR 514. In all microsequencer operations, except certain operations described below, the microcode address appearing on UY
Bus 5~4 is transferred onto NXUPC Bus 530 to address either K~M 532 or W M 534. Therefore, UPCSR 526 will contain the ~ddress of the curr~ently executing microinstruction plus one.

. .

z~

3) A new microinstruction addressed by theaddress presently appearing on NXU~C 530 is loaded into UIR 538.

4) The address presently appearing on NXUPC
530 is loaded into and saved in UPCSR 526, so that UPCSR
526 always contains the address of the currently executing microinstruction except on a TRAP condition as described below.

5) The output of CON~ 550 from the microcycle just ending is loaded into CONSR 552.

6) US 116's pointer to the top of the microstack residing ~ n USTACR 510 is changed i the current US 116 operation specified in the cycle just ending has affected US 116's microstack.
~ 7) The contents o~ UA~ 526, whose operation is described further in following descriptions, is changed if the US 116 operations specified in the microc~cle just ending has affected UAR 506, or if other operations, described below, occurred during the same microcycle.

:

2~

~ aving described a typical microinstruction cycle sequence, US 116 operation for TRAPS will be described next below.
3. Trap ppe~ Q~
A TRAP condition occurs during execution of microcode when an exceptional condition occurs and it i8 desirable to stop the execution of a misroinstruction in pro~ress~ service the exceptional condition, and then ~es~me execution of microcode from the suspended microinstruction. A TRAP process must save sufficient machine state so that the stopped microinstruction ~ay be restarted. For those TRAPs that can be serviced entirely by microcoder the two pieces of state information that must be saved in US 116's microstack residing in USTACR 510 are, . (1) address of the stopped microinstruction;
and (2) the output of CONM .5S0 from the stopped microinstruction; that is, all conditions currently present.
CONI~ 550 output must be saved because the inputs to CONM S50 are registered, or stored, state that may change- during servicing of a TRAP condition and the microinstruction which was interrupted must recover the correct conditions selected upon resuming.
A signal, TRAP is asserted by IPD 114 During execution of any microinstruction which is to be sus~endedO This event causes the following to occur:
(1) Clock to all CS 101 registers under explicit microcode control is stopped so that these registers are not loaded with altered information during servicing o the TRAP condition;
(2) USCL 500's control input from UID 522 is forced into a state to force USCL 500 to do a jump operation to a TRAP handling microinstruction sequence;
and (3) Control input to UIM 554 is forced to the appropriate state to select UIM 554's input to be that provided from IPD 114.
The address of a TRAP handling microinstruction sequence ls provided to UIM 554l~ input ~rom IPD 114 by either CU 104 or PU 106, dependlng upon whether CU 104 or PU 106 is,the source of the ~RAP signal~ If both CU
104 and PU 106 have provided TRAP signals, then a -42~

' ~ ~

~3~

priority mechanism will determine the TRAP handling microinstruction sequence to be selected~ A TR~P
handling address is the starting address of a TRAP
handling microinstruction sequence and is placed dir~ctly upon NXUPC Bus 530 from UIN 504 through BuEfer 50~
At the end of a microcycle in which a TRAP
condition occurs, the following occurs:
(1) UIR 538 is loaded with the microinstruction beginning the TRAP handliny microinstruction sequence;
(2) UPCSR 526 is nQ~ loaded with the microinstruction address appearing on NXUPC 3us 530;
UPCSR 526 will therefore contain the address o:E the trapped, that is, interrupted, microinstruction during the first microinstruction of the TRAP handling microinstruction sequence;
(3) The output oE CONM 550 is loaded into CONSR 552.
At conclusion of handling of the TRAP condition the original state of execution of the interruptecl microinstruction sequence is restored, us.ing lnormatlon retained in UPCSR 526 and CONSR 552 and through the state save/restore mechanism described next below.
4. E~ c ~a~e Save/Restor~ Mecha~i~m US 116's Basic State Save/Restore Mechanism is USCL
500lS microstack residing in USTACX 510~
During the irst microinstruction cycle of a trap handling microinstruction sequence, signal TRAP is not asserted and any the information stored in UPSCR 526 may change state. The first microinstruction cycle of a TRAP handling microinstruction sequence must therefore do a state save/restore operation to save current state of US 116 and USTACR 510. During this operation, the contents o~ CONSR 552, that is, previo~s conditional states of execution, and the contents of UPSCR 526, that is, the address of interrupted microi~struction, are transferred through UIM 554 and onto UIN Bus 504. This state information is then transferred through USM 512 and onto the top of microstack residing in USTACX SlOr thereby saviny the conditions and address cf the interrupted microinstruction.
If a T~AP may be totally ~andled by a microcode, no further microsequencer state save is required. Resuming 2~21~

execution of the stopped mlcroinstruction is accomplished by leaving the saved condition state and microinstruction address at the top of microstack residing in USTACR 510 and performing a resume operation which "pops" the itop entry in USTACK 510~ A "pop~
ojperation fetches the stopped microinstruetion while reading the saved eondition state information from top of microstack and transferring this information from top of microstack through UAM 502 and into UPCSR 526~ Saved condition state is a single bit of information from UPCSR 526 and which represents the saved output o~ CO~M
550. After be;ng transferred into UPCSR 526, and during re-execution of the interrupted microinstruction, the saved eondition state inf ormation ts transferred onto COMM 550's output throuyh Buffer 527, t;~ereby providing saved condition state information l:o CONSR 552 and UID
522. Saved address of the interrupted microinstruction is concurrently transferred through UAM 502, UPCM 51a and UPCR 516 t~ UPCR 514. At this point execution of the interrupted microinstruction may be resumed.
Having described US 116's bas:ic state save/restore meehanism, US 116's state save/resi~ore meehanism for , -.

conditions requiring assistance from macrocode9 that is, from instruction stored in MEM 102, will be described next ~elow.

When a trap condition occurs requiring macroco~e assistance for handling, the trc~p handler must save all mierosequencer state and other ~ 106 state in MEM ].02 rather than in USTACK 510's micr.ostack. State saved in such conditions includes the current contents of USTAC~
510's microstack including the address of the eurrently executing microinstructions and current state condition information pertaining to the interrupted ~icroinstruetion, and the curre;nt contents of UAR 506 As in the case described above, eurrent condition from CONSR 552 and UPCSR 526 are first pushed onto USTACR
510. Full state save then saves the eontents of USTACK
510 and MAR 5~6 in MEM 102~
Current state eonditions and current microlnstruction address are read from CONSR 552 and UPCSR 526, respectively, and through UIM 55~ to UIN Buss ~46-504O This information, together with information from U~R 506 and the contents of. USTACK 510's microstack, are read through UAM 502 and UY Bus 524 into UYR 528. State inormation so read from US 116 may then be transferxed through D Bus 112 to MEM lt)2, or to scratch pad memory in PU lQ6, described in a following description of PU
106.
State restore is accomplished by reading US 116's saved state inor~ation from MEM 102, or scratch pad rnemory in PU 106, to D Bus 11~. This in~ormation i~
~hen trans~erred into UIM 554ls input from D Bus 112, and onto UIN Bus 504~ ~he saved contents of U~R 506 and USTAC~ 510 may then be transferred through UARM 508 to UAR 506 or through USM 512 to USTACR 510. Once completed, the saved condition state and interrupted microinst-ruction address will be the top entry in USTACX
510 and the interrupted microinstruction may be resumed as described in section 3 above.
6. ~ D~_~Dd~ LII~ C~ 9C~ QL~
As previously described, CS 101 implements vertical microcode in a writable control` store, that is, VUM 534.
A means, described next below, is provided to write 2~:~

vertical microcode from external memory to MEM 102 and from MEM 102 to VUM 534. This means also allows the contents of VUM 534 and and XUM 532 read from VUM 534 or RUM 532 to D Bus 112, for example, to verify microcode residing in W M 534 or KUM 532 or to be read as a source of literal data. This mechanism operates under microcode control and the functions described may be performed under control of microcode provided from either R~M 532 or VUM 534.
During a microcode write to VUM 534~ or a microcode read from VUM 534 or K~-M 532, USCL 500 is forced to perform a condîtional microinstruction jump to the appropriate microinstruction sequence, by means o a microcode input to UID 522 and a corresponding instruction to USCLC 520. Microcode memory read and write addresses are provided to NXUPC Bus 530 from UAR
506 through U~ 502 and UY Bus 524. UAR 506, in turn, is provided with read and write addresses from D Bus 112 through UIM 554 and UIM Bus 504.
In microcode write operations to VUM 5~4, microinstruction words are pro~ided on D Bus 112 and are transferred through UCD Bus 546 to VUM 534's data input -~8-~g~

through Buffer 5350 In m.icrocode read operations from either XUM 532 or VUM 534, microinstruction words are read rom ~nM S32 or VUM 534 onto UCo Bus 536 and into UIRS~I 542 and UIRSLO 5440 Microinstruction words may then be transferred ~rom UIRS~I 542 and UIRSLO 544 to ~CD Bus 546 and to D Bus 112.

7. Microcode Parity Erro:r~
Each microinstruction provided by gUM 532 or by VUM
534 is a 32 bit word comprising 31 bits of microcode inormation, plus 1 parity bit which is set to preserve odd parity. Parity of each microinstruction appearing in UIR 538 is checked by UPARC 562 after each fetch of a microinstruction from KUM 532 or VUL~ 534. If a parity error occurs, UPARC 562 will initiat:e a microparity error trap that prevents execution cf t5he microinstruction in error and transfers control to Kernel microcodè in KUM 532 for error handling.

8. L~g~ b,~ u~ lh~lldaLi~
In the above descriptions, IPD 114 was described as the source of instructions to be executed by means o~
corresponding microinstr,uction'sequences provided by US
116. An instructlon boundary is crossed when the ~ .

microinstruction sequence corresponding to a first instruction is ended, for example, by completin~
execution o~ the sequence or because o a trap condition, and execution of a second instruction i5 ir.itiated. Microinstruction sequences provided by US
116 provide a mechanism for initiating the execution of new instructions.
~ nd of execution of a current instruction may be indicated by the ap~earance in UIR 538 of a particular microinstruction in the corresponding microinstruction seqùence. If such an end of execution microinstruction occurs, UID 522 and USCLC 520 provide an instruction to USCL 500 to jump to a state for receiving a next instruction At this time, UIN 554 is instructed to accept as input to UIN Bus 504 UIM 554's input from IPD
114. IPD 114 will then provide, through U~M 554 and UIM
Bus 504, the starting address in microinstruction memory of the next instruction to be executed.
If an interrupt is pending, or if the next instruction has not yet been fetched, or if any one o several other conditions occurs, a next instruction may not appear ox be available. IP~ 114 will then provide /

~82Z~

to UIM 554 the address in, microinstructicn memory of an appropriate routine to handle the existing condition.

9. So~,t ConsoLe As previo~sly described, CU 101 incorporates a "soft consolen9 ~hat is, operator console type commands may be entered through a terminal rather than through front panel switches. US llS will detect the initiatlon of such a conso~e command entry by means of a non maskable interrupt initiated by an initial console command. Upon such occurrence, an address will be forced at UI~ 554's input from IPD 114 which, provided to USCL 500 and thus to NXUPC Bus 530, is the initial address in KUM 532 of console microcode sequences stored therein.
As previously descri~ed, at system initiation US
11~ micro ode memory contains only kernel microcode. In a present embodiment of the present invention, kernel microcode includes at least a portion of the NOVA
instruction set microcode and is responsive to single character commands provided from a terminal through SIO
120. Vertical microcode include microcode for the full NOVA, ECLIPSE and MV/8000 instruction sets and i'3 1~9~32~

responsive to multiple character commands provided from a terminal through SIO 120. CS 101 thereby provides a limited "raft" console, that is, from a terminalf at system start-up, and full console functions after vertical microcode has been loaded.
Having described the structure and operation of US
116, the structure and operation of IPD ~14 will be described next below.

3. Instruc~ion P~f~çh_~n~ Decod9~ 5~J~ o~L~ _5 ~L
As indicated in Fig. 5 and SA, and as previously described, IPD 114 is connected between memory data (MDA) Bus 110 and D Bus 112 with an output to an input of UIM 554 in US 116. IPD 114 operates as aan up to four instruction deep instruction prefetch, and as an initial instruction decoder. Some typical formats of instructions used in CS 101 have been previously described with reference to Fig. 2.
a. ~5~ss_l0~ LEL~
Referring to IPD 114, 16 b~it Prefetch Register A
(P~A) 564 and 16 bit Prefetch Register B ~PRB) 566 ha~e ~8~

.inputs connected from MDA ~us 110. 16 bit outputs of PRA 564 and PRB 566 are connected to 16 bit Prefetch Register (PR) Bus 568.
PR Bus 568 is connected to 16 bit input of Displacement ~igh Latch (DISPHIL) 570 and to 16 bit input of Displacement Low Latch (DISPLOL) 572. 16 bit outputs of DISP~Ih 570 and DISPLOL 572 are connected to first and second 16 bit inputs of IPD Ou~put Multiplexer (IP~OM) 574.
Next Instruction Regis~er (NIR) 574 has a 16 bit input connected from PR Bus 568 and 16 bit output connected to 16 bit input of Instruction Register (IR) 578. I~ 578 in turn has a 16 bit output connected to a third input of IPDOM 574.
Finally, PR Bus 568 i5 connected to 16 bit input of Single Level Instruction Cracker (SLIC) 580. 9 bit output of SLIC 580 is connected to the input of 9 bit Single Level Instruction Cracker Register (Sl.ICR~ 582, and 9 bit output of SLICR 582 is connected to input of Macroinstruction Decode Memory (MIDM) 584.
A 2irst output of MIDM 584 is connected to the input of Decoded Instruction Register (DIR) 586.

first output of DIR 586 is connected to a fourth input of IP~OM 574 and in part controls IPDOM ~74 Second outputs of DIR 586 are provided to other portions of CS
101, as will be described in following descriptions~
A second output of MIDM 584 is connected to a first input of Microinstruction Aadress Multiplexer (UADRM) 588. A second input of ~ADRM 588 is connected from Trap Addresses (TA) 590.
~ lnally, IPD 114ls first output, from output of IP~OM 574, is connected to D Bus 112 while IPD 114's second output, from output of U~DRM 588, is connected to the previously described input of UIM 554 in US 116.
Having described the overall structure of IPD 114, the operation of IPD 114 will be described next below.
20 l~$L~ QQQL~LQn As has been previously described, a typical instruction of CS 101 may contain 32 bits, including. 16 bits o~ instruction information (opcode .ield) and 15 or 16 bits of address displacement in~ormation tdisplacernent field). Certain instructions, however, will nave a total length of 16 bits or will have a double word displacement field of 32 bits, for a total ;

z~

o 48 bits. As also previously described, and as will be further described in fo]lowing descriptions, all writes to and reads from MEM 102 by CS 101 are of double wordst tha~ is, of two 16 bit words at a time. Upon each read from MEM 102, therefore, PRA 564 and PRB 566 will receive a 32 bit double word from MDA Bus 110, with one 16 bit ~ord being received in PRA 564 and the other 16 bit word belng received in PR3 556. A Pre~etch Register 5PR) pointer generated by U5 116 indicates, at any time, which o~ PRA 564 or PRB 566 presently contains or will contain a 16 bit instruction inormation o a current instruction field or which contains or will contain displacement f leld inf ormation.
Instruction displacement field information may be transferred .rom either P~A 564 or PRB 566 PR Bus 568 and toeither of DISHIL 570 or DISPLOL 572. Diplacement field information may then be transerred from DISP~IL
570 or DISPLOL 572 and through IPDOM 574 to D Bus 112 for use by PU 106 in addressing data referenced by an instruction. Two displace field latches, that iSr DISP~IL 570 and DISPLOL 572, are provided to enable displace~nent field information to be transferred to PU

~98~

106 in a single cycle for 15, 16 or 32 bit displacement fields Instruction information fields may be txansferred from either P~A 564 or PRB 566 to PR Bus 568 and ~IR 575 and in turn to IR 578. From IR 578, instruction in~ormation fields may be transferred, simultaneously with the corresponding decoded output of SLIC 580 to SLICR 58~, through IPDOM 574 to D Bus 112 and thexeby to US 115 through UIM 5S4 to select corresponding microinstxuction sequences to be executed by CS 101.
NIR 576 and IR 578, together with PRA 564 and PRB 566, provide an up to four instruction deep prefetch mechanism, allowing CU 104 to fetch instructions in advance of the instruction currently beins executed.
Certain of CS lOl's instructions cannot be executed immediately as received from MEM 102~ Fox example, instructions will frequently xequixe additional processing of the instructions addressing information before the data referenced by the instruction can be fetched from MEM 102. Additionally, due to the variety of instruction formats used b~ CS 101, CS 101 and US
116, in particular, must perform certain preliminary . .

2~

operations in order to properly interpret and respond to instructions~
The instruction cracking and decoding circuitry provided by SLIC 580 and MIDM 584 and related logic provides a mechanism for interpreting instructions.
First, SLIC 580 examines the 16 bit instruction information field of each instruction and extracts therefrom 9 bits~ depending upon the instruction format, defining the operation to be performed. A first output is a g bit predecode address which is provided as an input to MIDM 584, described below. A second, ~ bit, output defines the index maae for the instructions being decoded and other output may define the înstruction class. The in~ormation so extracted includes i~formation relating ~o data addressing, such as data width~ displacement type and instruction width.
~ IDM 584 is a read-only-memor-~ addressed by the 9 bit output of SLIC 580 and pxoviding appropriate control outputs~ MIDM 584's first output to DIR 586 provides information relating to data width, displacement type and data length. MIDM 584's second output, to UADRM 588 provides to US 116 the starting microaddress of microinstruction sequences to be executed, as previously described in the description of U5 116~
UADRM 586's second input, from TA 590, provides in~ormation to UIM 554, and thus to US 116, regarding the starting microaddress of microlnstruction sequences to handle trap conditions occuring in CS 101, as previously described.
~ a~ing described the structure and operation of IPD
114, the structure and operation of MC 118 will be described next below.
3. ~ ;.
MC 118, as previously deccribed, performs in~erface functions between CU 101 and MEM 102. MC 118 is a ~look aside~ interface device, that is, is connected in parallel from MAD Bus 108 and MDA Bus 110, rather than being connected in series in these buses between CS 101 and MEM 102. MC 118 operates, however, as if connected in series in MAD Bus 108 and MDA Bus 110 between CS 101 and MEM 102. MC 118 allows CS 101 and MEM 102 to share the same address and data signals on MAD Bus 108 and MDA
BU5 110 while, at the same ti~e, allowing CS 101 and MEM
102 to have different interface protocols.

~8~
In addi-tion to ~erforming transla-tion be-tween CS
lOl~s memory bus protocol and MEM 102's memor~ bus protocolO
MC 118 provides MEM 102 refresh and "sniffing". Sniffing, as described in US Patent 4,380,812, issued April 19, 1983, is a mechanism and method for scanning MEM 102 locations being refreshed, detecting errors therein, and correcting such errors. In addition, MC 118 performs memory error logging. Finally, as previously described with reference to CS lOl's addressing mech~nisms and in particular CS lOl's demand paging mechanism, MC 101 monitors and logs, or records, referenced and modified pages residing in MEM 102 a. Structure of MC 118 Referring to Fig. 5, MC 118 includes a Memory Control Sequencer (MCS) 592, which provides timing and control for all memory related operations, in particular those of MC 118. MCS 592 has a clock input from SCG 120, a refresh timing input from Refresh Timer (REFT) 594, and an error input from MC 118's ERCC logic, described below. In addition to other control outputs, cr /J ~

r EL~lL9~3~ ff~

MCS 592 provides out.puts to Re~resh Address Counter Buffer (RACB) 596 and to Referenced/Modified Bits Logic (REFMOD) 598.
In addition to a timing output to MCS 592~ REFT 594 provides a timing output to Refresh Address Counter (RAC~ 501. RAC 501 in turn provides refresh address outputs to RACB 5g6, and RACB 596 in turn provides refresh address outputs to ~AD Bus 108 under control of the previously described control input from MCS 59~
REFMOD 598, as previously described, monitors and logs referenced and modiied pages in MEM 10~ as part o CS lOi's demand paging system by stori~g information bits pertaining to referenced and modified pages residing in MEM 1020 In addition to a control input from MCS 592, R~F~O~ 598 includes an in~ut from M~D Bus 108 and a bidirectional connection to MDA Bus 110.
Finally~ MC 118 incorporates Error Chec~ing and Corxection tERCC) lo~ic which includes a f if st level ERCCER (FLE) 503 and a second level ERCCER (SLE) 505.
FLE 503 and SLE 505 are implemented with Advanced Microdevices~A~ 2960s connected in a 32 bit con~iguration.

. ..

I

~i8;~2~

MC 118's E~CC logic is provided with an internal data bus, Check Data (CDATA) 507,which allows data to be transferred from M~A Bus 110 to MC 118 ERCC logic, manipulated, and transferred back onto MDA Bus 11OD
Data is transferred from M~A Bus 110 to CDATA Bus 507 through ERCC Data.Input Buffer (EDIB) 509, and from CDATA Bus 507 to MDA Bus 110 t~hrough ERCC Data Output Buffer (E~OB) 511~
FLE 503 and SLE 505 each have a 16 bit bidirectional data inputJoutput connection to C~ATA Bus 507 for receiving data from and transferring data to CDATA ~us 5~7O FLE 5~3 receives 7 bi~s of check bi~
(ERCC) i~formation, from MDA Bus 110 through FLE 503is check bit (CB~ input connected from MDA Bus 110 and provides a check bit output to check bit input of SLE
505's CB input. SLE 505 provides 7 check bits of ERCC
information to ~A Bus 110 through ERCC Check bit Output Buffer (ECBOB) 513. SLE 505 also provides error outputs, as previously described, to MCS 592 and to ERRLX 556 in US 116.

2~
Having described the structure and certain features of the opera-tion of MC 118, certain features of MC 118 will be described further next below.
2. Operation of MC 118 The operation of MEM :L02, and MEM 102's interface to MAD Bus 108 and MDA Bus 110 are described in Canadian Patent Application No. 441,238, filed October 26, 1983. MEM
102 and MEM 102's interface to CS 101 will thereby not be described further in detail herein. The following description will pertain to CS 101 and CS lOl's interfaces to MAD Bus 108 and MDA Bus 110 and CS 101's functionality with respect to memory operations.
As described above, CS 101 and MEM 102, will have differing interface protocols but share the address and data signals appearing on MAD Bus 108 and MDA Bus 110.
Translation between CS 101 and ~EM 102 interface protocols involves the control signals exchanged therebetween and manipulation of check, or ERCC, bits appearing on MDA Bus 110. It should be noted that CS 101 may provide 30 bits of address, since, as previously cr/~,~
. .

1~9~32~

described, CS 101 performs reads from and writes to MEP
102 double words only~
The least significant bit of CS lOl's addresses are exchanged to be the least significant bit of the addresses received by MEM 1020 This implies that consecutive double words written or read by CS 101 never appear in consecutive locations in MEM 102, allowing faster double word instruction retches when MEM 102 interleave operation is considered.
MC 118 operations may be divided into two broad classes, read operations and write operations. Read and write operations diffe~ in that read operations ~ay be pipelined, wherèas write operation may not, due to the operation of the MEM 102. That is, address and control signals for a next read operation may be sent to MEM 10~
while reading and checking the data read from MEM 102 in a present read opefation. ~11 data control and add_ess control functions for a present write operation must, however, be fully completed before initiating a subsequent write operation.
~ CS 592 may be reaarded as perCorming two mutually dependent operations with regard to memory read and z~

write operations, address control and data control.
Address control monitors operation of MEM 102 through control signals provided rom MEM 102, initlates addressing operations, determines acceptance of addresses by MEM 102, and generates control signals to initiate operation of MCS 592's data control logic on information transfers. MCS 532's address control also mo~itors reresh operations, to allo~ sniffing operations MCS 592's data control logic generates all data control signals for MEM 102's CS lOl's interfaces to MAD
Bus 108 and MDA 110. MCS 592's data control logic also generates all control signals ~or MC 118 ERCC functions and monitors the ERCC outputs of MC 118's E~CC loglc~
As de~cribed above, MC 118 performs refresh operations upon in~ormation stored in MEM 102. Refresh is performed through ncycle stealing" operations, wherein MC 118's reresh control circuitry takes control of MAD 108 and MDA Bus 110 at periodic intervals to refresh successive portions of MEM 102's address space.
REFT 594 generates a ref~esh request signal at periodic intervals and, at time o~ a refresh cycle, increments ~L98Z~

RAC 501 to generate successive refresh addresses. RAC
501 generates 21 bit addresses specifying double words to be read and checked for errors.
A sniff operation, that is examining information stored in MEM 102 in storage locations currently being refreshed for error checking and correction, begins by requesting a refresh cycle. During refresh cycle, MC
lla takes control of ~D Bus lOS and ~DA Bus 110 and asserts a refresh address from RAC 501 through RACB 596 to MAD Bus 108~ Inormation read fxom corresponding locations in ME~ 102 is checked for errors, ~hile C~ 101 is allowed to continue making memory references. If a correctible error is found, a refresh write back operation is initiated. A refresh write back operation is performed in the same manner as the original refresh except that the information is corrected and written back.
When RAC 501 generates an address greater than the present address space of MEM 102, that address will address nonexistant memory. When this event occurs, MEM
102 will not.generate a signal indicating that the refresh address has been acceptedO This event causes ~l~9~2~

RAC 501 to be reset to zero, allowing xefresh to start over at the beginning of MEM 102 address space~ A
refresh and sniff in MEM 102's address zero is performed immediately upon this occurrence.
As described above, ERCC and error logging is accomplished through MC 118's ERCC logicf including FLE
503 and SLE S0S. Data inputs to FLE 503 and SLE 505 from MDA Bus 110, and data outputs from FLE 503 and SLE
505 to MDA Bus 110 are isolated from MDA Bus 110 through the bidirectlonal buffer comprising EDIB 509 and EBOB
511. As described above, CDATA Bus 507 operates as the data portion of MDA Bus 110, ~ut is isolated from MDA
Bus 110 by thls bidirectional buffer. Check bits, that is ERCC bi.ts appearing on MDA Bus 110, are, however, provided directl-y to FLE 503's check bit (CB) input from MDA Bus 110. Check bit output SC of MC 118's ERCC logic is provided from check bit output SC of SLE.505 to MDA
Bus 110 through ECBOB 513. MGS S92 provides individual and separate controls of all data and check bit transfers through EDIB 509, E~OB 511, FLE 503, Sl,E 505, and ECBOB 513~ `

~.~9~22~

ERCC upon information read from MEM 102 on to MDA
Bus 110 is accomplished by reading data bits from MDA
Bus 110 and through EDIB 509 to CDATA Bus 5Q7, and thus into FLE 503 and SLE 505, while check bits are read directly into FLE 503. It should be noted that FLE 503 receives the 16 least significant bits of data while SLE
505 receives the mos~ significant 16 bits o~ data~ FLE
503 utilizes the check bit inputs from M~A Bus 110 and the 16 least significant data bits received from CDATA
Bus ~07 to generate an appropriate check bit output to SLE 505 for those check and information bits. SLE 505 in turn utilizes the most significant 16 bits of data from CDATA 507 and the check bit input from FLE 503 to generate a final check bit output~
ERCC upon information read from MEM 102 is performed at the same time that the information is passed on to the requestor, in most cases PU 106. That is, ERCC is performed in parallel with the read operation.
I~ an ERCC error is detected, a signal halting memory operations is asserted and a correction cycle initiated.
During correction cycle, error syndrome bits indicating 82~1 the error which has occurred are pro~ided at output of SLE 505 and are driven onto MDA Bus 110 through ECBOB
513. From MDA Bus 110, error syndrome bits are transferred into FLE 503, which provides appropriate outputs to the check bit input of SLE 505. FLE 503 and SLE 505 then generate corrected data onto CDATA Bus 507.
The corrected data is then transferred through EDOB511 to MDA Bus 110 and therehy to the requester. Because comparitively few read operations will result in correction cycles, the parallel operatlon o~ MC 118's ERCC Logic, wherein inormation is p~ssed on to the requester while ERCC's performed, will result in faster avera~e read operations than will a series ERCC
operation.
MC 118's E~CC Logic also generates ERC~ bits during write operations to MEM 102. As previously described, all write operationst as are all read operations, are of double words. Data appearing on MDA Bus 110 to be written into MEM 102 is accepted on to CDATA Bus 507 through EDIB 509. FLE 503 and SLE 505 accept this data as inputs and generat~ corresponding check bits from the output af SLE 505. These write check bits are then .

:

r ~JW~

trans,errea onto the check bit portiCrl of MDA Bus 110 through ECBOB 5]3, and the data and correspcnding check bits written into MEM 1O2J
CS 101 may also perform partial write operatiOns~
that is, writes of single words of single bytes.
As described above, all read and write operations of CS 101 from and to MEM 102 are of double words, that is, of two sixteen bit words at a time. As has also been previously describedr CS 101 is also capable of generating read and ~rite addresses referencing single words (16 bits) and single bytes (8 bits). The operation of CS 101, and in particular MC 118, in performing single word and byte read an~ write operations will be described next below.
Referring to Eig 7, a block diagram o certain portions or CU 104 and PU 106 is shown, in par~icular CU
104's ERCC circuitry, including FLE 503 and SLE 505 and CDATA Bus 507, and PU 106's MDS 132, in particular MDR
602. In Fig. 7, FLE 503, SLE 505, EDIB 509, EDOB 511, MDR 602, and MDRB 603 have been redrawn to illustrate the operatio~l of these elements in yet greater detail.
In particular, MDR 602 and MDRB 603 o~ MDS 132 are -69~

l~g~,2i indicated as operating, respectively, as four in~ependently controllable 8 bit registers and buffers, C, D, E, and F, rather than as a single 32 bit register and buffer. In FLE 503 and SLE 505, input latches I
have been represented as each comprising two independently controllable 8 bit latches Aand B, while output latches O have been similarly represented as each-comprising two independently controllable 8 bit latches, A and B. Similarly, EDIB 509 is represented as comprising four independently controllable 8 bit input bu~fers, while EDIB 511 is represented as comprising four independently controllable 8 bit output bufers.
For clarity of presentation of the following descriptionj CDATA Bus 507 is shown as divided in two parts, one part corresponding to FLE 503 while the second part is associated with SLE 505. This division is made ror illustrative purposes only and the two halves of CDATA Bus 507 shown in Fig. 7 are in fact a single bus. MDA Bus 110 is represented as being comprised of a 32 bit data bus and a 7 ~it check bit bus ~or ERCC bits.

~91!3~zi~

In as much as CS 101 performs only double word reads from and writes to MEM 102, a write of a single word or byte to MEM 102 is performed as a read, modify and write of a double word. Tthe double word containing the address location of the single word or byte to be written into MEM 102 is read from MEM 102. The double word read from ~lEM 102 is effectively modified by ha~ing the single word or byte written into the appropriate location in the double word, and the double word is then written back into MEM 102. The following will describe the operation of CS 101 in writing a single by.2 (8 bits~ into MEM 102. A single word write, that is, of 16 bits, or two bytes, is performed in the same manner except that two bytes rather than one are written into the appropriate location in the double word.
Referring to Fig. 7, at start of a single byte write operation a doub~e word is read from MEM 102 on MDA Bus 110. Thirty-two data bits appear upon the data portions of MDA Bus 110, while seven check bits appear on the check bit portion thereo~. The four 8 bit bytes comprising the 32 bit double word are transferred through the corresponding portions of EDIB 509 to CDAT~

Bus 507 and into the corresponding A and B portions of FLE 503lS and SLE 505~s input (I) latches. The check bits are transferred directly into FLE 503's check bit (CB) input. The 32 bit word received frorn MEM 102 and to FLE 503's and SLE 505's I latches are checked for errors, corrected if necessary, and transferred in~o Fl.
503's and SLE 505's four 8 bit output (O) latches A and B~
At the same time, the byte to be written into MEM
102 is loaded into one of MDR 602's four single byte (8 bit) latches, C, D/ E, and F, from D Bus 112 The byte to be written into MEM 102 will appear in the one of MDR
602's latches corresponding to the location that the byte is to be written into in the double word initially read from MEM 102O ~he byte to be wr.tten is then transferred from the corresponding byte register of ~IRD
602 and through the corresponding portion of MDRB 603 to the data portion of MDA Bus 110 and therefrom into the correspondiRg single byte input latch of FLE 503 or SLE 505. For example, a byte appearing in MDR 602 byte register E oould correspondingl~ be transferred into FLE

.

z~

503's I latch A, while a byte appearing in MDR 602's latch D would appear in SL.E 505's i latch B.
At this time, three o:E FLE 503's and S~E 505's input latche~ contain corresponding bytes from the double word originally read from MEM 102 while one of ~LE 50~'s or SLE 505's input latches contains the byte to be written into MEM 102. FLE 503's and SLE 505's input latches thereby contain the modified double word to be written back into MEM 102, tha!: is, the double word containing the byte to ~e written into MEM 102.
FLE 503 and SLE 505 will then generate the new seven check bits for the modified double word. The check bits in modified double word are then transferred to FLE
503's and SLE 505's output latches and on to CDATA Bus 507 and ~.DA Bus 110 to be ~ritten inlo MEM 102, thereby completing the write of 2 single byte into MEM 102. As described above, a write of a single word, that is of two bytes at a time, is performed in the same manner as a single byte write operation except that two bytes are received from MDR 602 and used to generate the modified double word.~

~9~

Finally, as previously described, MC 118's REFMOD
598 operates as part of CS lOl's demand paging system by monitoring and storing information relating to referenced and modified pages residing in MEM 102.
REFMOD ~8 may store information pertaining to up to, for example, 8 megabytes of information storage in MEM
102.
REFMOD 598 stores two different types of information pertaining to each page in MEM 1020 First, REFMOD 598 stores, for each page residing in MEM 102, a bit indicating whether the page has been referenced by CS 101, for example, in executing a user's program.
Secondly, REFMOD 598 stores, again for each page in MEM
102, a bit indicating whether CS 101 has modified, that is, performed a write operation to, that page in MEM
102. Referenced in~ormation bits are updated upon occurrence oi each read or write operation to MEM 102, while modi~ied bit information is updated during each write operation. Updating of reierenced and modified information in REFMOD 598 is periormed under control of CU 104 random control outputs from HUM 548 and US 116 as previously described.

~ C~

~ aving described the structure and operation of CU
la4, the structure and operation of PU 106 will be corresponding described next belsw.
B. PRQCESSOR U~IT (P~l lQh_~B~,TURE_L~1D
O~E~TIQ~ n~ ~A~
Referring to Fig. 6, a detailed block diagram of PU
106 is shown. As previously descri~ed, PU 106 operates under microinstruction control of CU 104 to e:~ecute user's programs. That is, ~V 106 performs all data manipulation and calculation operations, addressing operations, and informatlon transfels beiween CS 101 and external storage devices.
~ neral Structure an~ Op~ration of PV 106 As pre~iously described and as shown in Fig. 6, PU
106 includes CPU Processor (CPUP) 122, Nibble Shifter (NIBS) 126, Stratch Pad and Address Translation Unit (SPAD) 128, Memory Addressing (MAD) 130, Memory Data Store (MDS) 132, Serial Input/Output (5IO) 134, and Data/BMC Input/Output (DBIO) 136.
Referring first to C?UP 122, CPUP is a 32 bit processor comprised ~f 8 four ~lt Advanced ~icro Devices (AMD) 2901C microprocesscrs connected in parallel.

i CPUP 1~2 performs all CS 101 arithmetic operations under microcode control of CU 104. CPUP 122 includes a random access memory (~AM~, a shift register/buffer, a register file, an arithmetic and logic unit (ALU), and other registers~ shift registers, and multiplexers as needed to perform general purpose data manipulation operations, including arithmetlc operationsl CPUP 122 further includes internal ~icrocode control, which receives instructlon inputs from US 116. CPUP 122 receiYes two inputs, ~EG and BREG from US 115 microcode control output which selects, for certain operations, source and destination registers in CPUP 122's register file. As indicated in Fig. 6, CPUP 122 has a 32 bit data input connected from D Bus 112 and a 32 bit output connected to Y Bus 124. The circuitry comprising C~UP
122 are commercially available components well known to those of ordinary skill in the art, and will not be described further except as required for a more thorough understanding of CS 101 during t~e following detailed descriptions of other portions of PU 106.
~ aving described PV 106's CPUP 122, the transmission paths by which information, primarily data --7~-2:~

and addresses, are transferred between MEM 102 and PU
106, and in particular CPUP 122, will be described next below. These transmission paths include MAD Bus 108, by which read and write addresses are provided to MEM 102 by ~U 106~ and MDA Bus 110, by which instructions an~
data are communicated between PU 106 and M~M 102.
Paths internal to PU 106 include D Bus 112 and Y
Bus 124. As indicated in Fig. 6~ MDS 132 is connected bet~een D Bus 112 and MDA Bus 110 and between MDA Bus 110 and Y bus 1~4. MDS 132 includes Memory Data Register (MDR) 602, having a 32 bit input conrlected from D 3us 11~ and a 32 outpu~ connected through buffer driver M~RB 602 to MDA Bus 110. I~BS 132 also includes Memory Data Latch (MDL) 6Q4, which has 32 bit input connected from MDA Bus 110 and a 32 hit output connected to Y Bus 124. Finally, PV 106's internal data path further includes NIBS 126, having a 32 bit input connected from Y Bus 124 and a 32 bit output connected l~o D Bus 112. ~.AD 130r comprising prJ 106's address output to MAD Bus 108, will be discussed separately further below, in conjunction with the discussion o~
SPAD 128.

Considering first data transfers from M~M 102 to PU
106, data read rom M~M 102 appears on MDA Bus 110 and may be received and stored :in MDL 60~. That data may be then transferred from MDL 604 to Y Bus 124, and may then be transferred from Y Bus 124 to NIBS 126~
NIBS 126 is a nibble shifter and is capable of either passing data straight through or performing right or left shifts of data on a nibble by nibble basis.
NIBS 12~ is used, for example, to ~hift data within words received from MEM 102 into difrering formats for subsequent operations by CPUP 122. NIBS 126 mayt for example, be further used to reorganize data resulting from operations CPUP 122 into ormats selected for storing such data in MEM 102 2.s previously described, NIBS 126'~ output is connected to D Bus 112, so that data appearing on Y Bus 124 may be transferred onto D Bus 112, either directly as a straight through-put or after being operated upon by NIBS 126.
As previously described the output of CPU~ 122 is connected to~Y Bus 12~, so that data genera8ed as a result oE CPUP 122 operations may be txansferred, ~8~

through NIBS 126, to D Bus 112. Again, data transferred through NIBS 126 rom output of CPUP 122 may be passed directly through NIBS 126 or may be opera~ed upon by NIBS 126~ For example, NIBS 126 may perform ali9nment operations upon data outputs of CPUP 122 in preparation for subsequent write operation to MEM lC2.
Data appearing on D Bus 112 may then be transferred into MDR 602 and subse~uently transferred through ~DRB
603 to MDA Bus 110 and thus written into MEM 102 Alternately, data appearing on D Bus 112 may be trans~erred into CPUP 122's data input. Data appearing on D Bus 112 may also be transferred through Buffer 606 to DBIO 136 for subsequent transfer to external storage devices.
Before describing SPAD 128 and MAD 130, two further features associated with operation of CPUP 122 will be described next. The first is the use of CPUP 122 to perorm increment by two operations and the second is the multiple uses of Temporary Register tTREG) 608, which is bi-directionally connected rom D Bus 112.
A common operation, for example, in manipulating addresses and other arithmetic operationst is to increment a given number by two. The ~MD 2901Cs utilized in CPUP 122 are, ho~lever, not directly capable o performing an increment by two operation. ~inus 2 Source (MINUS2) 610 having an output to D Bus 112, and a microinstruc~ion seq~ence from US 116, allow CPUP 122 to perform increment by two oE~rations. MINUS2 610 is a source for placing on D Bus 112 ~ 32 bit number having a nu~,eric vallle of minus 2~ CPUP 122 contains the number to be incremented by 2 in its register file. It accepts the minus 2 operand provided by MINUS2 610, and compliments it (giving a ~1) and per.orms an add operation with the number to be incremented to give a number equal to the operand to be incre~ented plus 1.
At the same time, a plus 1 is forced into CPU 122's .~LU
carry input to provide a further plus 1 increment. The output of CPUP 122's ALU will thereby be the original operand incremented by 2. MINUS2 610 thereby allows CPUP 122 to perform a commonly desired operation not originally provided for by the ~MD 2901ccircuits employed therein, Referring now to TREG 60B, TREG 608 is a 32 bit shift register which may be used or temporary storage 2;~

of data appearing on D Bus 112, from which TREG ~08 is connected by a bi-directional 32 bit bus. T~EG 608 is further utili~ed to generate 32 bit long control word sequences for controlling other operations of CS 101.
Under microcode control, a 32 bit pattern of ones and zeros is loaded into TREC 608. That 32 bit pattern is then shifted rlght or left as necessary to ~enerate bLt sequences which are used, for example, to ~erorm system resets, to perform timed input/output operations, and to control ~uffers for program~ed input and output operations. T~EG 608 thereby provides an extended means for controlling certain operations of CS 101 while utilizing already existing circuitry normally intended for temporary data storage functions.
Referring now to SPAD 128 and MAD 130~ SP~D 128, having inputs connec~ed from Y 3us 124, performs address translation and mapping functions as previousl~
described. SPAD 128, for example, accepts logical addresses from Y 3us 12~ and provides corre~ponding physical addresses to MAD 130. MAD 130 transfers addresses from SPAD 128 to MAD Bus 108. In addition, MAD 130 operates ln conjunction with IPD 114 as a ~W~d~

prefetch mechanism by generating and providing prefetch read addresses to MEM 102 through MAD Bus 108.
Re~erring ~irst to SPAD 128, the core o~ SPAD 128 is SPAD Memory (SPADM) 129. SPADM 129 is a random access memory used in part by PU 106 and CS 101 as a scratch pad memory. SPADM 129 is further utilized ~o store address map~ing information, and thus is a part of CS 101 ~ 5 addressing mechanism. For example, SPADM 129 may be used to store address translation maps for CS
lOl's data channel, burst multiplexer channel, programmed I/O, through DBIO 136. SPADM 129 is also used to store addressing maps for logical to physical address translations. In addition, SPADM 129 contains cs lOl's ~egment Base Registers (SBRs), previouslv described, and a portion of SPADM 129 is utilized as accumulators for floating point operations.
As indicated in Fig~ 6, SPA~ 128 includes an internal addressing bus~ referred to as Logical Address Register (LAR) Bus 132, ~nd a data bus, referred to as SPAD Bus 134. LAR Bus 132 is connected from Y 3us 124 through Logical Address Register (LARR) 136 and Logical Address Register Multiplexer (LARM) 138~ LARR 136 has a 32~

32 bit output to LAR Bus 13 2 and has inputs f rom Y Bus 12~ and f rom LARM 1380 LARR 136 and LARM 138 are utilized to provide logical and physical addresses to SP~D 128 and MAD 130 The general format of CS lOl's logical addresses has heen previously described. In those descriptions, certain bits were indicated as representing physical or logical page numbers and page offsets, while other bits comprise qarious control fieldsO As shown in Fig. 6, LARR 136 has a first lS bit input connected from Y Bus 124 for receiving 16 bit physical and logical page offset fields from Y Bus 124. LARR 136's second input is connected from LARM 138 and comprises those 16 bits of address used for logical and phy3ical page number fields,, various control fields, and al50 for short addresses. LARM 138 includes a first 16 bit input connected ~rom Y Bus 124 to receivel for example, a correspondins 16 bits of page number field from Y Bus 124 when LARR 136's ~irst input is receiving a page offset fieldO L~RM 138 further includes 2 inputs to enahle varyi~g formats to be selected for bits 0 to 16 o addresses to be provided to SPAD 128. For example, --~3--ID r~

.hree bits (CRE) of each of these two inputs represents which of CS lOl's 8 memory space segments CS 101 is to be addressed by a particular addressr while other bits of these two inputs are taken from Y Bus 124.
As indicated in FigO 6, LARR 136 7 S 32 bit output is connected to L~R Bus 132, which in turn is a source of addresses to SPADM 123, to CS lOl's address translation unit control, TG 1~6 and ATC 148, and to MAD 130.
A first output of LAR Bus 132 is directly to MAD
130, and in particular to an input of MAD Multiplexer ~MADM) 140. As will be described further below, ~ADM
1~0 is a source of physical address offset ields for M~D 130's output~ LAR Bus 132's output directly to MADM
140 is used, for example, to provlde physical pa~e ofsets to MADM 140 when PU 106 is dixectly physlcally addressing M~M 102. This path is also used, in further example, to provide single and double level page table oEset fields when perorming single and double level page table translations of logical to physical addresses, as previously described.
LAR Bus 132 is ~urther provided wit~ a direct path through Bufer 142 to SP~.D Bus 134. As will be z~

described further below, this path may be used to provide physical page number fields directly to Memory Address Latch tMAL) 150 in MAD 130 from L~RR 136 in conjunction with the correspondi~g offs~t field of a physical address as described above. Finally, will be described further below, S~ADM 129 is provided with a bi-directional data input/output connection to SPAD BU5 134. The path comprising LAR Bus 132~ Buffer 142, and SP.~D Bus 134 may also be used, for example~ to write information, such as address maps, into SPADM 129 from L~RR 136.
LAR Bus 132 also provides an input into SP~D
Multiplexer (SPAM) 144, which has an address output connected to SPADM 129's address input (.~D). SP~M 144 is the means by which SP~DM 129 is addressed for read and write ope~ations~ The path comprising LAR Bus 132 and first input of SPAM 144 is used, in part, to address SPADM 129 .
SPAM 144 i.s provided with three further inputs.
Two of these inputs, ACD and ACS, are provided from IR
578 in IPD 114, respectivelyt and identify destination and source accumulators. ACD and ACS may be used, for .. .

example, in addressir.g SPADM 1291s address locations assigned, for example, as floating point accumulators.
SP~M 144's fourth input is connected from UIR Bus 540 in US 116 is used to microinstruction control in addressing SPADM
The above combination of address sources for SPAM
144 allo~7s, for example, ACS or ACD inputs to specify a base address in SPADM 129 and VIR microinstruction inputs to specify an o fset from such a base address to a floating point source or destination accumulator.
This addressing mode also allows tbe ACS field of IR 578 to be determined without performing a mas~ and shift operation to read ACS field from IR 578; the information is instead determined from a read from SPADM 129, wlth the results of such an ACS read indicating the contents of IR 578's ACS field. Microinstruction and I~ 578 addressing of SPAD~ 129 also allows constants to be ~tored in and recovered from SPADM 129 as required.
Finally, LAR Bus 132 provides an output to SPAV
128's address translation control unit, comprising Tag Compare ~TC) 146 and Address Translation Control (ATC) 148. TC 146 receives certain portions of addresses 2~

appearing on L~R Bus 132 and SPAD Bus 134 and, utilizing this information, generates control inputs to ATC 148.
.TC 148 has a bi-directional connection to Y Bus 1~4 to receive address translation control information therefrom and to provide such control informatio~ onko Y
Bus 124, Referring to SPAD Bus 134, as previously described SPAD Bus 134 has a direct 32 bit connection from LAR Bus 132 through Buffer 142 and has a bi-di~ectional 32 bit input/output to SPADM 129. Certain address fields, that is, physical page number fields, appearing on SPhD Bus 134 from SPADM 12~, or from Buffer 142, may be transferred in~o Memory Address Latch ~MAL) 150 in MAD

~ inally, SPAD Bus 134 has a 32 bit hi-directional input/output connection to D Bus 112 through SPAD Buffer (SPADB) 152. SPADB 152 allows operations to be performed on SPAD Bus 134, for example writing a page number into MAL 150, while leaving D Bus ].12 free for other, concurrent operations. SPADB 152 allows information to be transferred between D Bus 112 and SPADM 129 or TC 146. For example~ address information -~7-z~

may read from SPADM 129 to D ~us 112, or may be read from D Bus 112 and written into SPADM 129 for example, when loading address maps into SPADM 129. 5PADB 152 is particularly used, for example, in floating point operations and for any o~eration wherein SPADM 129 is being used as P~ 106's scratchpad memory, or general registers.
~ aving described SPAD 128, MAD 130 will be described next below.

3~ D'~._f~
As previously described, MAD 130 is connected ~rom outputs of SP~D 128 and in turn has an output connected to MAD Bus 108. MAD 130 receives physical addresses from SPAD 128 and transfers those physical addresses to MAD Bus 108 to address MEM 102 for read and write operations. MAD 130 al90 operates in conjunction with IPD 114 as an instruction prefetch mechanism by providing instruction pre~etch ph~sical addresses to MEM
102.
As also prev-iously described, physical addresses ~or reading from or writing to ~EM 102 are comprised of -a physical page number field and a physical page ofrset field. As described above, physical page n~nber fields are pro~rided by SPAD 128 to MAL 150 through SPAD Bus 134~ either from SPADM 129 or from LAR~ 136 through Buffer 142. Physical page offset fields are provided to MADM 140 by LARR 13~ through the bus connection directly from LAR Bus 132 to an input of MADM 140.
Outputs of MAL 150 and MADM 140 are connected to Memory Addressing Internal (MADI) Bus lS4, which is connected in turn through Memory Address BufXer (MADB) 15~ to MAD Bus 108~ Physical addresses rec~ived by MAD
130 from SPAD 128 may thereby be assembled from MAL 150 and MADM 140 onto MADI Bus 154 and transferred onto MAD
Bus 108 to address MEM 1020 That portion of MAD 130 which operates as part o CS 101's prefetch mechanism includes Prefetch Page Number Register (PPNR) 158, Prefetch Page Offset Counter (PPOC) 160. and Write Compare (WCOMP) 162. PPNR 158 has an input connected from and an output connected to MADI
Bus 154. PPOC 160 has an input connected from MADI Bus 154 and a:n output connected from PPNR 158 and MADI Bus 154 and provides outputs to IPD 114.

An initial physical address, including page number and page offset, from which instruction prefetch is to begin is generated by SPAD 128 and is transerred onto MADI Bus 154. Page number and page offset are then transferred from MADI Bus 154 into, respectively, PPNR
158 and PPOC 160. Thereafter, page cffset in PPOC 160 is successively incremented and combined, through ~ADM
140, with pase number read from PPNR 158 to provide successive instruction prefetch read addresses on MADI
Bus 154 and thus onbo MAD Bus 108 to etch successive double words containing instructions from MEM 102 Sequential instructions are fetched from consecutive lQ~ pages, thus barring address j~mps. Consecutive logical pages need not be cor.secutive ~hysical pages.
PPNR 158 is i.~plemented as a register, rather than a counter, to prevent prefetch from crossing pnysical page boundaries. When PPOC 160 over10ws, prefetch is stopped until PPNR 158 is loaded with a ne~ phycical page number, corresponding to the next sequential logical page of execution.
WCOMP 162 chec~s each physical address to MEM 102 for ~rite operations and compares such addresses to addresses of instructions prefetched by MAD 130 and IPD
114~ If a write operztion is executed to a physical address ~ithin the same page as a prefetched instruction, WCO~P 16~ provides an output lndicating that the contents of IPD l:L4 are no longer valid CS
101 will respond by einit~ating prefetch to obtain ne~
valid instructions from ~EM '02.
~ escription of a preferred embodiment of the present invention ls hereby concluded. The invention may be embodied in yet other specific forms without departing from the spirit or essential characteristics thereof. Thus/ the present embodiments are to be considered in all respects as illustr2tive and not restrictive, tne scope of the invention being in~ica~ed by the appended claims rather than by the foresoing description, and all changes which come within the meaning and range of equiva1ency of the claims are therefore intended to be embraced tnerein.

Claims (5)

What is claimed is:

1) In a data processing system including processor means for processing said data and including addressing means for providing memory read and write addresses, memory means for storing said data and responsive to said addresses for transferring said data to and from said processor means, and bus means including data lines and check bit lines for conducting said addresses and data between said memory means and said processor means, memory control means, comprising:
memory control internal bus means including a plurality of data line corresponding to said bus means data lines, check bit checking and providing means having first inputs connected from and first outputs connected to said internal bus means and second inputs connected to said check bit lines of said bus means, and bidirectional buffer means connected between said bus mean data lines and said internal bus means data lines, said memory control means responsive to operation of said processor means and said memory means (a) during memory write operations for accepting said data to be written into said memory means from said bus means data lines generating corresponding check bits, and providing said corresponding check bits on said bus means check bit lines, and (b) during memory read operations accepting said data and corresponding check bits read from said memory means from said bus means data and check bit lines and determining whether said data read from said memory means contains errors concurrently with said data read from said memory means being received by said processor means.

2) The memory control means of claim 1, wherein said bidirectional buffer means further comprises a plurality of independently selectable byte input buffer means connected from separate bytes of said bus means data lines to corresponding bytes of said internal bus means data lines and responsive to operation of said processor means to selectively transfer bytes of said data from said bus means to said internal bus means, and a plurality of independently selectable byte output buffer means connected from said separate bytes of said internal bus means data lines corresponding bytes of said bus means data lines and responsive to operation of said processor means to selectively transfer bytes of said data from said internal bus means to said bus means, and said said check bit means further comprises a plurality of independently controllable byte input register means connected from corresponding said bytes of said internal bus means data lines for selectively receiving bytes of said data into said check bit means, and a plurality of independently controllable byte output register means connected to corresponding said bytes of said internal bus means data lines for selectively providing bytes of said data to said internal bus means.

3) The memory control means of claim 2, wherein said processor means further comprises:
a plurality of independently controllable byte output register means connected to corresponding said bytes of said bus means data lines for selectively transferring bytes of said data from said processor means to said bus means.

4) The memory control means of claim 3, wherein each one of said memory write operations is of a first fixed plurality of bytes of said data equal to the said plurality of said bytes of said bus means data lines.

5) In the memory control means of claim 4, the method of performing a said memory write operation of a second plurality of said bytes of data wherein said second plurality of bytes of data is less than said first plurality of bytes, comprising the steps of;
(a) reading from said memory means a said first plurality of bytes including bytes corresponding to the bytes of a said second plurality of bytes, (b) receiving said a said first plurality of bytes, and said corresponding check bits into said check bit means input register means, (c) correcting said a said first plurality of bytes if an error is detected therein, (d) transferring said a said second plurality of bytes from said processor means and through said corresponding output register means to said corresponding bytes of said bus means data lines, (e) transferring said a said second plurality of bytes from said corresponding bytes of said bus means and through said corresponding said bytes of said control means input buffer means and said corresponding bytes of said internal bus means into said corresponding bytes of said check bit means input register means to form, in combination with non-corresponding bytes of said a said first plurality of bytes, a new said first plurality of bytes, (d) generating said corresponding check bits for said new said plurality of bytes, and (e) transferring said new said first plurality of bytes and said check bits onto said bus means and writing said new said first plurality of bytes and said corresponding check bits into said memory means.