CA1191560A - Short-protected buffer - Google Patents
Short-protected bufferInfo
- Publication number
- CA1191560A CA1191560A CA000443506A CA443506A CA1191560A CA 1191560 A CA1191560 A CA 1191560A CA 000443506 A CA000443506 A CA 000443506A CA 443506 A CA443506 A CA 443506A CA 1191560 A CA1191560 A CA 1191560A
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- Prior art keywords
- source
- coupled
- transistor
- gate
- voltage
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Logic Circuits (AREA)
- Emergency Protection Circuit Devices (AREA)
- Amplifiers (AREA)
- Control Of Electrical Variables (AREA)
- Protection Of Static Devices (AREA)
Abstract
SHORT-PROTECTED BUFFER CIRCUIT
Abstract A short-protected buffer circuit comprising a source current output transistor (T1, Fig. 3) and a sink current output transistor (T2) is capable of providing high output current at low output voltage. A current-limiting bypass circuit, comprising two series-connected field effect transistors (T3 and T4) and a voltage reference (T5 and T6), limits the gate voltage on the source current output transistor (T1) and thus limits the output source current.
The circuit is compact and can be implemented in integrated circuit form. The output voltage at which protection starts is independent of temperature and of process variations.
Abstract A short-protected buffer circuit comprising a source current output transistor (T1, Fig. 3) and a sink current output transistor (T2) is capable of providing high output current at low output voltage. A current-limiting bypass circuit, comprising two series-connected field effect transistors (T3 and T4) and a voltage reference (T5 and T6), limits the gate voltage on the source current output transistor (T1) and thus limits the output source current.
The circuit is compact and can be implemented in integrated circuit form. The output voltage at which protection starts is independent of temperature and of process variations.
Description
SHORT-PROTECTED BUFFER CIRCUIT
Technical Field This inven~ion r~lates generally to a buffer circuit ~uitable for implementation in an integrated circuit, and~
in parti~ular, to a bufer circuit ~hich provides a current limiting prvtection to ~he output transistors~
Background of the Invention In the design of int~grated circuits it i~ known to provide output buffer circuits between signals in~ernal to the integrated circuit and signals off-chipO Since it is ge~erally undesirable to have larg~ current signals within the integrated circuit, as large currents can inhibit the ability of the chip to dissipate heat a~ well as the Qperational speed of the circuits internal to the chip, a significant function performed by output buffer circuits is to tran~late the relatively low curren~ on-chip si~nals into relatively large current off-chip signals.
Cer~ain applîcations of int~grated circui~s re~uire the generation of output si~nals having relatively low voltage and rela~ively high current. Prior art output buffers have not been able to provide signals ~o these pecifications without utilizing large on-chip devicesO
For example, referring to FIGo 1~ there is shown a prior art short~protected output buffer~ The circuit comprises a constant current source in the form of 3G depletion m~de transistor T7, whose drain is connected to a ~upply voltage, who~e ~ource is connected to its gate, to th~ drain o inverter transistor T8 and to the gate of source current output transistor Tl. The input at lead 5 is ~vnn~cted to the g~te of inverter TB and to the gate of 6ink current output transi~tor T2~ The output is taken off ~,~., lead lOo A large on-chip diffused resistor R is connected betwe~n the drain of transis~or Tl and the supply voltage.
An input signal at a giv~n logic lev~l (binary 1 or 0) is inverted by transistors T8 and T2~ For example~ if the input is 1, then T8 and T2 will be condllctive. The gate voltage on Tl will b~ low, rendering it non-conduc~ive, and output lead 10 will be ~hunte~ to ground through T2. If the input is 0, then T8 and T2 will be non~conductiveO The gat~ voltage on Tl will be high, so ~hat Tl will be condue~ive, and thus output lead 10 will be highO
It will b~e under~tood by one of ordinary skill in the art that regarding enhanc~ment mode transistors, such as Tl,T2t and T8, he transistor is rendered conduc~ive when the gate-to-sour~e voltage is equal to or exceeds the threshold voltage V~0 When the gate-to-source voltage is just equal to VT~, the ~ransistor is soft conducting, iue. just beginning to conduct~ A5 the gats-to-source voltage is increased J the drain~to-source current increases until eventually a limit is reached
Technical Field This inven~ion r~lates generally to a buffer circuit ~uitable for implementation in an integrated circuit, and~
in parti~ular, to a bufer circuit ~hich provides a current limiting prvtection to ~he output transistors~
Background of the Invention In the design of int~grated circuits it i~ known to provide output buffer circuits between signals in~ernal to the integrated circuit and signals off-chipO Since it is ge~erally undesirable to have larg~ current signals within the integrated circuit, as large currents can inhibit the ability of the chip to dissipate heat a~ well as the Qperational speed of the circuits internal to the chip, a significant function performed by output buffer circuits is to tran~late the relatively low curren~ on-chip si~nals into relatively large current off-chip signals.
Cer~ain applîcations of int~grated circui~s re~uire the generation of output si~nals having relatively low voltage and rela~ively high current. Prior art output buffers have not been able to provide signals ~o these pecifications without utilizing large on-chip devicesO
For example, referring to FIGo 1~ there is shown a prior art short~protected output buffer~ The circuit comprises a constant current source in the form of 3G depletion m~de transistor T7, whose drain is connected to a ~upply voltage, who~e ~ource is connected to its gate, to th~ drain o inverter transistor T8 and to the gate of source current output transistor Tl. The input at lead 5 is ~vnn~cted to the g~te of inverter TB and to the gate of 6ink current output transi~tor T2~ The output is taken off ~,~., lead lOo A large on-chip diffused resistor R is connected betwe~n the drain of transis~or Tl and the supply voltage.
An input signal at a giv~n logic lev~l (binary 1 or 0) is inverted by transistors T8 and T2~ For example~ if the input is 1, then T8 and T2 will be condllctive. The gate voltage on Tl will b~ low, rendering it non-conduc~ive, and output lead 10 will be ~hunte~ to ground through T2. If the input is 0, then T8 and T2 will be non~conductiveO The gat~ voltage on Tl will be high, so ~hat Tl will be condue~ive, and thus output lead 10 will be highO
It will b~e under~tood by one of ordinary skill in the art that regarding enhanc~ment mode transistors, such as Tl,T2t and T8, he transistor is rendered conduc~ive when the gate-to-sour~e voltage is equal to or exceeds the threshold voltage V~0 When the gate-to-source voltage is just equal to VT~, the ~ransistor is soft conducting, iue. just beginning to conduct~ A5 the gats-to-source voltage is increased J the drain~to-source current increases until eventually a limit is reached
2~ ~eyond which the transistor is saturated.
Regarding the ou~pu~ buffer shown in FIGo 1~ let us assume that VTE of Tl is 1. 0 volts~ and let u~ assume that the input is a logical 0. Let us further assume that the`output voltage on lead 10 is 5~0 volts, and that transistor T7 is supplying ~ full 500 volts on lead 7 to ~he gate of Tl. Under these conditions the gate-to-source voltage across Tl is 0.0 volts~ and Tl is non~conductive, If the output voltage on lead 10 is 4.0 vol~s, ~hen 30 the ga~e to-source voltage across Tl is loO volts/ and Tl just begins to turn on.
If the input at lead 5 has just switched from 1 to 0, the voltage on lead 7 has quickly risen to 5.0 volts, while the voltage on lead 10 remains at ground potentialO Thus the gate-to-source voltage acro~s Tl is approximately 5.0 volts, so Tl is turned hard on~
5~;~
Still regarding the prior art circuit shown in FIG. 1, the source current output transistor T] is protected against excessive drain-to-source current by resistor Ro However, this resistor limits the drain-to-source current of Tl, so that the output current is also limited. In order to generate high output current, very larqe output transistors Tl and T2 and a very large resistor R ~ust be provided. But these large devices result in a large, expensive in~egrated circui~. Also the resultant integrated circuit has high power consurnption.
FIG. 2 shows another prior art short-protected buffer circuitO The circuit shown in FIGo 2 is identical to that shown in FIG~ 1, except that bypass transistors T3 and T4 are series~connected between the gate of transistor Tl and the output lead 10. T3 and T4 are connected as diodes, with their gates connected to their respective drains.
When the drain-to-source voltage drop across both T3 and T4 (i.e. between the gate of Tl and output lead 10) is equal to the sum of their threshold voltages, T3 and T4 are both turned on. That is, the forward voltage is equal -to the sum of their threshold voltages, so each diode turns on.
As a result, the gate-to-source voltage on Tl cannot exceed a voltage which is equal to the 5.0 volt supply voltage less two times VTE. Thus a limit is imposed on the gate-to-source voltage on Tl~ and as a consequence a limit is imposed on the maximum output currentO
A major disadvantage of the prior art circuit shown in FIG. 2 is that the protective action begins while the output voltage is still at too high a value. As mentioned above, certain applications require a relatively high output current at a relatively low output voltage, while still maintaining a limit on the output currentO To achieve this result using the circuit shown in FIG. 2, output transistor Tl would have to be greatly enlarged, and the resulting integrated circuit would also be grea-tly enlarged and therefore more expensive.
The present invention overcomes the disadvantages associated with the above-described prior art output buffsr circuits.
Brief Summary of Invention Accordingly, it is an object of the present invention to provide an improved short-protected buffer circuit.
It is also an object of the present inven~ion to provide a short-protected buffer circuit which can provide relatively high output current levels even at low output voltage levels.
It is a further object of the present invention to provide a short-protected buffer circuit which does not require implementation using large integrated circuit devices.
It is yet another object of the present invention to provide a short-protected buffer circuit whose operation is s-table and independent of temperature or process variations.
These and other objects are achieved in accordance with a preferred embodiment of the invention by providing a short-protected buffer circuit having an input and an output, the circuit comprising a voltage source, the voltage source being at a certain potential relative to ground; a source current output transistor having a drain coupled to the voltage source, a source coupled to the output, and a gate; a sink current output transistor having a drain coupled to the output, a source coupled to ground, and a gate; and a protection circuit for protecting the outpu~ transistors from excessive current, the protection circuit comprising a voltage reference; a third transistor having a drain coupled to the gate of the source current output transistor, a source, and a gate coupled to its ` 35 drain; and a fourth transistor having a drain coupled to :~3L9~
the source of the third transistor, a source coupled to the output, and a gate coupled to the voltage reference.
Brief Description of the D~awings The invention is pointed out with particularity in the appended claims. However, other features of the invention will become more apparent and the invention will be best understood by referring to the following detailed description in conjunction with the accompanying drawings in which:
FIG. 1 shows a prior art short-protected buffar circult .
FIG~ 2 shows another prior art short-protected buEfer circuit.
FIG. 3 shows a circuit diagram of a preferred embodiment of the short-protected buffer circuit of the present invention.
FIG. 4 shows an equivalent circuit to that shown in ~IG. 3 for ease in understanding the operation of the FIG.
Regarding the ou~pu~ buffer shown in FIGo 1~ let us assume that VTE of Tl is 1. 0 volts~ and let u~ assume that the input is a logical 0. Let us further assume that the`output voltage on lead 10 is 5~0 volts, and that transistor T7 is supplying ~ full 500 volts on lead 7 to ~he gate of Tl. Under these conditions the gate-to-source voltage across Tl is 0.0 volts~ and Tl is non~conductive, If the output voltage on lead 10 is 4.0 vol~s, ~hen 30 the ga~e to-source voltage across Tl is loO volts/ and Tl just begins to turn on.
If the input at lead 5 has just switched from 1 to 0, the voltage on lead 7 has quickly risen to 5.0 volts, while the voltage on lead 10 remains at ground potentialO Thus the gate-to-source voltage acro~s Tl is approximately 5.0 volts, so Tl is turned hard on~
5~;~
Still regarding the prior art circuit shown in FIG. 1, the source current output transistor T] is protected against excessive drain-to-source current by resistor Ro However, this resistor limits the drain-to-source current of Tl, so that the output current is also limited. In order to generate high output current, very larqe output transistors Tl and T2 and a very large resistor R ~ust be provided. But these large devices result in a large, expensive in~egrated circui~. Also the resultant integrated circuit has high power consurnption.
FIG. 2 shows another prior art short-protected buffer circuitO The circuit shown in FIGo 2 is identical to that shown in FIG~ 1, except that bypass transistors T3 and T4 are series~connected between the gate of transistor Tl and the output lead 10. T3 and T4 are connected as diodes, with their gates connected to their respective drains.
When the drain-to-source voltage drop across both T3 and T4 (i.e. between the gate of Tl and output lead 10) is equal to the sum of their threshold voltages, T3 and T4 are both turned on. That is, the forward voltage is equal -to the sum of their threshold voltages, so each diode turns on.
As a result, the gate-to-source voltage on Tl cannot exceed a voltage which is equal to the 5.0 volt supply voltage less two times VTE. Thus a limit is imposed on the gate-to-source voltage on Tl~ and as a consequence a limit is imposed on the maximum output currentO
A major disadvantage of the prior art circuit shown in FIG. 2 is that the protective action begins while the output voltage is still at too high a value. As mentioned above, certain applications require a relatively high output current at a relatively low output voltage, while still maintaining a limit on the output currentO To achieve this result using the circuit shown in FIG. 2, output transistor Tl would have to be greatly enlarged, and the resulting integrated circuit would also be grea-tly enlarged and therefore more expensive.
The present invention overcomes the disadvantages associated with the above-described prior art output buffsr circuits.
Brief Summary of Invention Accordingly, it is an object of the present invention to provide an improved short-protected buffer circuit.
It is also an object of the present inven~ion to provide a short-protected buffer circuit which can provide relatively high output current levels even at low output voltage levels.
It is a further object of the present invention to provide a short-protected buffer circuit which does not require implementation using large integrated circuit devices.
It is yet another object of the present invention to provide a short-protected buffer circuit whose operation is s-table and independent of temperature or process variations.
These and other objects are achieved in accordance with a preferred embodiment of the invention by providing a short-protected buffer circuit having an input and an output, the circuit comprising a voltage source, the voltage source being at a certain potential relative to ground; a source current output transistor having a drain coupled to the voltage source, a source coupled to the output, and a gate; a sink current output transistor having a drain coupled to the output, a source coupled to ground, and a gate; and a protection circuit for protecting the outpu~ transistors from excessive current, the protection circuit comprising a voltage reference; a third transistor having a drain coupled to the gate of the source current output transistor, a source, and a gate coupled to its ` 35 drain; and a fourth transistor having a drain coupled to :~3L9~
the source of the third transistor, a source coupled to the output, and a gate coupled to the voltage reference.
Brief Description of the D~awings The invention is pointed out with particularity in the appended claims. However, other features of the invention will become more apparent and the invention will be best understood by referring to the following detailed description in conjunction with the accompanying drawings in which:
FIG. 1 shows a prior art short-protected buffar circult .
FIG~ 2 shows another prior art short-protected buEfer circuit.
FIG. 3 shows a circuit diagram of a preferred embodiment of the short-protected buffer circuit of the present invention.
FIG. 4 shows an equivalent circuit to that shown in ~IG. 3 for ease in understanding the operation of the FIG.
3 circuit.
FIGo 5 shows a graph of output current versus output voltage regarding the preferred embodiment.
FIG. 6 shows a graph of the gate voltage on transistor Tl of the pre~erred embodiment versus the output voltage.
Uetailed Description of the Invention FIG~ 3 shows a circuit diagram of a preferred embodiment of the short-protected buffer circuit of the present invention~
The circuit shown in FIG. 3 differs from that shown in FIG~ 2 in at least one significant wayO In FIG. 3, transistor T4 is not connected as a diode, as in FIG. 2, but rather is operated as a transistor to whose gate is applied a reference voltage.
s~
The reference voltage i6 provided by transistor pair T5 and T6. T5 is a deple~ion mode transistor whose drain i5 connected to a voltag0 ~ource, which in the preferred embodiment is 5.0 volts~ The ~ource and gate of T5 are sonnected together and to ~he ~ate of T4~ Tran~istor T6 is an enhancement mode transistor whose drain is connected to its gate and to the ~ource of T5, and who~e source is coupled to ground.
Operation of Preferred Embodiment FIG. 4 shows an equivalent circuit to thak shown in FIG~ 3 for ease in understanding the operation of the FIGo 3 circuitO ~egarding FIG. 3, when the input on lead 5 is lS low, then T8 and ~ are off, so the current source provided by T7 can be shown in equivalent fashion as Gl in FIG~ 4, and T8 and T2 can be deleted. In FIGo 3, T3 is operating as a diode, whose equivalent diode D is shown in FIG. 4.
Also in FIG. 3; T5 and T6 are operating as a voltag 20 source, repres~nted by voltage ~ource 12 in FIG. 4, In PIG. 4 I diode D has a forward YOltage VTE ~
which is def ined as the voltage required to just start conduction in the forward direction (iOe~ frc)m the gate of Tl to the drain of T4 ) through D,, Voltage source 12 is ~5 regulated to VTE, where VTE is defined as the threshold voltage of an enhancement mode transistor, such as T40 Let us as~ume that when VTE is 1~ 0 volts, T4 just starts to conduct, and that when VI,E reaches 1~ 4 volts y T4 is fully conductive.
In FIGr 4 let us also connect a variable voltage source 14 to thP output lead 10 in order to see how the protection circuit operates as the output voltage changes.
Tl will not be conductive unless its gate-to-source voltage is equal to or gr~ater than Vq,~. Like T4, transistor Tl wi 11 just start to conduct when its gate-to~
source voltage is approximately 1.0 volts, and it will be fully conductive when ~he gate-to-source voltage reaches l.4 volts.
Before we begin changing the variable voltage source 14 to explore the operation o the protection circuit, let us look at FIGS. 5 and 6, which will also aid in under-standing the operation of the preferred embodiment7 FIG. 5 shows a graph of output current versus output voltage, the output current being plotted on the Y axis and the output voltage being plotted along the X-axisO The solid line 20 represents ~he plot for the present invention, while the dashed line 30 represents that ~or the FIG. 2 prior art circuit. From FIG. 5 it will easily be seen that in the present invention the output current is signiEicantly higher at low output voltages than for the FIG. 2 prior art circuit~
FIG~ 6 shows a graph oE how ~he gate voltage on transistor T1 of the preEerred embodiment varies with the output voltage~ As in FIG. 5, the output voltage is plotted along the X-axis The gate voltage on Tl is plotted on the Y-axis. Again the solid line 40 represents the curve for the present invention, and the dashed line 50 represents that for the FIG4 2 prior art circuit. It will also be seen from FIG. 6 that the output current limiting 2S action in the present invention doesn't begin to occur until the output voltage drops to approximately 0.4 volts, as shown at point 41 on curve 40 t whereas ~he limiting action in the FIG~ 2 prior art circuit begins at approxi-mately 2.6 volts, as shown by point 51 on curve 50O
ReEerring now to both FIGS. 4 and 5, let us set the variable voltage VS on lead 10 to 5.0 volts~ Since the gate voltage on T4 is 1.4 volts, the gate-to-source voltage on T4 i5 1. 4 volts minus 5D O volts, or -3.6 volts, so T4 is definitely non-conducting, since, as mentioned above, T4 35 conduction begins when its gate-to-source voltage ls approximately +l.0 volts. Since T4 is non-conducting, the 56~
gate voltage on T1 is 5.U volts, and the gate-to~source voltage on Tl is 0.0 volts, so Tl is non-conducting~ This is confirmed in FIG, 5, which indicates no output current when the out~ut voltage is 5.0 volts D
If voltage VS is now reduced to 4.0 volts, r4 i5 still non~conductive. However, rrl just begins to turn on, since its gate-to-source voltage is approximately 1.0 voltsO
As VS is lowered further, Tl turns on increasingly harder, and the output current rises accordingly, as shown b~ curve 20 in FIGo 5O
When VS is lowered to 0.4 vol-ts, the gate-to-source voltage across T4 is 1.4 minus 0~4, or approxima~ely 1~0 volts r so T4 iS just starting to turn onO The forward voltage across diode D is greater than its threshold voltage, so it too becomes conductive. As a result~ the potential on the gate of Tl is decreased. Thus 0.4 volts is the value of the output voltage where the current limiting protection starts.
As VS is lowered still further below 0~4 volts, T4 turns on harder and harder, and the gate-to-source voltage on Tl is reduced still further, thus causing the output current to decrease, as shown by curve 20 in FIG. 5~
When VS is lowered all the way to 0.0 volts~ the gate--to-source voltage on T4 is equal to the reference voltage on the gate of T4, or 1O4 volts. The potential on the drain of T4 is 104 volts, and the potential on the anode of D is also 1.4 volts. So the ma4YimUm potential on the gate o~ Tl is twice VTE 9 or 2.8 vol-ts, as shown in FIG 6. The fact that the maximum potential on the gate of Tl is limited to twice VT~ limits the output source current.
It will be apparent to those skilled in the art that the disclosed Sho~t-Protected Buffer Circuit may be modified in numerous ways and may assume many embodiments other than the preferred form specifically set out and described above.
5~
For example, the output voltage at which the current limiting protection starts can be changedO This may be done by changing the voltage reference supplied to the gate of T4 by T5/T6 by changing the size (i.e9 the gate length and width) of T5. By changing the reference voltage on the gate of T4, the protection starting voltage is changed.
For example, if the output current level of the circuit is found to be too high at O.A output volts, then the reference voltage can simply be changed from 1.4 volts to 1.5 volts, thereby increasing the protec-tion starting voltage from 0~4 output volts to 0.5 output volts.
It will be noted that ~he protection starting voltage is determined by the difference between the reference voltage (approximately 1.4 volts) and the T4 threshold voltage (approximately 1.0 volt). Even if the threshold voltages are shifted, as a result of process variations, the reference voltage supplied by T5/T6 will shift in the same direction, so that the difference will remain constant. Thus the protection starting voltage will remain constant despite minor process variations which result in different thresholds on different wafers.
Likewise, the operating characteristics are not affected by variations in temperature, since such variations affect the reference voltage supplied by T5/T6 and the T4 threshold to the same extent, so that the difference again remains constant.
The present invention finds utility, for example, in a telephone control integrated circuit, but it will be understood that it may be implemented in many different forms depending upon the particular application required.
Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.
FIGo 5 shows a graph of output current versus output voltage regarding the preferred embodiment.
FIG. 6 shows a graph of the gate voltage on transistor Tl of the pre~erred embodiment versus the output voltage.
Uetailed Description of the Invention FIG~ 3 shows a circuit diagram of a preferred embodiment of the short-protected buffer circuit of the present invention~
The circuit shown in FIG. 3 differs from that shown in FIG~ 2 in at least one significant wayO In FIG. 3, transistor T4 is not connected as a diode, as in FIG. 2, but rather is operated as a transistor to whose gate is applied a reference voltage.
s~
The reference voltage i6 provided by transistor pair T5 and T6. T5 is a deple~ion mode transistor whose drain i5 connected to a voltag0 ~ource, which in the preferred embodiment is 5.0 volts~ The ~ource and gate of T5 are sonnected together and to ~he ~ate of T4~ Tran~istor T6 is an enhancement mode transistor whose drain is connected to its gate and to the ~ource of T5, and who~e source is coupled to ground.
Operation of Preferred Embodiment FIG. 4 shows an equivalent circuit to thak shown in FIG~ 3 for ease in understanding the operation of the FIGo 3 circuitO ~egarding FIG. 3, when the input on lead 5 is lS low, then T8 and ~ are off, so the current source provided by T7 can be shown in equivalent fashion as Gl in FIG~ 4, and T8 and T2 can be deleted. In FIGo 3, T3 is operating as a diode, whose equivalent diode D is shown in FIG. 4.
Also in FIG. 3; T5 and T6 are operating as a voltag 20 source, repres~nted by voltage ~ource 12 in FIG. 4, In PIG. 4 I diode D has a forward YOltage VTE ~
which is def ined as the voltage required to just start conduction in the forward direction (iOe~ frc)m the gate of Tl to the drain of T4 ) through D,, Voltage source 12 is ~5 regulated to VTE, where VTE is defined as the threshold voltage of an enhancement mode transistor, such as T40 Let us as~ume that when VTE is 1~ 0 volts, T4 just starts to conduct, and that when VI,E reaches 1~ 4 volts y T4 is fully conductive.
In FIGr 4 let us also connect a variable voltage source 14 to thP output lead 10 in order to see how the protection circuit operates as the output voltage changes.
Tl will not be conductive unless its gate-to-source voltage is equal to or gr~ater than Vq,~. Like T4, transistor Tl wi 11 just start to conduct when its gate-to~
source voltage is approximately 1.0 volts, and it will be fully conductive when ~he gate-to-source voltage reaches l.4 volts.
Before we begin changing the variable voltage source 14 to explore the operation o the protection circuit, let us look at FIGS. 5 and 6, which will also aid in under-standing the operation of the preferred embodiment7 FIG. 5 shows a graph of output current versus output voltage, the output current being plotted on the Y axis and the output voltage being plotted along the X-axisO The solid line 20 represents ~he plot for the present invention, while the dashed line 30 represents that ~or the FIG. 2 prior art circuit. From FIG. 5 it will easily be seen that in the present invention the output current is signiEicantly higher at low output voltages than for the FIG. 2 prior art circuit~
FIG~ 6 shows a graph oE how ~he gate voltage on transistor T1 of the preEerred embodiment varies with the output voltage~ As in FIG. 5, the output voltage is plotted along the X-axis The gate voltage on Tl is plotted on the Y-axis. Again the solid line 40 represents the curve for the present invention, and the dashed line 50 represents that for the FIG4 2 prior art circuit. It will also be seen from FIG. 6 that the output current limiting 2S action in the present invention doesn't begin to occur until the output voltage drops to approximately 0.4 volts, as shown at point 41 on curve 40 t whereas ~he limiting action in the FIG~ 2 prior art circuit begins at approxi-mately 2.6 volts, as shown by point 51 on curve 50O
ReEerring now to both FIGS. 4 and 5, let us set the variable voltage VS on lead 10 to 5.0 volts~ Since the gate voltage on T4 is 1.4 volts, the gate-to-source voltage on T4 i5 1. 4 volts minus 5D O volts, or -3.6 volts, so T4 is definitely non-conducting, since, as mentioned above, T4 35 conduction begins when its gate-to-source voltage ls approximately +l.0 volts. Since T4 is non-conducting, the 56~
gate voltage on T1 is 5.U volts, and the gate-to~source voltage on Tl is 0.0 volts, so Tl is non-conducting~ This is confirmed in FIG, 5, which indicates no output current when the out~ut voltage is 5.0 volts D
If voltage VS is now reduced to 4.0 volts, r4 i5 still non~conductive. However, rrl just begins to turn on, since its gate-to-source voltage is approximately 1.0 voltsO
As VS is lowered further, Tl turns on increasingly harder, and the output current rises accordingly, as shown b~ curve 20 in FIGo 5O
When VS is lowered to 0.4 vol-ts, the gate-to-source voltage across T4 is 1.4 minus 0~4, or approxima~ely 1~0 volts r so T4 iS just starting to turn onO The forward voltage across diode D is greater than its threshold voltage, so it too becomes conductive. As a result~ the potential on the gate of Tl is decreased. Thus 0.4 volts is the value of the output voltage where the current limiting protection starts.
As VS is lowered still further below 0~4 volts, T4 turns on harder and harder, and the gate-to-source voltage on Tl is reduced still further, thus causing the output current to decrease, as shown by curve 20 in FIG. 5~
When VS is lowered all the way to 0.0 volts~ the gate--to-source voltage on T4 is equal to the reference voltage on the gate of T4, or 1O4 volts. The potential on the drain of T4 is 104 volts, and the potential on the anode of D is also 1.4 volts. So the ma4YimUm potential on the gate o~ Tl is twice VTE 9 or 2.8 vol-ts, as shown in FIG 6. The fact that the maximum potential on the gate of Tl is limited to twice VT~ limits the output source current.
It will be apparent to those skilled in the art that the disclosed Sho~t-Protected Buffer Circuit may be modified in numerous ways and may assume many embodiments other than the preferred form specifically set out and described above.
5~
For example, the output voltage at which the current limiting protection starts can be changedO This may be done by changing the voltage reference supplied to the gate of T4 by T5/T6 by changing the size (i.e9 the gate length and width) of T5. By changing the reference voltage on the gate of T4, the protection starting voltage is changed.
For example, if the output current level of the circuit is found to be too high at O.A output volts, then the reference voltage can simply be changed from 1.4 volts to 1.5 volts, thereby increasing the protec-tion starting voltage from 0~4 output volts to 0.5 output volts.
It will be noted that ~he protection starting voltage is determined by the difference between the reference voltage (approximately 1.4 volts) and the T4 threshold voltage (approximately 1.0 volt). Even if the threshold voltages are shifted, as a result of process variations, the reference voltage supplied by T5/T6 will shift in the same direction, so that the difference will remain constant. Thus the protection starting voltage will remain constant despite minor process variations which result in different thresholds on different wafers.
Likewise, the operating characteristics are not affected by variations in temperature, since such variations affect the reference voltage supplied by T5/T6 and the T4 threshold to the same extent, so that the difference again remains constant.
The present invention finds utility, for example, in a telephone control integrated circuit, but it will be understood that it may be implemented in many different forms depending upon the particular application required.
Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.
Claims (17)
1. A short-protected buffer circuit having an input and an output, said circuit comprising a voltage source terminal for receiving a voltage source being at a certain potential relative to ground;
a source current output transistor having a drain coupled to said voltage source terminal, a source coupled to said output, and a gate;
a sink current output transistor having a drain coupled to said output, a source coupled to ground, and a gate; and a protection circuit for protecting said source current output transistor from excessive current, said protection circuit comprising a voltage reference;
a third transistor having a drain coupled to the gate of said source current output transistor, a source, and a gate coupled to its drain; and a fourth transistor having a drain coupled to the source of said third transistor, a source coupled to said output, and a gate coupled to said voltage reference.
a source current output transistor having a drain coupled to said voltage source terminal, a source coupled to said output, and a gate;
a sink current output transistor having a drain coupled to said output, a source coupled to ground, and a gate; and a protection circuit for protecting said source current output transistor from excessive current, said protection circuit comprising a voltage reference;
a third transistor having a drain coupled to the gate of said source current output transistor, a source, and a gate coupled to its drain; and a fourth transistor having a drain coupled to the source of said third transistor, a source coupled to said output, and a gate coupled to said voltage reference.
2. The short-protected buffer circuit as recited in claim 1 wherein said voltage reference comprises a first depletion mode transistor having a drain coupled to said voltage source terminal, a source coupled to the gate or said fourth transistor, and a gate coupled to its source; and a fifth transistor having a drain coupled to the source of said first depletion mode transistor, a source coupled to ground, and a gate coupled to its drain.
3. The short-protected buffer circuit as recited in claim 1, wherein said circuit comprises an inverter circuit said inverter comprising a constant current source;
a fifth transistor having a drain coupled to said constant current source and to the drain of said third transistor, a source coupled to ground, and a gate coupled to said input.
a fifth transistor having a drain coupled to said constant current source and to the drain of said third transistor, a source coupled to ground, and a gate coupled to said input.
4. The short-protected buffer circuit as recited in claim 3, wherein said constant current source comprises a first depletion mode transistor having a drain coupled to said voltage source terminal, a source coupled to the gate of said source current output transistor and a gate coupled to its source.
5. A short-protected buffer circuit having an input and an output, said circuit comprising a voltage source terminal for receiving a voltage source being at a certain potential relative to ground;
a source current output transistor having a drain coupled to said voltage source terminal, a source coupled to said output and a gate;
a sink current output transistor having a drain coupled to said output, a source coupled to ground, and a gate;
a protection circuit for protecting said output transistors from excessive current, said protection circuit comprising a voltage reference;
a third transistor having a drain coupled to the gate of said source current output transistor, a source, and a gate coupled to its drain; and a fourth transistor having a drain coupled to the source of said third transistor, a source coupled to said output and a gate coupled to said voltage reference;
and an inverter circuit, said inverter comprising a constant current source, said constant current source comprising a first depletion mode transistor having a drain coupled to said voltage source terminal, a source coupled to the gate of said source current output transistor, and a gate coupled to its source; and a fifth transistor having a drain coupled to said constant current source and to the drain of said third transistor, a source coupled to ground, and a gate coupled to said input.
a source current output transistor having a drain coupled to said voltage source terminal, a source coupled to said output and a gate;
a sink current output transistor having a drain coupled to said output, a source coupled to ground, and a gate;
a protection circuit for protecting said output transistors from excessive current, said protection circuit comprising a voltage reference;
a third transistor having a drain coupled to the gate of said source current output transistor, a source, and a gate coupled to its drain; and a fourth transistor having a drain coupled to the source of said third transistor, a source coupled to said output and a gate coupled to said voltage reference;
and an inverter circuit, said inverter comprising a constant current source, said constant current source comprising a first depletion mode transistor having a drain coupled to said voltage source terminal, a source coupled to the gate of said source current output transistor, and a gate coupled to its source; and a fifth transistor having a drain coupled to said constant current source and to the drain of said third transistor, a source coupled to ground, and a gate coupled to said input.
6. The short-protected buffer circuit as recited in claim 5 wherein said voltage reference comprises a second depletion mode transistor having a drain coupled to said voltage source terminal, a source coupled to the gate of said fourth transistor, and a gate coupled to its source; and a sixth transistor having a drain coupled to the source of said second depletion mode transistor a source coupled to ground, and a gate coupled to its drain.
7. The short-protected buffer circuit as recited in claim 1 wherein said first through fourth transistors are enhancement mode field effect transistors.
8. The short-protected buffer circuit as recited in claim 2 wherein said first through fifth transistors are enhancement mode field effect transistors.
9. The short-protected buffer circuit as recited in claim 3 wherein said first through fifth transistors are enhancement mode field effect transistors.
10. The short-protected buffer circuit as recited in claim 5 wherein said first through fifth transistors are enhancement mode field effect transistors.
11. The short-protected buffer circuit as recited in claim 6 wherein said first through sixth transistors are enhancement mode field effect transistors.
12. In a short-protected buffer circuit having an input and an output; a voltage source terminal for receiving a voltage source being at a certain potential relative to ground; a source current output transistor having a drain coupled to said voltage source terminal, a source coupled to said output, and a gate; a sink current output transistor having a drain coupled to said output, a source coupled to ground, and a gate; the improvement characterized whereby there is further provided a protection circuit for protecting said source current output transistor from excessive current, said protection circuit comprising a voltage reference; a third transistor having a drain coupled to the gate of said source current output transistor, a source, and a gate coupled to its drain; and a fourth transistor having a drain coupled to the source of said third transistor, a source coupled to said output, and a gate coupled to said voltage reference.
13. The short-protected buffer circuit as recited in claim 12 wherein said voltage reference comprises a first depletion mode transistor having a drain coupled to said voltage source terminal, a source coupled to the gate of said fourth transistor, and a gate coupled to its source; and a fifth transistor having a drain coupled to the source of said first depletion mode transistor, a source coupled to ground, and a gate coupled to its drain.
14. The short-protected buffer circuit as recited in claim 12, wherein said circuit comprises an inverter circuit, said inverter comprising a constant current source;
a fifth transistor having a drain coupled to said constant current source and to the drain of said third transistor, a source coupled to ground, and a gate coupled to said input.
a fifth transistor having a drain coupled to said constant current source and to the drain of said third transistor, a source coupled to ground, and a gate coupled to said input.
15. The short-protected buffer circuit as recited in claim 14, wherein said constant current source comprises a second depletion mode transistor having a drain coupled to said voltage source terminal, a source coupled to the gate of said source current output transistor, and a gate coupled to its source.
16. The short-protected buffer circuit as recited in claim 12 wherein said first through fourth transistors are enhancement mode field effect transistors.
17. The short-protected buffer circuit as recited in claim 14 wherein said first through fifth transistors are enhancement mode field effect transistors.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US46369783A | 1983-02-04 | 1983-02-04 | |
| US463,697 | 1990-01-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1191560A true CA1191560A (en) | 1985-08-06 |
Family
ID=23841000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000443506A Expired CA1191560A (en) | 1983-02-04 | 1983-12-16 | Short-protected buffer |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP0141819A4 (en) |
| JP (1) | JPS60500437A (en) |
| KR (1) | KR900001812B1 (en) |
| CA (1) | CA1191560A (en) |
| IT (1) | IT1178355B (en) |
| WO (1) | WO1984003181A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2384632B (en) | 2002-01-25 | 2005-11-16 | Zetex Plc | Current limiting protection circuit |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3407339A (en) * | 1966-05-02 | 1968-10-22 | North American Rockwell | Voltage protection device utilizing a field effect transistor |
| US3749936A (en) * | 1971-08-19 | 1973-07-31 | Texas Instruments Inc | Fault protected output buffer |
| US4096398A (en) * | 1977-02-23 | 1978-06-20 | National Semiconductor Corporation | MOS output buffer circuit with feedback |
| US4110633A (en) * | 1977-06-30 | 1978-08-29 | International Business Machines Corporation | Depletion/enhancement mode FET logic circuit |
| US4178620A (en) * | 1977-10-11 | 1979-12-11 | Signetics Corporation | Three state bus driver with protection circuitry |
| GB2034996B (en) * | 1978-10-20 | 1982-12-08 | Philips Electronic Associated | Voltage clamping circuit |
| US4275313A (en) * | 1979-04-09 | 1981-06-23 | Bell Telephone Laboratories, Incorporated | Current limiting output circuit with output feedback |
| US4347447A (en) * | 1981-04-16 | 1982-08-31 | Mostek Corporation | Current limiting MOS transistor driver circuit |
-
1983
- 1983-12-12 WO PCT/US1983/001966 patent/WO1984003181A1/en not_active Ceased
- 1983-12-12 EP EP19840900356 patent/EP0141819A4/en not_active Withdrawn
- 1983-12-12 JP JP84500457A patent/JPS60500437A/en active Pending
- 1983-12-16 CA CA000443506A patent/CA1191560A/en not_active Expired
-
1984
- 1984-01-12 IT IT47534/84A patent/IT1178355B/en active
- 1984-02-04 KR KR1019840000525A patent/KR900001812B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| IT8447534A0 (en) | 1984-01-12 |
| KR840008098A (en) | 1984-12-12 |
| JPS60500437A (en) | 1985-03-28 |
| KR900001812B1 (en) | 1990-03-24 |
| EP0141819A1 (en) | 1985-05-22 |
| WO1984003181A1 (en) | 1984-08-16 |
| EP0141819A4 (en) | 1986-06-05 |
| IT8447534A1 (en) | 1985-07-12 |
| IT1178355B (en) | 1987-09-09 |
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