CA1144274A

CA1144274A - Transmission method and system for facsimile signal

Info

Publication number: CA1144274A
Application number: CA000400498A
Authority: CA
Inventors: Kiyohiro Yuuki; Yasushi Wakahara; Yasuhiro Yamazaki; Toyomichi Yamada
Original assignee: Kokusai Denshin Denwa KK; Nippon Telegraph and Telephone Corp
Current assignee: KDDI Corp; NTT Inc
Priority date: 1978-07-31
Filing date: 1982-04-05
Publication date: 1983-04-05

Abstract

S P E C I F I C A T I O N

TRANSMISSION METHOD AND SYSTEM FOR FACSIMILE SIGNAL

ABSTRACT OF THE DISCLOSURE
A transmission method for a facsimile signal by the use of the two-dimensional coding principle, in which when succes-sively coding addresses of a facsimile signal representative of the positions of information change picture elements, each having a binary value different from that of an immediately preceding picture element, the above-mentioned addresses on each coding scanning line are classified into three modes that are determined by the states of information change picture elements on the coding scanning line and on a reference scan-ning line immediately preceding the coding scanning line.
The above two-dimensional coding principle and a one-dimensional coding principle may be adaptively adopted to shorten the trans-mission time and to lessen the influence of a transmission error.

Description

i44Z74 This invention relates to a transmission method for efficient transmission of a binary signal, such as a two level facsimile signal.
Heretofore, there have been proposed, as a two-level facsi-mile signal coding system, (l) a run-length coding system in which a signal obtained by scanning is converted into a time series train and then the magnitudes of the run lengths of white and black are successively coded alternately with each other for transmission and (2) a system in which signals of plural, for example, two scanning lines are simultaneously coded all together.
The system (1) does not utilize at all the property that facsi-mile signals have a high correlation in a direction perpendicular (vertical) to the sc~nning line direction ; therefore, the compression efficiency is low. T~e system (2) makes use of the correlation in the vertical direction with respect to the signals of a set of scanning lines to be coded at a time~but does not utilize the correlation to signals of this system other scanning lines ; consequently, the compression efficiency is higher than that of the system (1) but no sufficient compression effect is achieved, since this system does not fully use the two dimen-sional correlation among adjacent scanning lines.
An object of this invention is to overcome such defects of the prior art systems and to provide a transmission method using a two-dimensional successive coding system which removes redun-dancy of a facsimile signal by a relatively small numher ofmemories and a simple circuit or means to thereby permit a sub-stantial reduction of the number of bits to be sent out.
~ nother object of this invention is to provide a transmis-sion method using a one-dimensional, two dimensional adaptive ~44~74 coding method in which the ~wo-dimensional successive coding principle and the one-dimensional coding principle, such as a run-length coding system, are adaptively adopted, 80 that the amount of information or signals to be transmitted is reduced, thereby to shorten the tr~nsmission time and to lessen the influence of a transmission error.
Further object of this invention is to provide a decoding system suitable for decoding a facsimile signal coded by the above mentioned coding method.
The present invention relating to the first object is based on the principle that when successively coding information (hereinafter referred to as addresses) of a facsimile signal xepresentative of the positions of information change picture elements ~hereinafter referred to simply as change picture ele-ments), each having a binary signal value different from that of an immediately preceding picture element, the-number of pic-ture elements ~hereina~ter referred to as the distance) between each change picture element to be coded and a selected one of the adjoining change picture elements on the same scanning line (hereinafter referred to as a coding line) as the change picture element to be coded or on a scanning line immediately preceding it ~which scanning line will hereinafter be referred to as a reierence line) is employed to be classified into three modes determined by the combinations of states of the above infor-mation change picture elements.
The present in~ention relating to the second object isbased on the principle that in the coding of a digital facsimile signal, picture signal information of, each line is coded by the one-dimensional system (for example, a run-length coding system) and the two-dimensional system and, for each line, the two coded signals are compared with each other, for example, in the number of coded bits and a favorable one of them is selected as a coded output. Let [one-dimensional]
and ltwo-dimensional] represent the numbers of coded bits obtained by coding a coding line by the one-dimensional and the two-dimensional coding system, respectively. When [one-dimensional] > [two-dimensional], the two-dimensional coding is used as a result of a judgement that the amount of information by the one-dimensional coding is larger than that by the two-dimensional coding, whereas when [one-dimensional] _ [two-dimensional], the one-dimensional cod-ing is employed for the line to be coded as a result of a judgement that the amount of information by the one-dimensional coding is smaller than that by the two-dimensional coding.
In accordance with the present invention, there is provided a transmission system for facsimile signal for decoding a coded facsimile sig-nal developed so that the positions of information change picture elements included in a two level facsimile signal, which is obtained by scanning an original picture and successively sampling the scanning output into picture elements, are coded, the improvement of the system comprising: first circuit for storing information of a scanning line to be coded; second circuit for storing information of a reference line just decoded; third circuit for con-trolling addresses of said first circuit; fourth circuit for controlling ad-dresses of said second circuit; fifth circuit for setting a starting picture element on a decoding scanning line from which the decoding starts; sixth circuit for detecting first, second and third mode codes from the coded facsimile signal; seventh circuit for detecting a first reference picture element which is a first information change picture element positioned after a picture element just above the starting picture element on the reference scanning line and having a signal value different from that of the starting picture element; eighth circuit for detecting a second reference picture ele-ment which is an information change picture element just succeeding to the first reference picture element; ninth circu;t for decoding a code indica-tive of a relative distance between the first reference picture element and an information change picture element just succeeding to the starting picture element on the decoding line when the third mode code is detected; and tenth circuit for decoding a code indicative of a relative distance between the starting picture element and an information change picture element just suc-ceeding to the starting picture element on the decoding line when the second mode code is detected.
This invention will be described in details hereinafter with reference to the accompanying drawings, in which:
Figures 1, 2, 3A, 3B, 6, 7, 8A, 8B, 8C, ll and 16 show examples of facsimile signals, explanatory of the principles of this invention;
Figure 4A illustrates in block form an embodiment of this inven-tion;
Figures 4B, 4C and 4D illustrate in block form specific operative examples of circuits for use in the embodiment of Figure 4A;
Figure 5A shows in block form an example of a decoding device for a facsimile signal encoded by the embodiment of Figure 4A;
Figures 5B, 5C and 5D show in block form specific operative ex-amples of circuits for use in the decoding device of Figure 5A;
Figure 9 shows in block form another embodiment of this ~lg4'~74 inventioi- ;
Fig. lOA illustrates in block form an eY~ample of a de-coding device for a facsimile signal encoded by the embodiment of Fig. 9 ;
Fig. los illustrates in block form a specific operative example of a circuit for use in the decoding device of Fig. lOA;
Fig. 12 shows in block form another embodiment of this invention ;
Fig. 13 shows in bloc]~ form an example of a decoding device for a facsimile signal encoded by the embodiment of Fig. 12 ;
~ i~s. 14 and 17 axe bloc~ diagrams each illilstrating-another emhodiment -^f this invention ; and Fig. 15 is a block diagram illustrating an example of a decoding device for a facsimile signal encoded by the embodiment of Fig. 14.
A detailed description will be given of specific operative examples of this invention.
Figs. 1, 2, 3A and 3~ illustrate examples of facsimile sig-nals, blank blocks representing white picture elements and hatched blocks black picture elements.
At first, a coding start picture element aO and other change picture elements are defined as follows :
aO : a starting picture element on the coding line Lc with which the coding starts along the scanning direction SD ;
a~ : a change picture element next to aO on the coding line ;
b~ : a first change picture element on the reference line Lr occurring af-ter the picture element just above aO and having a binary signal value difEerent from that of aO ;

~44274 b2 : a change picture element next to b, on the refer-ence line.
As will hereinbelow be described, the picture elements on the coding line and the reference line are successively collat-ed with each other to detect the change picture elements onthe both scanning lines for coding.
(Procedure 1) : In a case where the two change picture ele-ments bl and b2 on the reference line are detected prior to the change picture element al on the coding line (refer to Fig. 2), thi~s state is recoqnized as "a Pass mode" and the chanqe picture elements bl and b2 are coded with a Pass mode code, for example, "1110" (refer to the column of the Pass mode in Table 1), by which a startinq picture element for the next coding is set at a picture element a'0 on the coding line just under the picture element b2, (Procedure 2) : In a case where the change picture element al is detected on the coding line prior to the change picture element bl on the reference line (refer to Figs. 3A and 3B), scanning of the picture elements proceeds until the change pic-ture element bl occurs and the number of coded bits ~aOal] isobtained by adding the coded bits of a distance aOal to the bits OI a Horizontal mode code "llll". At the same time, the number of coded bits [bla,] for coding a distance bla~ as a Vertical mode is obtained ~refer to Table l).

1~4~274 Table l __ Mode to be coded Code _,_ Pass mode blb2 1110 _ Horizontal mode aOal 1111 + MH(aOal) b1al = 0 blal = ~-1 100 Vertical mode blal = -l lOl blal _ 2 llO0 + D(blal - l) blal < -2 llOl + D(¦blal¦ -l) .
lO xy xy: white MH (xy) n D(n) . _ _

2 0111 11 3 001

3 1000 lO 4 0001 15 4 ; 011 5 00001 In the column of the "Vertical mode" in Table 1, "-"
indicates the case o. the picture element al being detected before the picture element bl and "+" the case of the picture element a~ being detected after the picture element bl. These coded bit numbers are compared with each other to select any one of coding modes in accordance with the following conditions:
. a) [aDal] > [blal]

In a case where this condition is established, it is judged that a high correlation exists between the chanqe Picture ele-ment al to be coded and the reference Picture element bl and - 7 ~

1~44274 the distance b~al is selected as the ~ertical mode to shift a new starting picture element to the position of the picture element a~.
For example, in the case of Fig. 3A, [b~al] = "110101" =
6 bits and [aOal] = "11111000" = 8 bits ; consequently, the condition [aOal] _ [blal] is established. Then, the picture element a, is encoded by a ~ertical mcde so that the coded signal "110101" is aenerated.
b) [aOal] _ [b~al]
When this condition is set up, it is judged that a high correlation exists between the ~hange picture element a~ to be coded and the starting picture element aO and coding of the distance aOal is achieved following the Horizontal mode code "1111", shifting a new starting picture element to the position of the picture element al.
For example, in the case ~f Fig. 3B, [blal~ = -6 =
"110100001" = 9 bits and [aOal] = "11111000" = 8 bits ; con-sequently, the condition [aOal] _ [blal] is established and the coded output of the picture element al becomes "11111000".
In the above description, the expressions (a) and (b) are mentioned as the conditions for selecting either the Horizontal mode or the Vertical mode but other conditional expressions can be used, such as follows :
(a) : [aOa~] > [blal] ~ m (m beina an integer) (b) : [aOal] ~ [blal] + m (m being an integer) Alternatively, if use is made of the distances aOal and bla before coding, (a) : aOal > blal + m (m being an integer) (b) : aOa~ < blal ~ m (m being an inte~er) 114~;~74 Moreover, in the column of codes in Table l, a MH code (a modified Huffmann code, for particulars, refer to CCITT
Recommendation To 4) and a bit-by-bit code D(n) are used ;
but it is a mat~ter of course that the present invention is not limited specifically to the use of such codes and can be achiev-ed with ordinary variable length codes.
Besides, in the procedure l, it is condi~ioned that the change picture elements just above the picture elements aO and al are not regarded as bl and b2 ; but the condition can be modified such that the change picture element just above the picture element aO or a~ is included in bl and b2, or that the change picture elements are not regarded as bl and b2 unless they are not spaced more than n (_ being 0 or a positive in-teger) picture elements apart from the picture elements aO and a~.
As described in detail above, in the present invention, addresses of change picture elements to be coded are succes-sively coded and, in this case, the addresses are each coded using a relative distance between the change picture element to be coded and a selected one of the change picture elements already coded.
A brief description will be made of an example of boundary conditions which are utilized when this invention is reduced into practice, althou~h it does not define the essence of the invention.
(1) Coding of a starting picture element on each scanning line :
A change picture element from white to black is always used as a first change picture element on each line to be coded.

Accordingly, in ~ case of the first picture element being black, it is made the first change picture element or the first picture element is compulsorily made white.
Further, the first starting picture element aO on each coding line is set up at the position of the first picture element.
(2) Coding of a terminating picture element on each scan-ning line :
The terminating picture element (in CCITT Recommend-ation T. 4, one line consists of 1728 picture elements) ofeach line is coded on the assumption that a change picture element lies ne~t to it.
The following will describe examples of circuits for carrying this invention into practice in accordance with the principles described above.
Fig. 4A illustrates an example of a coding device.
Reference numeral 1 indicates an input terminal for a sampled t~o-level facsimile signal ; 2 and 3 designate line memories, each storing signals of one line ; 4 identifies a memory for storing the level of starting picture element aO ; 5 denotes an address control circuit for controlling addresses of memories 2 and 3 and for generating an end of line signal EOL ; 6 re-presents an exclusive OR circuit ; 11 and 12 show change picture element detectors, each composed of a l-bit memory 420 and an exclusive OR circuit 421, as shown in Fig. 4B ; 21, 23 and 24 refer to detectors for detecting the change picture elements a~, bl and b2, respectively ; 25 indicates a bla~ direction detector ; 32 and 33 designate counters ; 40 identifies a pass mode detector ; 52, 53 and 54 denote coders ; 60 represents a ~4~274 - comparator for comparing the numbers of coded bits with each other ; 71, 72, 74 and 75 show gates ; 81, 82 and 84 refer to address registers, each formed by a counter ; 90 indicates a signal combiner ; and lO0 identifies an output terminal.
For the sake of brevity, a memory shift pulse generator, a counter clock pulse generator, etc. are not shown ; but these do not exert influence on an understanding of the essence of the operation of the present invention.
Next, the construction and operation of this embodiment will be described in detail. A facsimile signal to be coded is provided from the input terminal 1 to the coding line memory 2 for storage therein. Before this time, as a signal of a reference line, a signal o~ the preceding line stored in the line memory 2 is transferred to the reference line memory 3 for storage therein. The aO memory 4 has stored therein level of the starting picture element aO, as will be described later on.
Reading of the coding line memory 2 and the reference line memory 3 simultaneously starts from the position of the start-ing picture element aO under the control of the address control circuit 5. The change picture element detector ll compares a picture element signal read out of the line memory 2 with an immediately preceding picture element signal, successively, and as a result it generates an output "0" or "l" in dependence on whether the former signal is of the same level as the latter signal or not. The change picture element detector 12 detects change picture elements on the line memory 3 successively by the same manner as the dete~tor ll. The b, detector 23 is an AN~ circuit which provides "1" on an output line blp when a change plcture element is detected by the change picture element 11~4Z74 detector 12 and the detected change picture element level differs from that of the s~arting picture element a0, that is, when the output from the exclusive OR circuit 6 is "1". The b2 detector 24 provides "1l' on an output line b2p in a case where a change picture element is detected by the change picture element detector 12 after detection of the change picture ele-ment bl by the b~ detector 23 ; this bl detector 24 can be made up of one flip~flop and an AND circuit. The Pass mode detector 40 is an AND circuit which provides "1'l on an output line p, judging that the mode of operation is the Pass mode in a case where the picture element al has not been detected at the moment of occurrence of l'l" on the output line b2p (in this case, aln which is the output Q of a flip-flop in the al detec-tor 21 is l'l"), as will be described later. With "1" on the output line ~, the Pass mode coding circuit 54 yields a Pass mode code "1110", which is appliPd to the signal combiner 90.
Following this, a new starting picture element aO is shifted to the position just below the picture element b2 in the follow-ing manner : Upon occurrence of "1" on the line b2p, the b2 .address register 81 stops counting of pulses from the address control circuit 5 and stores this status. This information is applied via the gate 74 to the aO address register 84 for addition to its content when the Pass mode detector 40 produces "1" on the line p. sesides, the a~ address register 82 stops counting of pulses from the address control circuit 5 upon occurrence of "1" on the line alp and this information is pro-vided via the gate 75 to the a0 address register 84 for addi-tion to its content when the comparator 60 produces "1" on a line V or h. The contents of the aO address register 84 are ' :

1~442~4 applied to the address control circuit 5 to re-start the cod-ing operation with the new starting picture element. The ad-dress control circuit 5 has such a construction as shown in Fig. 4D, which stores the contents of the a0 address register 84 in a register of a memory drive circuit 430 and increases a memory read-out address one by one upon each occurrence of a pulse from a pulse generator 431 to read information of the line memories 2 and 3 simultaneously bit by bit from the aO
address in the register of the memory drive circuit 43~.
Further, upon each reception of the contents of the aO address register 84, the address control circuit applies the new start-ing picture element level to the a0 memory 4 via the coding line memory 2. The contents of the memory drive circuit 430 arè compared in a comparator 432 with contents of an address memory 433 of the end picture element of one line to generate an end of line signal EOL.
The first change picture element detector 11, when detect-ing a change picture element, provides an output "l" to the al detector 21 (a flip-flop). As a result of this, the information on the lines alp and aln change from "0" to "l" and from "l"
to "0", respectively. The a0al counter 32 starts counting of pulses from the moment of setting aO in the address control circuit 5, and stops the counting upon reception of "1" from the line alp and provides the count value to the aOa~ coding circuit 52. The a0a, coding circuit 52 encodes the count value with "1111" added to its head, using a code table such as shown in the column of the Horizontal mode of Table 1. The blal counter 33 receives the outputs from the lines blp and al so that it starts pulse counting with a first appearing "1"

114~'~4 in either one of th~ lines bl and al and stops the counting with a next appearing "1" in the other. To the bla, direction de~ector 25 are also supplied the outputs from the lines blp and alp and, with the circuit construction shown in Fig. 4C, comprising the AND circuits 423 and 424 and two flip-flop circuits 425 and 426, this detector outputs "1" on a line +
when "1" of the line blp appears earlier than or simultaneously with "1" of the line al but, in the opposite case, provides an output "1" on a line -.
The bla~ coding circuit 53 encodes b~a~ with a sign + or - added thereto on the basis of the count value of the bla counter 33 and the output of the line + or - from the blal direction detector 25, as shown in the column of the Vertical mode of Table 1. The bit numbers encoded by the coding circuits 52 and 53 are compared in magnitude with each other in the comparator 60 ; when the condition [aOa~] _ [b~a~] is establish-ed, "1" is provided on the line V (the Vertical mode), whereas when this condition is not established, "1" is provided on the line h (~orizontal ~lode). In a case of the Vertical mode in which "1" is outputted on the line V of the comparator 60, the coded signal of the blal coding circuit 53 is provided via the gate 71 to the slgnal combiner 90. On the other hand, in the Hori~ontal mode in which "1" is yielded on the line h, the gate 72 is opened to apply therethrough the coded signal of the a0al coding circuit 52 to the signal combiner 90. The sig-nal combiner 90 combines the coded signals applied thereto from the Pass mode coding circuit 54 and the gates 71 and 72 into a composite signal, which is provided on the output line 100 after being converted into an output signal train.

1144;~74 For the sake of brevity, the conditions for resetting the detectors, registers, counters and so forth are neither described in the foregoing nor shown in the drawings ; but, required ones of these circuits (the b2 detector 24, the al S detector 21, the registers 81 and 82, the bla~ direction detec-tor 25j the counters 32 and 33 and so forth) are reset for each setting of the picture element a0.
-; The interruption of the operation of this coding device is placed under the control of the address control circuit 5.
Namely, the aO address is always watched by the address con-trol circuit 5, the coding is stopped at the moment when the aO address bPcomes a line terminating picture élement and the a0 address is newly set to a line starting picture element and then coding of the subsequent line is resumed.
The above is the operation of the coding device of Fig.
4A and decoding is achieved by reversing the abovesaid steps.
An example of a decoding device is shown in Fig. 5A. Reference numeral 201 indicates an input terminal ; 202 designates an input buffer memory ; 203 identifies a mode code identify cir-cuit ; 211 and 212 denote line memories ; 213 represents an a0 memory ; 221 and 222 show address control circuits ; 231 and 232 refer to decoding circuits ; 240 indicates a change pic-ture element detector ; 251 and 252 designate a b~ detector and a b2 detector, respectively ; 261 and 262 identify an adder and a subtractor, respectively ; 271 and 272 denote counters ; 281 to 285 represent gates ; 291, 292 and 294 show OR circuits ; 293 refers to an exclusive OR circuit ; 300 indi-cates an aO register ; and 310 designates an output terminal.
The following will describe the construction and the ~144*74 operatio~ o~ the decoding device of Fig. 5A in detail. A
coded signal from the input terminal 201 is once stored in the input ~uffer memory 202. The mode code identify circuit 203 has su~h a construction as shown in Fig. SB, comprising resistors 441, 442, 44~, 444, 445, ~46 and 447 and coincidence cir~ui~s 451, 452, 453 and 454, in which a signal (four bits at ~ost, as shown in Table 1) necessary for mode identifica-tio~ is read out of the input buffer memory 202 to identify the ~odes of operation~ i.e. the Pass mode, the Horizontal m~de ~nd the Vertical mode. When the signal is "1110", it is re~arded as indicating the Pass mode and "l" is outputted on a line ~ ; when the signal is "llll", it is re~arded as indi-cating the Horizontal mode and n 1~' iS provided on a line h ;
when the signal is IIOJI, ~10O~ or "1100", it is regarded as indicating that the direction of the distance blal is plus in th~ Vertical mode and "1" is produced on a line V+ ; and when the signal is "101" or "1101", it is regarded as indicating that th~ direction of the distance blal is minus in the Verti-; cal mo~e and "1" is yielded on a line V-. The address control circui~ 221 has such a construction as depi~ted in Fig. 5C, in ~i~h when any one of the outputs ~, V- and V~ from the mode co~e i~entify circuit is "1", pulses are applied to the memory 211 t~ shift it bit by bit from the a~ address provided from S~ -Whe~ the identify circuit 203 proviees "1" on the line ~he ~ass mode), the address control circuit 221 reads the reference line memory 211 from the address of the picture ele-ment aD to start detection of the distance blb2. The reference ~144~74 line memory has stored therein information of the previous line via the coding line memory 212.
The change picture element detector 240 has the const-ruction shown in Fig. 4B and provides an 0l1tpUt "1" upon each S detection of a picture element, whose level is dif'ferent from the immediately preceding one in the signal train applied from the line memory 211. At the moment when the change picture element detector 240 provides the output "1", if the detected picture element is differer.t in level from the picture element aO, the output "1l' is applied via the exclusive OR circuit 293 to the bl detector (an AND circuit) 251 to produce an output "1" on a line b1p. The a3b~ counter 272 receives pulses from the address control circuit 221 and counts the number of pulses occurring in the time interval from the aO address to bl (until "1" is provided on the line b1p). The b2 detector 252 outputs "1" on a line b2p when another change picture element is detec-ted by the change picture element de~ector 240 after detection of the picture element bl. This bl detector comprises a flip-flop and an AND circuit. The aOb2 counter 271 receives pulses from the address control circuit 221 and counts them occurring in the time interval from the aO address to b2 (until "1" is provided on the line b2p). The contents of the aOb2 counter 271 are applied to the aO register 300 via the gate 281, which is opened by the provision of the output "1" on the line 2 of the mode code identify circuit 203. The contents of the aO
reg-ister 300 are added to the address control circuits 221 and 222, so that the aO address is newly set and the decoding operation is resumed.
In a case where the identify circuit 203 provides "1" on 1:~44~74 the line ~ or V- (Vertical mode~, the output "1" from the ~R
circuit 291 is applied to the address control circuit 221 and th~ b~a~ Z~coding circuit 231. As a consequence, decoding rel~ting to the abovesaid bl takes place and the count value oS t~ aD~ counter 272 indicates the address of the picture e~e~* ~I relative to the picture element aO. The blal de-r~ding CiICUit 231 reads signals of one word from the input ~uffer ~e~y 202 and decodes them. The decoded value is added by the ad~er 261 to the value of the aOb~ counter 272 and, at th~ s~2e ~ti~e, subtracted by the subtractor 262 from the value of the z~ counter 272. In a case where the output line V+
o~ the mode code identify circuit 203 is "1", the gate 284 is opene~, so that the information of the adder 261 is provided via ~he ~R circuit 292 to the addxess control circuit 222 and to t~ ~0 register 300 via the gate 282. In contrast thereto, if ~he output line V- of the mode code identify circuit 203 is ~ the gate 285 is opened, passing on the information of thP su~ractor 262 to the address control circuit 222 via the O~ circuit 292 and to the aO register 300 via the gate 282.
.20 T~e a~dress control circuit 222 has such a construction as d~ict~d in Fig. 5D, which sets up the address of the picture ele~e~t ~3 on the basis of the information transmitted thereto Yia the ~ circuit 292, reproduces the picture element signals ~r; t~e ~oding line as the sarne level as the picture element aO
~-~o~ ih~ picture element a~ to a picture element imrnediately preceding al, and inverts the level of the picture element a~
relative to the information of the picture element aO. The conte~ts OI the aO register 300 are applied to the address control circuits 221 and 222, newly settir.g the address of the picture element aO and resumin~ decoding.
In a case where the line h of the mode code identify cir-cuit 203 becom~s "1" `(Horizontal mode), the aOal decoding cir-cuit 232 reads signals of one word from the input buffer memory 5 202 and decodes them. The decoded value is added to the address control circuit 222 and the aO register 300 via the gate 283.
The address control circuit 222 sets up the address of the picture element al, reproduces th~ picture element signal on the coding line as the same level as the picture element aO
10 from the picture element aO to a picture element immediately preceding a~, and makes the level of the picture element al to be dif~erent ~rom the level of the picture element aO. The aO
address register 300 restores the address of the picture ele-ment al, so that the al address becomes a new aO address.
15 This new address is provided to the address control circuits 221 and 222 to set the aq address and re-start decodiny.
Also in respect of the above decodlng device, the reset-ting conditions for the detectors, the registers, the counters and so forth have been neither described nor shown in the 20 drawings; but the mode code identify circuit 203, the b2 detector 252, the address control circuits 221 and 222, the counters 271 and ~72, the s~ecoding circuits 231 and 232, etc.
are reset for each new setting of the aO address. The termi-nation of one line is achieved by supervising the aO address 25 with the address con~rol circuit 222 and at the moment of the address of the picture element becoming the address of the last picture element of a scanning line, decoding of that line is completed and decoding of the next line is resumed.
In the above embodiment, when the Horizontal mode is 11~4'~74 identified, a distance between the startinq picture element and the codi~g change point is encoded and the code "1111"
indicating the Hori~ontal mode is added to the encoded value.
~ol further enhancement of the compression efficiency, however, S i~ ;s oonsidered that in the case of the Horizontal mode being i~enti~ied, the following change picture elements are encoded toge~ner aad added with one Horizontal mode code "1111".
~ha$ i5, one Hori~ontal mode code is shared by two change pic-ture e~me~ts ; consequently, the compression efficiency is i~prD~ed. This will hereinbelow be describe in detail.
~ ig. 6 illustrates examples of facsimile signals, blank blocks r~resenting white picture elements and hatched blocks bl~c~ pi~ture elements. At first, a coding start picture ele-ment a~ and other change picture elements are defined as folls~s :
a~ : a starting picture element on the coding line with whi~ the coding starts ;
al : a change picture element next to aO on the coding line ;
a2 . a chang~ picture element next to a~ on the coding line ;
bl : a first change picture element on the reference line ~c~uIri~g after the picture element just above aO and having a ~ signal value different from that of aQ ;
b2 : a change picture element next 'LO h~ on the refer-~ce line.
As will hereinbelow be described, the picture elements on ~he coding line and the reference line are successively collated with each other to detect the change picture elements 114~274 on the both scan lines for coding~
(Procedure l) : In a case where the two change picture elements b1 and b2 on the reference line are detected prior to the change picture element al on the coding line (refer to Fig 7), this state is recognized as a Pass mode and the change picture elements bl and b2 are coded with a Pass mode code, for example, "1110" (refer to the colun~ of the Pass mode in Table 2), by which a starting picture element for the next coding is set at a picture element a'0 on the coding line just under the picture element b2.
(Procedure 2) : In a case where the change picture ele-ment al is detected on the coding line prior to the change picture element bl on the reference line (refer to Figs. 8A, 8B), scanning of the picture elements proceeds until the change picture element bl occurs and the number of coded bits [aOal]
is obtained by adding the coded bits of a distance aOal to the bits of a Horizontal mode code "1111". At the same time, the number of coded bits [blal] for coding a distance b~al as a Vertical mode is obtained (refer to Table 2) Table 2 Mode Elements to be Code Pass mode blb2 lllO
Horizontal mode aOal, ala2 llll + ~I(aOal) + MH(ala2) blal = O O
blal = +1 lO0 Vertical mode blal = -1 101 blal _ 2 1100 + D(blal - l) blal < -2 1101 + D(¦bla 1~44~74 .
xy xy : ~7hite ~ xy . black n O ~ 101 0000110111 i 1 l J~ OODlll ¦ 010 2 01 2 ~ ll 3 001 3 ~ lO 1 4 0001 o~l The signs ~-~ and "+" are the sarne as in Table l. These coded bit n~bers are compared to select any one of coding modes in acc~rdance ^7ith the following conditions :
a~ ~a~al] > [bla,]
~hen this condition is established, it is judged that a high coxrelation e~ists between the change picture element al to be coded and the reference picture element bl, and the value of the distance bla~ coded in the Vertical mode is selected to shift a new starting picture element to the position of the picture element a~
For e~a~ple, in the case of Fig. 8A, [blal] = "110101" =
6 bits and laOal] = "11111000" = 8 bits ; consequen-tly, the c~n~iti~n ~aOal] ~ [blal] is established. Then the picture el~ent al is encoded by a Vertical mode so that the coded sig-nal "ll~101" is generated.
b~ [aOalJ c [blal]
~en this condition is set up, it is judged that a high ccrrelation exists between the change picture element a~ to be coded and the starting picture element aO, and ;t is decided to perfo~ coding in the Horizontal mode until a change picture element a2 ap~ears after al ; thus, collation proceeds until 1~44Z74 the change picture element a2 occ~lrs and code generation of the distances a~a, and ala2 is achieved following the gener-ation of Hori~ontal mode code, for example, "1111", thereby shifting a new starting picture element to the position of the picture element a2.
For exa~nple, in the case of Fig. 8B, [b~al] = -6 =
"110100001" = 9 bits and [aOal] = "11111000" -- 8 bits ; con-sequently, the condition [aOal] < [blall is established and the coded outputs of the pi.cture elemen~s al and a2 become 10 "11111000" and "011".
In the above description, the expressions (a) and (b) are mentioned as the conditions for selecting either the Horizontal mode or the Vertical mode but other conditional expressions can be u6ed, such as follows :
(a) : [aOal] > lblal~ + m (m being an integer) (b) : [acal] _ [blal] + m (m being an integer) Alternatively, if use is made ~f the distances aOal and bla before coding, (a) : aOal > blal + m (m being an integer) (b) : aOal _ blal + m (m being an integer) Moreover, in the column of codes in Table 2, a l~H code (a modified Huffmann code, for particulars, refer to CCITT
Recommendation T.4) and a bit-by-bit code D(n) are used ; but it is a matter of course that the present invention is not limited specifically to the use of such codes and can be achieved with ordinary variable length codes.
Besides, in the procedure 1, it is conditioned tha-t the change picture elements just above ~he picture elements aO and a~ are not regarded as bl and b2 i but the condition can be ~44~74 modified such that the change picture element just above the picture element aO or a, is included in bl and b2, or that the change picture elements are not regarded as bl and b2 unless they are not spaced more than n (1~ being 0 or a positive in-teger~ picture elements apart from the picture elements aO anda~.
As described in detail above, in the present invention, addresses of change picture elements to be coded are succes-sively coded and, in this case, the addresses are each coded usin~ a relative distance between the change picture element to be coded and a selected one of the change picture elements al-ready coded. Where this selected change picture element is the starting picture element aO on the coding line, the address of the next change picture element a2 to be coded is also coded using the relatlve di.stance between it and the picture element a~. As a consequence, the change picture elements whose ad-dresses are coded using the distances between them and the starting picture elements on the coding line, are always in pairs. In a case of using the relative distance between change picture elements to be coded and a change picture element on the immediately preceding reference line, the change picture elements on the coding line are coded individually.
A brief description will be made of an example of boundary conditions which are utilized when this invention is reduced into practice, al-through it does not define the essence of the invention.
(l) Coding of a starting picture element on each scan-ning line :
change picture element from white to black is always - ~4 -1~44~4 used as a first change picture element on each line to be coded. Accordingly, in a case of the first picture element being black, it is made the first change pictuxe element or the first picture element is compulsorily made white.
S Further, the first starting picture element aO on each coding line is set up at the position of the first picture - element.
(2) Coding of a terminating picture element on each scan-ning line :
The terminating picture element (In CCITT Recommendation To 4. one line consists of 1728 picture elements ; accordingly, the terminating picture element is the 1728th picture element.) of each line is coded on the assumption that a change picture element lies next to it.
The following will describe examples of circuits for carry-ing this invention into practice in accordance with the princi-ples described above.
Fig. 9 illustrates an examPle of a codinq device. Refer-ence numeral 1 indicates an input terminal for a sampled two-level facsimile signal ; 2 and 3 designate line memories, each storing signals of one line ; 4 identifies a memory for stor-ing the level of starting picture element aO ; 5 denotes an address control circuit for controlling addresses of memories 2 and 3 ; 6 represents an exclusive OR circuit ; 11 and 12 show change picture element detectors, each composed of a l-bit memory and an exclusive OR circuit, as shown in Fig. 4B ; 21, 22, 23 and 24 refer to detectors for detecting the change picture elements al~ a2~ b~ and b2, respectively ; 25 indicates a b~a~ direction detector ; 31, 32 and 33 designate counters ;

1;~4~*~4 40 identifies a Pass mode detec~or ; Sl, 52, 53 and 54 denote coders ; 50 represents a compaxator for comparinq the numbers of coded bits with each other ; 71, 72, 73, 74, 75 and 76 show qates ; 81~ 82, 83 and 84 refer to address registers ; 90 indi-cates a signal com~iner ; ~nd 100 identifies an output termi-nal. For the sake of brevity, a memory shift pulse generator, a counter cloc~ pulse generator~ etc. are not shown ; but these do no~ exert inflJence on an understanding of the essence of the operation of the present invention.
Next, the construction and operation of this embodiment will be described in detail A facsimile signal to be coded is provided from the input terminal 1 to the coding line memory 2 for storage therein. Before this time, as a signal of a reference line, a signal of the preceding line stored in the lS line memory 2 is transferred to the reference line memory 3 for storage therein. The a0 memory 4 has stored therein level of the starting picture element aO, as will be described later on.
Reading of the coding line memory 2 and the reference llne memory 3 simultaneously starts from the position of the starting picture element aO under the control of the address control circuit 5. The change picture element detectors 11 and 12 each comprise an exclusive OR circuit and a l-bit memory, as shown in Fig. 4B, and compare the picture element signals read out of the each line memories 2 and 3 with immediately preceding picture element signals to output "0" or "1" in dependence on whether the former signals are of the same level as the latter signals or not, respecti~ely. The bl detector 23 is an ~ND
circuit which provides "1" on an output line bl when a change picture element is detected by the second change picture element 1~44Z74 detector 12 and the detecte~' chang2 pi.cture elemen-t level differs from that of the starting picture element aO, that is, when the output from the e~clusive OR ci.rcuit 6 is "1". The b2 detector 24 provides "1" on an Olltput llne b2 in a case where a change picture elemen-t is detected by the change pic-ture element d2tectcr 12 after detec-tion of the change picture element bl by the bl detector 23 ; this b2 detector 24 can be made up of one flip-flop and an AND circui.t. The Pass mode detector 40 is an AND circuit which provides "1" on an output lG line p, judging that the mode of operation is the Pass mode in a case where the picture element al ha~ not been detected at the moment of occurrence of "1" on the output line b2 (in this case, aln which is the output Q of a flip-flop in the al detector 21 is "1"), as ~ill be described later. With "1" on the output line _, the Pass mode coding circuit 54 yields a Pass mode code "1110", which is applied to the signal combiner 90. Following this, a new starting picture element (ac) is shifted to the position just under the picture element b2 in the following manner : Upon occurrence of "1" on the line blp, the b2 address register 81 stops counting of pulses from the address control circuit 5 and stores the count value.
These contents are applied via the gate 74 to the aO address register 84 when the Pass mode detector 40 produces "1" on the line ~. The contents o~ the aO address register 84 are applied to the address control circuit 5 to re-start the coding oper-ation with the new starting picture element.
The first change picture element detector 11, when detect-ing - change picture element~ provides an output "1" to the a, detector 21 (a flip-flop). As a result of this, the information on the llnes alp and aln change from "0" to "1" and from "1"
to "0", respeclivley. The a2 detector 22 is a flip-flop which produces lll" on a line a2 when a change picture element is detected by the change picture element detector 11 after the picture element a; is detected by the al detector 21 ("1" on the line alp) The aOal counter 32 starts counting of pulses from the ~om~nt of setting aO in the address control circuit 5, and stops the counting upon reception of "1" from the line alp and provides the count value to the aOal coding circuit 52. The aOa~ coding circuit encodes the count value with "1111" added to its head, using, for example, such a code table as shoY~ in the column of the Horizontal mode of Table 1. The ala2 counter 31 starts counting with "1" on the line alp and stops the counting with "1" on the line a2p and provides the count value to the a,a2 coding circuit Sl.
The ala2 coding circuit 51 encodes the count value using such a code table, for example, as shown in the column MH(xy) of Table 2. The b~al counter 33 receives the outputs from the lines blp and alp so that it starts pulse counting with a first appearing "1" in either one of the outputs blp and alp and stops the counting with a next appearing "1" in the other. To the b~a, direction detector 25 are also applied the outputs from the lines blp and alp and, with the circuit construction shown in Fig. 4C, this detector outputs "1" on a line + when "1" of the line blp appears earlier than or simultaneously with "1" of the line alp but, in the opposite case, provides an output "1" on a line -.
The b~al coding circuit 53 encodes bla~ with a sign ~ or - added thereto on the basis of the COUIlt value of the bla ( ~44;~74 counter 33 and the OUtpllt of the line + or - from the b~al direction detector 25, as sl~own in the column of the ~ertical mode of Table 1. The bit n~lbers encoded by the coding cir-cuits 52 and 53 are compared in magnitude ~ith each other in ~ 5 the comparator 60 ; when the condition Ea~a~] > [blal~ is -~ established "1" is provided on the line V (Vertical mode), whereas when this condition is not established, "1l' is pro-vided on the line h (Horizontal mode~. In a case of the Vert-cal mode in which "1" is outpu~ted on the line V of the com-parator 60, the coded signal of the b1a1 coding circuit 53 is provided via the gate 71 to the signal combiner 90. On the other hand, in the Horizontal mode in which "1" is yielded on the line h, the gates 72 and 73 are opened to apply therethrough the coded signals of the a0a1 coding circuit 52 and the a1a2 coding circuit 51 to the signal combiner 90. The signal com-biner 90 combines the coded signals applied thereto from the Pass mode coding circuit 54 and the gates 71, 72 and 73 into a composite signal, which is provided on the output line 100 after being converted into an output signal train.
For the sake of brevity, the conditions for resetting the detectors, registers, counters and so forth are neither de-scribed in the foregoing nor shown in the drawings ; but, re-quired ones of these circuits (the b2 detector 24, the a detector 21, the a2 detector 22, the registers 81, 82 and 83, 25 the b~al direction detector 25, the counters 31, 32 and 33 and so forth) are reset for each setting of the picture element a0.
The interruption of the operation of this coding device is placed under the control of the address control circuit.
Namely, the a0 address is always watched by the address control .
.

~ ~144~74 circuit 5, the coding is stop~ed at the mornent when the aO
address becomes a iine terminating picture element and the aO address is newly set to a line starting pic~ure element and then coding of the subsecIuent line is resumed.
The above i~ the operation of the coding device of Fig. 9 and decoding is achiev2a by reversing the abovesaid steps.
An example o a decoding device is shown in Fig. 10~. Refer-ence numera]. 201 indicates an input terminal ; 202 designates an input bufex memory ; 203 identifies a mode code identify circuit ; 211 and 212 denote line memories ; 213 represents an aO memory ; 221 and 222 show address control circuits ; 231, 232 and 233 refer to decoding circuits ; 240 indicates a change picture element detector ; 251 and 252 designate a b~ detector and a b2 detector, respectively ; 261 and 262 identify an adder and a subtractor, respectively ; 271 and 272 denote counters ;
281, 282, 283, 284, 285 and 286 represent gates ; 291, 292 and 294 show OR circuits ; 293 refers to an excluslve OR circuit ;
300 indicates an aO reyister ; and 310 designates an output terminal.
The following will describe the construction and the oper-ation of the decoding circuit of Fig. lOA in detail. A coded signal from the input terrninal 201 is once stored in the in-put buffer memory 202. I'he mode code identify circuit 203 has such a con~truction as showr. in Fig. 5B, in which a signal (for example, four bits at most, as shown in Table 2) necessary or mode identification is read out of the input buf4er memory 202 to identify the modes of operation, i.e. the Pass mode, the Horizontal mode a~d the Vertical mode. When the signal is "1110", it is regarded as indicating tne Pass rnode and "1"

~ 4;~74 is outputted on a line ~ ; when the 5ignal is "1111", it is reqarded as indicatirlg the ~ori~ontal mode and "1" and is provided on a line _ ; when t'ne signal is "0", "100" or "1100", it is regarded as indicating that the direction of the distance blal is plus in the Vertical ~ode and "1" is produced on a line ~+ ; and when the signal is "101" cr "L101", it is regard-ed as indicating that the direction of the distance blal i5 minus in the Vertical rlode and "1" is yielded on a line V-.
The address contr.~l cir~uit 221 has such a construction as depicted in Fig. 5C, in which when any one of the ou~puts p, V- and V-t from t.he mode code identify circuit is "1", pulses are applied to tne memory 211 to shift it bit by bit from the a0 address provided from Sa0.
When the identify circuit 203 provides 'tl" on the line p (the Pass mode), the address control circuit 221 shifts the reference line memory 21.1 from the address OI the picture ele-ment aO to start detection of the distance b~b2. The reference line memory has stored therein information of the *revious line via the deeoding line memory 212. The change picture ele-ment detector 240 has the construction shown in Fig. 4B andprovides an output "1" upon each detection of a picture element different from the immediately preceding one in the signal train applied from the line memory 211. At the moment when the change pieture element detector 240 provides the output "1", if the detected picture element is different in level from the picture element aO, the output "1" is appli.ed via the exclusive OR
circuit 293 to the bl detector (an AND circuit) 251 to produce an output "1" on a line blp. The a0bl counter 272 receives pulses from the address control circuit 221 and counts the 1~44274 number of pulses occ-lrring in l-ne time inter~al from the aO
address to bl (un-ti.l ''1" i.s provided on tt~e line bl ). The b2 detector 252 ou.~puts "1" on a line b2p when another change picture element is detect.ed by the change p.icture element detector 240 after detection of the pictuxe element bl ("1'`
on -the line bl !. This b, detectol comprises a flip-flop and an AND circuit. The a~b2 counter 27i receives pulses from the address control circ~ 221 and counts them occurring in the time in~erval rom the a~ address to b2 ~until "1" i~ pro-vided on the line b2p). Upon occurrence of "1" on tne lineb~p, the address con..~ol ci.rcuit 221 once stops sending out of shift pulses. The informa~ion of the a0b2 counter 271 is applied to the aO register 300 via the gate 281, which is opened by the provision of the output "1" on the line p of the mode code identify circuit 203. The information of the a0 register 300 is added to the address control circuits 221 and 222, so that the aO address is newly set and the decoding oper-ation ~s resumed.
In a case where the identify circuit 203 provides "1" on the line V~ or V- (the Vertical mode), the output "1" from the OR circuit 291 is applied to the address control circuit 221 and the b~al decoding circuit 231. As a consequence, decoding relating to the abovesaid bl and b2 ta~es place and the count value of the a0bl counter lndicates the address of the picture element bl relative to the picture element a0. The bla~ de~
coding circuit 231 reads signals of one word from the input buffer memory 202 and decodes them. The decoded value is added by the adder 261 to the value of the a0bl counter 272 and, at ,he same time, subtracted by the subtractor 262 from the value ~144*~4 of the a0bl counter 272. In a case where the outpu-t line V+
of the mode code identify circuit 203 is "l", the gate 284 is opened, so ,hat the col~tents o~ the adder 26l. are provided via the OR circuit 2~2 to the address control circuit 222 and .- 5 to -the aO regis~er 300 via the gate 282. In contract thereto, if the output line V- of the mode code i.dent.ify circuit 203 is "l", the ga~e 225 is opened, passiny the contents of the subtract~r 262 to ~he address contrcl circuit 222 Vicl the OR
circuit 292 and to 'he a0 reglster 300 via the gate 282.
The address control circuit 222 has such a construction as depicted in Fl~. 10B, which sets up the address of the picture element a~ on the basis of the information transmitted thereto via the OR circuit 292, reproduces picture element sig-nals on the decoding line memory 212 from the picture element aO to a picture element immediately preceding a, to be the same level as the picture element a0 and inverts the level of the picture element a~ relative to the level of the picture element aO. The contents of the aO register 300 are ~pplied to the address control circuits 221 and 222, newly setting the address of the picture element a0 and resuming decoding.
In a case where the line _ of the mode code identify cir-cuit 203 becomes "1" (the Horizontal mode), the a0al and a~a2 decoding circuits 232 and 233 successively read si.gnals of two words from the input buffer memory 202 and the a0al decoding circuit 232 decodes the first one word and the ala2 decoding circuit 233 the second one word. The decoded values are added to the address control circuit 222 and the aO reyister 300 via the yates 283 and 286. The address control circuit 222 sets up the addresses of the picture elements al and a0, reproduces 1144~74 picture element signals on the decoding line memory 212 from the picture element aO to a picture element immediately preceding al to be the same as the level of the picture ele-ment aO and inverts the level of the picture element a~ and, thereafter, rPprcduces picture element sigrlals from the picture element al to a picture element immediately preceding a2 to be the same as the level of the picture element al and makes the informa~ion of the picture element a2 to be different from the level of the picture element al. The aO address register 1~ 300 restores the address of the picture elements a~ and a2, so that the a2 address becomes a new aO address. This new in-formation is provided to the address control circuits 221 and 222 to set the aO address and restart decoding.
Also in respec~ of the above decoding device, the reset-ting conditions for the detectors, the registers, the countersand so forth have been neither described nor shown in the drawings ; but required ones of them (the mode code identify circuit 203, the b2 detector 252, the address control circuits 221 and 222, the counters 271 and 272, the decoding circuit 231, 232 and 233, etc.) are reset for each setting of the aO
address. The termination of one line is achieved by super-vising the aO address with the address control circuit 222 and at the moment of the address of the picture element aO becoming the address of the last picture element of a scanning line, decoding of that line is completed and decoding of the next line is resumed.
Next, a description will be given of a system of suppres-sing degradation of thé picture ~uality of the reproduced picture due to a code error which is another object of this 1~44Z74 invention. In the coding system of this invention, a picture signal of the coding line is encoded using picture signal information of a reference line immediately preceding the coding line. Accordingly, on the slde of the decoder, the picture slgnal of the coding line is a1so decoded using the picture signal in~orma~ion already decoded. Thus, since cod-ing and decoding are performed ~uccessively using the picture siqnal information of scanninq 'ines immediately preceding the codlng lines respectl~ly, if a code error occurs due to the lC influence of circuit noises and the like to cause incorrect reproduction of picture signals of a certain line, picture signals of the succeeding lines~are not reproduced correctly, resulting in markedly degraded picture ~uality of the repro-duced picture.
Accordingly, it is necessary to detect occurrence of a code error, to suppress degradation of the picture quality of the line, in which the code error has occured and to rapidly recover from the code error state, so that the deterioration of the picture quality due to the code error do not spread to other lines.
According to this invention, these objects are achieved in the following manner : On the side of the coding device, a detectable, so-called self-synchronized first control code is inserted, from a desired position in a code train, at a predetermined period of a picture signal, for example, immedi-ately before the starting of coding of a line No.l evey four lines (K=4) as shown in Fig. 11 ; picture signal information of the line No.l is encoded (into, for instance, a run-length code RL~ by a one-dimensional method I without using picture ~ 35 -signal information of a line immediately preceding the~line ~No.l ; scanning lines No.2, ~o.3, ... No.K immediately follow-ing the line No.l are subjecte~? to the two-dimensional succes-~-~sive codins II of this inventlon ; and a;second cont~ol code, S different from the first control code for detecting the occurrence of a code error i9 inserted j-lst before the~coded ~signal of each llne~
On ths side of the decodirig de~vice, when the self-synchronized firsl control code is detected, it is decoded as ~10 the~ ne~No.l wlthout using information of the immediately precedlng line Oll the assumption that the directly ollowing ;~
code train has been encoded into a run-length code, RL. When the second control code is detected, it is decoded using in-formation of the immediately preceding line on the assumption that it has been encoded according to this invention. Directly after completion of decoding of each line, the presence or , absence of the first or second control code is checked to effect error checking. When an error is detected, the decoded line, in which the error is detected, is subjected to processing such as replacement by a picture signal of the immediately preced-ing line to thereby suppress deterioration of the picture :., quality. Upon detection of the error, the decoding operation is once stopped ; but when the self-synchronized first control code is detected, decoding of the run-length code RL is immedi-~ 25 ately started to restore from the error state.

-Fig. 12 illustrates in block form a coding device embody-ing the present invention based on such principles, and Fig. 13 ~; a corresponding decoding device. A facsimile picture signal .
input line 1 is connected via a switch 101a to an RL coder 102 ~ 36 ~

;~

-( 1144Z74 : `:

-~ ~ every K lines under the control of a switch control circuit 101~. At this time, a first control code generator 104 gener-ates~a~first control code and the RL coder 102 encodes a ine~(No.~ into a run-length code. Upon completion of this S encoding, the switch l01a is connected to a two-dimensional coder~l03 of this invention to achieve~ two-dimensional coding ;of~lines~No.~ 2 to No. K ac~ording to this invention and a second control code ls~lnserted by~a second control code in-serting clrcuit~105 just ~efore the coded signal of each scan-ning~ line~

" -: :: : ~ .: ~:
On~the;~side of the decoding dévice shown in Fig. 13, when the fir~st~control code is detected by a~ first control code detector 106, the run-length code is decoded by a run-length oode decoder 107 for one line (No. 1) only and the reproduced picture element information is stored in a line memory 108 ~ ~ :
and, upon completion of decoding of the line No. 1, the content of the line inemory 108 is transferred to a line memory 109.
, . .
Thereafter, successive decoding of the lines No. 2, No. 3, ..

.. No. K corresponding to the coding of this invention is : .
: ~ 20 effected~by such a decoder 110 as shown in Yigs. 5A and 10A
using the content of the line memory 109. Upon completion of decoding of each line, the control codes are detected by the ; oontrol code detectors 106 and 111, and it is checked by a code error detector 112 for occurrence of a code error.
Onoe a code error has occurred in a scanning line, no decoding takes place until the scanning line No. K. Then, upon detection of the first control codel an ordinary decoding operation is started to restore from the code error state.
~; As has been described in the foregoing, the present i - 37 -::
: ~:
, - ' .

1~4;~4 invention has the advanta~e that highly e~ficient coding can : be achieved without depending on correlation, between adja-cent lines of sig.nals, by properly selecting the two kinds of coding systems in which a signal having high correlation between adjacent lines, such as a two-level facsimile signal, is encoded with high efficiency using a dlstance between a change picture element to be encoded and an adjoining one, and in which in a case of a part havlng no correlation to a line just above it, just like a first line of a document, a change picture element is encoded using a distance between it and another picture element of the same line.
The present invention has another advantage that by in-. serting a self-synchronized first control code, for example, every K scanning lines, encoding only one scanning line into run-length codes, encodinq the subsequent scanninq lines accord-inq to this invention and then checkinq for a code error u-~on completion of codinq of the said one scanninq line, deqradat-ion of the Picture quality due to the code error is prevented from spreadinq, therebY to enable rapid restoration from the code error state.
In the following, another embodiment of this invention relating to the second object will now be described, in which the two dimensional coding principle as described above and the one dimensional coding principle, such as the run-length coding principle, are adaptively adopted.
Next, an example of the one~dimensional coding will be described. Fig. 8C shows an example of a facsimile signal.
In the one-dimensional coding system, a run from a picture ~element C, to a picture element directly before a picture ~ 38 1~4~74 element C2 consists of five black picture elements, and hence is coded into "0011", for example, according to the MH code in Table 1 ; a run from the picture element C 2 to a picture element immediately before a picture element C3 conslsts of seven white picture elements, and hence is coded into "1111" ;
and a run from the picture element C3 to a picture element immediately before a picture element C4 oonsists of two black picture elements, and hence is coded into "11". These coded trains are stored or outputted as a one-dimentional coded line.
The following will describe examples of circuits for applying this invention into practice in accordance with the principles described above.
Fig. 14 is an e~ample of a coding device, in which the part indicated by a dotted enclosure is the same as Fig. 9.
A change picture element detector 13 is composed of a l-bit memory and an exclusive OR circuit as shown in Fig. 4B. There are further provided a NAND circuit 7, an AND circuit 8, a counter 34, coders 55 and 56, coded signal memories 91 and 92, a comparator 62, tates 77 and 78, a first control code gener-ator 102, and a second control code generator 101.
Next, the construction and operation of this embodimentwill be described in detail. A facsimile signal to be coded is provided from the input terminal 1 to the coding line memory 2 for storage therein. Before this time, as a signal of a reference line, a signal of the preceding line stored in the line memory 2 is transferred to the reference line memory 3 for storage therein. The aO memory 4 has stored therein level ; of the starting picture element aO, as will be described later on. Reading of the coding line memory 2 and the reference ~ 39 ' ,. ~ - ' , -~1~4274 line memory 3 simultaneously starts from the position of the starting picture element aO under the control of the address control circuit 5.
`-` The change picture element detectors 11, 12 and 13 res-S pectively are each constructed, as shown in Fig. ~B, and compare the picture element signals read out of the line memo-ries 2 and 3, respectively, with immediatel~ preceding picture element signals of each line to output "0" or "1" in dependence on whether the former signals are of the same level as the latter signals or not.
The bl detector 23 is an AND circuit which provides "l" on the output line blp when a change picture element is detected by the change picture element detector 12 and level of the detected change picture element differs from that of the start-ing picture element a~, that is, when the output from the ex-clusive OR circuit 6 is "1". The b2 detector 24 procides "l"
on an output line b2p in a case where a change picture element is detected by the change picture element detector 12 after detection of the change picture ele~lent bl by the bl detector 23 ; this bl detector 24 can be made up of one flip-flop and an AND circuit The Pass mode detector 40 is an AND circuit which provides "1" on an output line ~, judging that the mode of operation is the Pass mode in a case where the picture ele-ment al has not been detected at the moment of occurrence of "l" on the output line b2p (in this case, aln which is the output Q of a flip-flop in the a~ detector 21 is "1"), as will be described later With "l" on the output line p, the Pass mode coder to the coded signal memory 91. Following this, a new starting picture element is shifted to the position just under the picture element b2 in the following manner : Upon occurrence of 1 on the line b2 ~ the b2 address register 81 stops counding of pulses from the address control circuit 5 and stores the count value. This information is appl~ed via the gate 74 to the aO address register 84 at the mo}nent of the Pass mode detector 40 providing 1 on the line ~ The contents of the aO address register 84 are applied to the address control circuit 5 to re-start the coding operation with the new starting picture element aO.
The change picture element detector 11, when detecting a change picture element provides an output 1 to the al de-tector 21 (a flip-flop). As a result of this the information on the lines al and a1n change from 0 to 1 and from 1 to 0 , respectively. The a2 detector 22 is a flip-flop which outputs '1" on a line a2p when a change picture element is detected by the change picture element detector 11 after the picture element a~ is detected by the a~ detector 21 ( 1 on the line a1p). The aOal counter 32 starts counting of pulses from the moment of setting aO in the address control circuit 5, but stops the counting upon reception of "1" from the line alp and provides the count value to the aOa~ coder 5~. The aOal coding circuit encodes the count value with lllll" added to its head, using such a code table as shown in the column of the Horizontal mode of Table 1. The a~a2 counter 31 starts counting with "1" on the line alp and stops the counting with "1" on the line a2p and provides the count value to the ala2 coder. The ala2 coder 51 encodes the count value using such a code table as shown in the column MH(xy) of Table 1. The bla~ counter 33 43ceives the outputs from the lines blp and 1~44274 alp and starts pulse counting with a first appearing "1" in either one of the outputs and stops the counting with a next appearing "1" in the other. To the b~al direction detector 25 are also applied the outputs fromt~e lines b1p and a1p and, with the circuit construction shown in Fig. 4C, this datector outputs "1" on a line + when "1" of the line b1p appears earlier than or simultaneously with "1" of the line alp but, in the opposite case, provides an output "l"~on a line -.
The b~al coder 53 encodes blal with a sign + or - added thereto on the basis of the count value of the bla~ counter 33 and the output of the line + or - from the blal direction detector 25, as shown in the column of the ~ertical mode of Table 1. The bit numbers encoded by the coders 52 and 53 are lS compared in magnitude with each other in the comparator 61 ;
when the condition [a0al] > [blal] is established, "1" is pro-vided on the line V (Vertical mode), whereas when this condi-tion is not established, "1~ is provided on the llne h (Hori-zontal mode). In a case of the Vertical mode in which "1" is outputted on the line V of the comparator 61, the coded signal of the blal coder 53 is provided via the gate 71 to the coded signal memory 91. On the other hand, in the Horizontal mode in which "1" is yielded on the line h, the gates 72 and 73 are opened to apply th~rethrough the coded signals of the aOa, and ala2 coders 52 to the coded signal memory 91.
The change picture element detector 13 is a detector for the one-dimensional coding. Upon detection of a change picture element by this detector, the counter 34 starts counting of clock pulses Pc and, upon detection of the next ~hange picture ~ 4 - ` -f 1144Z74 element, this CGUnting is once stopped, and the count value at this moment is coded by the coder 55 or 56 of the next stage.
The output from the counter 34 is coded by the coder 55 or 56 in dependence on whether the signal is white or black.
Namely, a signal from the coding line memory 2 and the output -~ from the change picture element detector 13 are applied to the NAND circuit 7 and the AND circuit 8, and the outputs from the NAND circuit 7 and the AND circuit 8 are applied to the coders 55 and 56 respectively ; the coder 55 or 56 operates in depen-dence on whether the outputs from the N~ND circuit and the AND
circuit are each "0" (white) or "l" (black). In this manner, the count value of the counter 34 is applied to the coder 55 or 56 and coded therein by the MH code of Table l, thereafter lS being provided as a one-dimensional coded train to the coded signal memory 92. The coded output signal thus stored in the coded signal memory 91 is a two-dim~nsional coded signal, there-as the coded output signal stored in the coded signal memory 92 is a one-dimensional coded signal. These coded signals are applied to the comparator 62 and compared with each other, for example, in the number of bits for each line in the outputs from the memories 91 and 92 for selecting a more advantageous one of the both memory output signals.
Where the one-dimensional coding is judged to be advantage-ous as a result of the comparison in the comparator 62, an out-put Sl becomes "l" to open the gate 78 for passing on the in-formation of the coded signal memory 92 to the signal cvmbiner 110. At the same time, the first control code generator 102 provides a first control code (a first line cynchronizing signal - 43 ~

LSSl)~,~for example, !~olllllll~ representing that the line is a one-dimensional coded line. This control code i9 added to the head of the~informaeion o2 the coded signal memory 92.
In~case~the two-dlmensional coding i9 judged to be advant-5~ ageous as~a~result~of~the~comparlson in the comparator 62, an output S2: becomes "l" to open~the gate 77~for applying there-through~the informatlon of the coded~signal memory 9l~to the slgnal combiner~llO. ~At~the same~time,~;~the second control code generator-~lOI provides a~second control~ code (a second line lOi: ~synchronizing signal LSS~2), for example,~ "01111110" indicating ~ that~the~line ls~a two-dimensional coded;line. This control '.'',,'!":' ~ code is~added~to~the~head of the information of the coded signal mémory 91. The~signal~combiner llO combines the control code from the control code generator lOl or 102 and the signal from " ~
the~gate 77 or~78 into a composite signal, which is sent out from the output terminal 120 after being ~onverted into an out-put signal train.
In a case of producing the first and second control codes ;in the form~of "Olllllll" and "OllllllO" respectively, as de- -0 scribed above,~in~ordér~to make these control codes distingish-;~ able from other codes, lt lS necessary, for example, to co=pul-~ sorily insert~"O" in the control codes every five "ls"-occurring ,~ .
- successlvely in the coded signals, like "11111010" ..."

~ Needless~ to say, the decoding siae decodes the coded signals < ~ 25 removing "O" next to "11111" in the coded signal.
.
For the sake of brevity, the conditions for resetting the detectors, registers, counters and so forth are neither described in the foregoing nor shown in the drawings ; but, required ones ,, ~ .
~ of these circuits (the b2 detector 24, the al detector 21, the .: : .
, .
. .

; .

114~ 74 :j a2~detector 22, the registers 81, 82 and a3, the blal direction detector 25, the counters:31, 32:and 33 and so forth) are re-set for each setting of the picture element aO.
The:ln~terruptlon of the operation of this coding device S is placed~under the~control of the address~ control circuit.
.~s;~Nam~ely,~the~aO:~address~is always~watched~by the~address control oiroult~5, and~the codlng is~stopped~ at the moment when the aO
address becomes~a llne:terminating picture:~element, and the a3 address ls~newly~set~to~a line'startin'g pLcture~element,'and 0 ~then~coding;~o~f the subsèquent line i8 resumed.
: An~example of a:decod:ing device for receiving a facsimile signal encoded by the~embodiment of Fig. I:4 is shown in Fig. 15, :;' in which oircuits enolosed~by a dotted enclosure are further added to:th decoding~devioe shown in Fig.: 10A. The enclosure part comprises a first oontrol oode detector 311, a second con-trol code~detector 312, flip-flops 321 and 322, gates 287, 331 and 332, a one-dimensional coder 234, and decoded signal memories 341 and~342.~ : ' ~The following will describe the construction and the oper-r, ~: ~,20 ~ation of the decoding devlce of Fig. 15 in detail. A coded ~' ., :, ~ :
i ' ~ signal fr.om~the input terminal 201 is once stored in the input buffer memory 202. The signal from the input buffer memory 202 is checkd~first by the first and second control code detectors ' : 311~and 312 as to whether the signal is the one-dimensional or two-dimensional coded one.
: :: If the inputted control code is, for example "01111110", 3 the signal is judged as the two-dimensional coded one, and the second control code detector 312 provides an output "1" to set the flip-flop 322j opening the gate 288. When.the control code ,~ : -.

:'~'' ', ' is,~for~example, "01111111", the signal lS judged as the one-; dimensional coded signal,~and the first control code detector 31~1 yields~an~output "l"; to set the flip-flop 321, opening the gate 287~ At~this time, the flip-flop 322 is reset ; consequ-5~ently,~the~gate~288~1s cut off.
In a~c~ase~of the~two-dimensional coded signal being applied to~ope~n;the~gat~e~288~, the mode oode ident~ify circuit 203, which has~such~a~oonstruction~as shown in~Fig. S~B, responds to open- -~
ng~of the~gate~288 to read a requir~ed number of signals (for O~example, four~bits~at most;, as shown~ln~TabI~é~l) from the input $~ buffer memory 20~2, identifying the mode of the input signal, i.e.
any of the Pass mode, the Horizontal mode and the Vertical mode.
When the s~ignal is "1110", it is regarded as indicating the Pass mode, and "1" is outputted on a line p ; when the signal is ;~ 15 "1111", it is regarded as indlcating the Horizontal mode, and "1" is-provided on a line h ; when the signal is "O", "100" or oo~, it is regarded~as indicating that the direction of the .
,~ distance b~al is plus in the Vertical mode, and "1" is produced on a line~V+ ; and when the signal is "101" or "1101" it is 20- regarded as indicating that the direction of the distance b~a, ~is minus in the vertical mode, and "1" is yielded on a line V-.
The address control circuit 221 has such a construction as de-picted in Fig. 5C, from which when any one of the outputs p, ,1 :
~- V- and V+ from the mode code identify circuit is "1", pulses ,, , :
2~5 provided from SaO are applied to the memory 211 to shift it bit by bit from the aO address.
., , ;When the identify clrcuit 203 provides "1" on the line p, the~address control circuit 221 shifts the reference line memory 211 from the address of the picture element aO to start detection " :
~ .

~ ~ li44;i~74 of~the~picture elements bl and b~. The reference;line memory 211~has~prestored~ therein information of the previou~s~llne 7~ vi~a the~decoded line memory 212. The chanqe picture element detector~240 has the construction shown in Fig. 4B~and provides S~ an output "l"~upon each detection of a picture element differ-ent~from the~lmmediately preceding one in the signal~train -- appl~ied~from~the~l~ine~memory~211. At the moment when the change picture el~ement~detector~240 provides the~output "1", if the detected-~plcture element~is~different in level from the picture ~A ~ 10; element a~ the~output~"l" is applied vla~the exclusive OR cir-J-~ cuit Z93 to the bl~detector tan AND circuit) 251 to produce an ¦ ~ output ~;ln o n~a line~blp. The aObl counter 272 receives pulses i~ rom the;address~control circuit 221 and counts the number of pulses occurring in the time interval from the aQ~address to b 15 (unit "1" ~i9 provided on the line blp). The b2 detector 252 outputs "ln~on a~line b2p when another change picture element is detected by the change picture element detector 240 after detection of the picture element b2 ("1" on the ~ine bl ).

:
This bl detector comprises a flip-flop and an AND circuit.
20 ; me aOb2 counter 271 receives pulses from the address control ~; circuit 221 and counts them ocourring in the time interval from t, ~ ~ the~aO address to b2 (until "1" is provided on the line b2p).
~ Upon occurrence of "1" on the line b2p, the address control cir-j~ ~cuit 221~once stops sending out of the shift pulses. The in-formation of the aûb2 counter 271 is applied to the aO register~ 300 via the gate 281, which is opened by the provision of the ; ~ output "1" on the line p of the mode code identify circuit 203.
~The contents of the aO register 300 are added to the address control circuits 221 and 222, so that the aO address is newly .~ , : ~: , ~ ~ 47 -;~

.' ' :~ , ~144~74 set and the decoding operation is resumed.
In a case where the identify circuit 203 provides "1" on the line V+ or V- (Vertical mode), the output "1" from the OR
circuit 291 is applied to the address control circuit 221 and the b~al decoder 231. As a consequence, decoding relating to the abovesaid bl and b2 takes place, and the count value of the aOb~ counter indicates the address of the picture element bl relative to the picture element a0.
; The blal decoder 231 reads signals o one word from the input buffer memory 202 and decodes them. The decoded value is added by the adder 261 to the value of the a0bl counter 272 and, at the same time, subtrac~ed by the subtractor 262 from the value of the aOb~ counter 272. In a case where the output line V+
of the mode code identify circuit 203 is "1", the gate 284 is opened, so that the contents of the adder 261 is provided via the OR circuit 292 to the address control circuit 222 and to the aO register 300 via the gate 282. In contrast thereto, if the output line V- of the mode code identify circult 203 is "1", the gate 285 is opened, passing the contents of the subtractor 262 to the address control circuit 222 via the OR
circuit 292 and to the aO register 300 via the gate 282 The address control circuit 222 has such a construction as depicted in Fig. 10B, which sets up the address of the picture element a~ on the basis of the contents transmitted thereto via the OR circuit 292, reproduces the picture element signals on the decoded line from the picture element aO to a ; picture element immediately preceding al identical with the level of the picture element aO and inverts the level of the picture element al relative to the level of the picture element - ~8 -1144;i~4 aO. The content of the aO register 300 is applied to the address control circuits ~21 and 222, newly setting the address of the picture element aO and resuming decoding.
In a case where the line h of the mode code identify cir-~; S cuit 203 becomes "1" (Horizontal mode), the aOa~ and a~a2 de-coders 232 and 233 successively read signals of two words from the input buffer memory 202 and the aOal decoder 232 decodes the first one word and the a~a2 decoder 233 the second one word. The decoded values are added to the address control cir-cuit 222 and to the aO register 300 via the gate 283 or 286.The address control circuit 222 sets up the addresses of the picture elements al and aO, reproduces the picture el~ement sig-nal on the decoded line from the picture element aO to a picture element immediately preceding a, to be the same level as that of the picture element aO and inverts the level of the picture element a~ and, thereafter, reproduces the picture element sig-nals from the picture element al to a picture element immedi-ately pr~ceding al to be the same level as that of the picture element a~ and sets the level of the picture element a2 to be different from the level of the picture element a,. The aO
address register 300 restores the addresses of the picture elements a~ and a2, so that the a2 address becomes a new aO ad-.: ~
dress. This new information is provided to the address control ; circuits 221 and 222 to set the aO address and restart decoding.
The two-dimensional decoded outputs of the Vertical and Horizontal modes thus applied to the address control circuit 222 is processed therein as described above and then stored in the decoded signal memory 342. In ,his case, since the flip-flop 322 is in the set state, the gate 332 is opened by its '' , , ~
~ 49 -output~, so that the two-dimensional decoded signal stored in ~ the decoded slgnal memory 342 is applied to the decoded line $~ memory 212 and then outputted via the output terminal 350.
Next, when the first control code detector 311 detects 5 ~the~control code indi~ating the one-dimensional coded signal, the~gate~28~7~is~opened, as mentloned above, and the signal of the line~is~decoded~by the one-dimensional decoder 234, there-after~being~stored in the decoded~signal~memory 341. ~At this time,~slno~e;~the~gate~33~1 is open,~the one-di=ensional decoded ~10 ~s~igna~ is~provided to~the decoded line memory 212, thereafter being outputted via the output terminal 350.
Also~in respect of the~ above decoding device, the reset-ting conditions for the detectors, the registers, the counters and so forth~have been neither described~nor shown in the r ~, ~15 drawings ; but required ones of them (thé mode code identify circuit 203, the b2 detector 252, the address control circuits 221 and 2?2, the counters 271 and 272, the decoders 231, 232 ~ i :
and 233, etc.) are reset for each setting of the aO address.
The termination of one line is achieved by supervising the aO
~o~ 20 address with~the address control circuit 222 and, at the moment ~ ~sf the address of the picture element aO becoming the address ;;~ of the last picture element of a scanning line, decoding of that line is completed and decoding of the next line is resummed.
In the embodiment described above, the numbers of bits of~the one-dimensional and two-dimensional coded signals for :~ éach line are compared, and the coded signal of a smaller num-ber of coded bits is selected ; but this comparison between the amounts of information of the one-dimensional and two-dimenslonal coded signals is not limited specifically to the .:

1~44274 above. For example, the absolute number and a predetermined reference number of picture element changing points of the line to be coded are compared with each other ; if the former is smaller than the latter, the one-dimensional coded line is used, and if the latter is smaller than the former, the two-dimensional coded line is used. Similarly, a dif~erence between the absolute number of picture element changing points of the line to be coded and the absolute number of picture ele-ment changing points of an immediately preceding reference line is compared with a predetermined reference number ; if the former is smaller than the latter, the two-dimensi~nal coded line is used, and if the former is larger than the latter, the one-dimensional coded line is used.
~ - In the above, the one-dimensional and two-dimensional coded lines are selectively employed in accordance with the results of compariso~ between the amounts of information of the one-dimensional and two-dimensional coded signals at the end of scanning of one line, but it is also possible to perform ; coding and comparison for each signal of a predetermined length on one scanning line. Moreover, while the above embodiment has been described in connection with a case of using the two-dimensional sequential coding system, the invention can be carried into practice even if some other two-dimensional cod-ing system is used.
; 25 As described in the foregoing, according to this invention, a digital facsimile signal is coded by the one-dimensional and the two-dimensional coding system for each line and, in accord-ance with the amounts of information of the two coded signals, a more favorable one of them is selected as a coded output, ; 1144Z74 for example, as shown in Fig. 16. Accordingly, there is the possibility that two-dimensional coded outputs are sucessively produced over a number of lines. With the two-dlmensional coding system, however, each line is coded and decoded utiliz-ing picture signal information of a reference lin~e immediatelypreceding it, as described previously, and a code error result-ing from a circuit noise or the like is likely to lead to a substantial degradation of the picture quality of reproduced pictures in those line following that in which the code error has occurred. Therefore, in a case where when a code error is detected, a request repeat system can be used as in a four-wire private circuit or data communication network and a two-wire network circuit like an ordinary telephone circuit is employed, it is necessary to prevent spreading of the error.
Next, a description will be given of a system for limit-ing degradation of the picture quality of a reproduced picture due to the code error. This is to prevent that in the one-dimensional, two-dimensional adaptive coding system described in the foregoing, the number of two-dimensional coded lines ZO being outputted in succession exceeds, for example, K lines (K is selected suitably but is shown to be five,), as shown in Fig. 16.
In Fig. 16, in a case where it is judged that a one-dimensional coded line is favorable for a first line and that .
two-dimensional coded lines are favorable for second to eighth lines, a one-dimensional coded line is compulsorily used for the sixth line instead of the two-dimensional coded line so that K does not exceed five. In Fig. 16, for a ninth line, a one-dimensional coded output is produced according to the judgement !

~144~74 that it is favorable for the ~ine. Even if the one-dimensional coded line is selected as a result of comparison between the ;~ one-dimensional and two-dimensional coded lines, a one-dimensional coded line is thus compulsorily inserted after K-l successive two-dimensional coded lines counting from the one-dimensional coded line. Accordingly, a one~dimensional coded line may in some cases be inserted after two-dimensional lines less than X are outputted.
In an embodiment of this invention based on such princi-ples, there are provided in-the coding device a scale-of-K
:
counter 130, an inhibit circuit 131 and OR circuit 132, as indi-cated by the broken line in Fig. 17. When the output S 2 from i ;; the comparator 62 is produced successively for K lines, the output S2 iS inhibited by the inhibit circuit 131, and the out-put from the OR circuit 132 is applied to the first control code generator 102 and the gate 78, with the result that the first control code and a one-dimensional coded signal are transferred to the signal combiner 110. For the decoding device, however, no modification is needed.
As has been described in detail in the foregoing, the present invention permits a substantial reduction of the amount of information to be transmitted and prevents spreading of degraded picture quality due to a code error or the like.

' ~: .

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A transmission system for facsimile signal for decoding a coded facsimile signal developed so that the positions of information change pic-ture elements included in a two level facsimile signal, which is obtained by scanning an original picture and successively sampling the scanning output into picture elements, are coded, the improvement of the system comprising:
first circuit for storing information of a scanning line to be coded;
second circuit for storing information of a reference line just coded;
third circuit for controlling addresses of said first circuit;
fourth circuit for controlling addresses of said second circuit;
fifth circuit for setting a starting picture element on a decoding scanning line from which the decoding starts;
sixth circuit for detecting first, second and third mode codes from the coded facsimile signal;
seventh circuit for detecting a first reference picture element which is a first information change picture element positioned after a picture element just above the starting picture element on the reference scanning line and having a signal value different from that of the starting picture element;
eighth circuit for detecting a second reference picture element which is an information change picture element just succeeding to the first reference picture element;
ninth circuit for decoding a code indicative of a relative distance between the first reference picture element and an information change picture element just succeeding to the starting picture element on the decoding line when the third mode code is detected; and tenth circuit for decoding a code indicative of a relative distance between the starting picture element and an information change picture element just succeeding to the starting picture element on the decoding line when the second mode code is detected.

2. A transmission system for decoding a coded facsimile signal ac-cording to claim 1, further including:
eleventh circuit for detecting a first control signal from the coded facsimile signal;
twelfth circuit for detecting a second control signal from the coded facsimile signal; and thirteenth circuit for decoding the coded facsimile signal without reference to the information of the reference scanning line;
fourteenth circuit for detecting code errors.

3. A transmission system for decoding a coded facsimile signal ac-cording to claim 1, further including:
eleventh circuit for decoding a code indicative of a relative dis-tance between the starting picture element and a second information change picture element just succeeding to the first information change picture ele-ment immediately after the starting picture element on the decoding scanning line when the second mode code is detected.

4. A transmission system for decoding a coded facsimile signal ac-cording to claim 3, further including:
twelfth circuit for detecting the first control signal from the coded facsimile signal;
thirteenth circuit for detecting the second control signal from the coded facsimile signal;
fourteenth circuit for decoding the coded facsimile signal without reference to the information of the reference scanning line; and fifteenth circuit for detecting code errors.