CA1085510A

CA1085510A - Compressed refresh buffer

Info

Publication number: CA1085510A
Application number: CA266,791A
Authority: CA
Inventors: Philip A. Sheppard
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1975-11-28
Filing date: 1976-11-29
Publication date: 1980-09-09
Also published as: IT1072610B; GB1488538A; DE2652900A1; FR2333319A1; FR2333319B1; JPS5282027A; DE2652900C2

Abstract

COMPRESSED REFRESH BUFFER
ABSTRACT
Data compression is effected in the refresh loop of a transient video display. The digital image is divided into equal areas and mapped in a bit map store. If an area contains one bits it is represented by a one in the bit map store, otherwise it is represented by a zero.
A refresh buffer store contains only those areas including one bits.
The buffer and bit map stores are operated synchronously and zeroes are forced in the data stream to the video display when zero is detected in the bit map store. Extension of the scheme to provide for colour displays is described.

Description

This invention relates to refresh circuitry for a device which provides a transient display. The most common device of this kind is the cathode-ray tube (CRT) display device and the invention will be described as applied to a CRT, although it is also applicable to pulsed arrays of electroluminescent devices, for example.
One way of providing an image display is selectively to brighten or illuminate discrete points of a raster. It is with this type of image display that the invention is concerned. Since the devices with which the invention is concerned provide transient displays, it is necessary repeatedly to supply to the device information defining the image being displayed. The circuitry which stores and repeatedly makes available the information is known as refresh circuitry.
The information may be held in the refresh circuitry in coded form which is decoded at the display device. This, however, can impose un-desirable limitations on the kind of image which can be displayed. The invention relates to that arrangement in which, for each point of the raster, the information consists of at least one binary digit. In the normal, non-colour, case there will be only one bit for each point of the raster. In this arrangement, the information defining the image to be displayed is called the digital image of the display.

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10~5510 1 A high-definition raster suitable for displaying detailed images isabout 1000 lines high, each line containing about 1400 raster points.
It follows that a digital image consists of about 1.5 x lo6 bits and the refresh circuitry proposed heretofore has had to provide storage for these bits.
It is readily observable, that most images, this page for example, consists of large regions of blank space. By suitable coding, the amount of storage required for a digital image can be reduced. It is to be the solution of the problem of saving storage space that this in-vention is directed.
British Patent 1 280 152 granted to Smiths Industries has suggestedthat in facsimile transmission apparatus a digital image be divided into regions of say 64 by 64 bits. If a region contains only zeroes, a single zero is transmitted whereas if the region contains at least one one, a one is transmitted and the region is divided into sub-regions of 16 by 16 bits. If a sub-region contains only zeroes, a single zero is transmitted, whereas if a sub-region contains at least one a one is transmitted and the sub-region divided into 4 by 4 areas. Again the coding technique is repeated until finally only those areas of the digital image which contain ones are directly transmitted. At the receiver the facsimile is reconstituted onto a CRT screen and photo-graphed. This coding system is extremely complex and cannot cheaply be implemented. Also it does not have to meet the strict timing requirements of refresh circuitry.
Another solution is described in an article by Thornhill and Cheek in the issue of Electronics dated 7 February 1974 at pages 95 to 101.
The blank regions of an image are identified by so-called address words -which point to the next object to be displayed. Storage contains code words representing characters or vectors, interspersed with address words defining variable length blanks. This is not a digital image as described above and dif~fers from the solution adopted by the invention, since decoding is required. Various other data compression schemes have been suggested, but have proved too complex to operate at the speed required to refresh a high definition digital image.

101~5510 1 According to the invention we provide, for a device providing a transient display and which operates to display an image by illuminating selectively and cyclically display points of a raster in response to a data stream cyclically supplied from refresh circuitry and comprising at least one digital image of the displayed image, wherein each digital image consists of equal digital image areas, refresh circuitry charac-terised by buffer storage means arranged in operation to contain only those digital image areas which do not contain only bits of a given value, bit map storage means containing for each digital image area a bit, the value of which indicates whether or not the digital image area consists only of bits of a given value, data stream generating means arranged in operation sequentially and cyclically to read out the contents of the bit map storage means and, in response to the said contents, generating the data stream by selectively reading out the content of the buffer storage means and selectively generating bits of the given value.
If the illumination of a raster point is defined by more than one bit, each such bit is defined as belonging to a different digital image.
For example, the choice of seven colours or blank can be represented by three bits. There are, in this case three digital images each con-sisting of one corresponding bit for each raster point.
The invention will further be explained, by way of example, with reference to the accompanying drawings, in which:
Figure 1 is a block diagram of refresh circuitry according to the invention associated with a CRT display;
Figures 2A to 2C are illustrative of how an image is generated and represented digitally;
Figure 3 shows how information is stored in the buffer and bit map stores I Figure 4 shows schematically part of the addressing circuitry of the bit map store;
Figure S is a block diagram of another embodiment of the invention;
and, Figure 6 shows one way of storing a digital image in the buffer store.
Referring to Figure 1 of the drawings, in the preferred embodiment of the invention, the beam of a cathode ray tube (CTR) 1 is caused by drive circuitry 2 to trace a fixed raster on the screen of the tube 1.
The intensity of the beam is low, so that the raster is not visible to an observer, and an image is generated by selective intensifying of the beam by bright-up pulses supplied to the brightness control circuitry over conductor 3. The pulses are of short duration, each being sufficient only to cause a point to be displayed. Means are known to run successive pulses together so that lengths of the raster, rather than points, are displayed, and such means can be used if desired. A refresh buffer store 4 is provided to supply the bright-up pulses to the CRT 1 in synchronism with the tracing of the raster. As shown, associated with the store is an output register 5 and an input register 6, although these may be combined into a single input/output register. Registers 5 and 6 are shift registers capable of receiving parallel data inputs and of providing parallel data outputs as well as shifting data serially into or out of the register. The serial output of register 5 is supplied to conductor 7 which is connected to conductor 3 and also to the serial input of register 6. In operation, information comprising bits stored in register 5 is shifted onto line 7 and is manifested as a pulse if the bit is one or as the absence of a pulse if the bit is zero. The pulses are supplied over line 3 as bright-up pulses and also to the input of register 6. The infonmation is shifted into register 6 which is operated in synchronism with 10~5510 1 register 5. Information in register 6 is transferred in parallel to theaddress location in buffer store 4 defined by the current state of addressing circuitry 8 and information for register 5 is received in parallel from the address defined by the addressing circuitry. If read-out from store 4 is non-destructive the connection between registers 5 and 6 is not required.
The components and operations so far described are conventional and well known in the display art. The invention leads to a big reduct;on in the size of buffer store 4 and, even when the cost of additional control circuitry is taken into account, to an overall reduction of cost of refresh circuitry.
The principle of the invention is shown in Figures 2A to 2C.
Figure 2A represents part of an image being displayed on the CRT screen.
The circles represent raster points at which bright-up pulses are possible and the shaded circles represent bright points on the screen, i.e. points at which bright-up pulses are possible and the shaded circles represent bright points on the screen, i.e. points at which bright-up pulses have been received. Figure 2B shows the known way of representing corresponding parts of the image in the buffer store 4.
Each point of the raster is allocated a binary storage location in the store and a one bit is stored in each location corresponding to a point to be brightened. In the simplest arrangement the storage locations correspond in their relationship in the store in the same way as the points of the raster in their relationship on the screen. Thus, if a raster contains 50,000 points, the bits representing the image are stored in 50,000 successive storage locations in the same sequence as the raster is scanned. Other arrangements are possible such as the storage of blocks of image information with pointers indicating the start address of the next block to be displayed. The invention is applicable to any such arrangement but will be described as applied to the simple one-to-one storage to image relationship.

~085510 1 Figures 2A and 2B have been divided into 4 by 4 element areas, th~elements being in one case raster points, and in the other case storage locations. It will be seen that the area of Figure 2B labelled II does not contain any one bits so that the effect of reading out area II j5 r' that no bright-up pulses are generated on line 7. Clearly the same effect can be achieved by not reading out area II for the time period of the raster scan assigned to area II of the store. The invention relies on appreciation of the fact that the usual image consists of a large number of areas such as area II, as is exemplified by consideration of this printed page or the drawings accompanying this specification. Even relatively detailed images, such as Ordnance Survey maps contain many "empty" areas. It has been empirically determined that when displaying a wide range of images on a typical high resolution raster display an assumption that 75% of digitised image areas do not contain one bits is acceptable. This assumption depends, of course, on the size of the image areas and is made for areas which are small relative to the raster. If the high definition raster mentioned above is taken as an example, a 4 x 4 area is 1/250 of the image height and 1/350 of the image width. The required storage capacity of buffer 4 is reduced by including in it only those areas which contain one bits and a bit map store 9 is provided which indicates which image areas are stored in buffer 4.
Each area of the image is represented by a binary digit held in bit map store 9, the digits being stored and accessed in the same order as the areas are displayed on the screen. If a digitized area contains one bits, it is represented by a one bit in the bit map store 9, otherwise it is represented by a zero bit. Thus referring to Figure 2C, only the areas I and III of the digitised image are held in buffer 4, the cor-responding bit map in store 9 being 101. In this description it is assumed that the areas are squares of side length 4 picture elements (raster points), but this is to be understood as by way of example only, as, depending on the nature of the image and the storage organisation, other sizes may be used.

108~510 1 The relationship between the image, buffer store 4, and bit map store 9 is further illustrated in Figure 3. Let it be assumed that the image consists of rows of eight 4 x 4 raster point image areas, and that, when digitised, only the second, third and sixth areas (counting from the left) contain ones. The bit map of this row is 01100100. As shown in Figure 3, the digitised image of the row consists of twelve groups of four bits and these are stored in successive storage locations of buffer store 4 which can access four bits at a time. In operation, the first bit of bit map store is accessed and found to be zero. Buffer store 4 is not accessed. Nothing appears on line 7 (Figure 1) and bright-up pulses are not received at CRT 1. At the end of the time taken by the CRT to trace four raster points bit map store 9 is again accessed and a one is detected. This results in buffer store 4 being accessed and the first four bits being supplied to shift register 5 from where they are stepped onto conductor 7 to be received by the CRT and shift register 6. From register 6 the bits are re-entered into buffer store 4. The bit map store 9 is then accessed and a one detected resulting in the readout and regeneration of the second group of four bits. The next access of bit map store 9 provides a zero which does not result in any operation of buffer store 4. After a further zero, a one is read from bit map store 9 which leads to the accessing of the third group of four bits. Two further zeroes complete the bit map of the first row of the image. The bit map store 9 is then caused to access again the eight bi-ts which leads to the readout, at appropriate times, of bit groups 4 to 6 from buffer store 4. The eight bits are accessed twice more before the addressing circuitry selects the next group of bits in the bit map store 9.
The means by which this sequence of operations is achieved is conventional. Addressing circuitry 8 of the buffer store 4 is a counter which increments by one storage location address after each access. The bit read from bit map store 9 into register 10 (a single bistable circuit) is used selectively to activate drive circuits to read out the l bit group held at the address represented by the setting of the counter. If the bit is one the drive circuits are activated. The bit map store accessing circuitry ll includes an n-stage binary counter ll' (Figure 4) of which the lowest three stages represent the address of bits within a group. The next two stages are not used for addressing and the higher order stages following these two stages represent the addresses of different groups of bits. Clearly, if the counter is incremented after each access of the bit map store, the bit address will be cycled four times before the group address -changes. The design of addressing circuitry and of counters to give any required count is described in the well-known books by R.K. Richards, Arithmetic Operations in Digital Computers (especially Chapter 7), and, Digital Computer Components and Circuits (especially Chapters 4 and 8).
Common timing circuits (not shown) of conventional construction control the rate at which the stores 4 and 9 are accessed to be that at which four raster points are traced. Appropriate pauses are included to account for line and frame flyback of the CRT beam.
We now describe how an image is loaded into buffer 4 and is mapped in bit map store 9. The image, or more precisely part of the image, ~O as will be explained, is held in an image store 12 of which one binary storage location represents one raster point and is read se-quentially four bits in parallel at a time to register 6. The bits in register 6 are supplied to an or circuit 13 which manifests a one bit on output line 14 only if any of the inputs to the or circuit 13 is a one, i.e. if register 6 holds a one. The addressing circuitry of bit map store 9 is activated as described above in synchronism with that of image store 12 to store the output of or circuit 13. Operation of the buffer store 4 is prevented while the mapping is taking place. To illustrate how the map is built up consider the bit patterns shown in Figure 2B. The first bit groups of the areas I to III result, re-spectively, in outputs of 1, O, O from or circuit 13 and the storage of 1 these bits in the first three locations of bit map store 9. After the first eight bit positions (in the example being described) of store 9 have been accessed, the addressing circuitry 11 causes them to be-reaccessed synchronously with the supply of the second row of groups of image bits, resulting in outputs of 1, O, 1, from or circuit 13. These are overwritten on the previous contents of the corresponding bit positions. This procedure continues until all four lines of the first row have been passed through the or circuit, after which the addressing circuitry accessed the next eight bit positions. It will be noted that the overwriting ensures that the final contents of the bit map store are correct, since otherwise the group of zeroes in the fourth line of area I would nullify the one bit already written as representing the area.
Overwriting is most conveniently done by reading out the contents of a bit position at access and then rewriting after or-ring with the signal on line 14. During creation of the bit map the contents of image store 12 are regenerated in the store 12. Then, the image is again sequen-tially read out and the bit map is used to control the transfer of information from register 6 to buffer store 4. If the bit map bit is one the contents of register 6 are stored in buffer 4 at the address currently determined by addressing circuitry 8. If the bit map bit is zero, this means that the content of register 6 is zero and writing into store 4 is prevented.
Modifications of parts of the image are effected by transferring the recirculating image by way of a conductor 15 to the image buffer 12.
New image data is supplied by way of line 16 from a host computer. A
new bit map is constructed as has been described.
As has been mentioned above, only part of the image is held in store 12. Clearly, if store 12 is a store remote from the processor providing the images and it were allocated to the storage of the whole image of a single display, the invention merely provides unnecessary hardware as store 12 could be used as the refresh buffer. These are two 1 cases to be taken into account: either the display is interactive or it is not. If the display is not interactive, store 12 and the conductor 15 is not required, and the images are supplied from a host processor.
If the display is interactive, there is the need to supply to the host processor the modified images. It is convenient to operate in quarter images - a method of storage is described later - and if store 12 is supplying one display it need only be of a size to contain quarter images. Alternatively, the store 12 can be arranged to hold a plurality of different quarter images, either different colour images for one display or different images for different displays.
The invention lends itself readily to the provision of display features, for example the ability to display certain objects as flashing on the screen. Figure 5 shows an arrangement for achieving this. As well as the normal buffer store 4, output register and serializer 5 connected to the CRT over conductor 7, addressing circuitry 8 and bit map store 9 all operated and connected as described with reference to Figure 1, there is provided an additional buffer store with input and output registers 16, 17, respectively, and addressing circuitry 18 controlled by a bit map store 19 which has its own addressing circuitry 20. The only difference in operation between buffer store 15 and 4 and the respective associated bit map stores is that a timing generator 21 so controls the rate at which information is read from buffer 15 and bit map store 19 that the resultant image is caused to flash on the screen.
The object which is flashed is supplied to buffer store 15 independently of the image in buffer store 4 by means of a data bus 22 connected to the host computer. Buffer store 15 is much smaller than buffer store 4 since the amount of information required to define objects to be flashed will be substantially less than that required to define the whole image.
Other features which can be provided by simple replication of the buffer store 4 and bit map 9 arrangement include control of a colour display. The display can be a simple two or three colour display in which case respective buffer stores are allotted to each colour image or 108~510 1 can be a display using predetermined combinations of three primary colours in which case three buffer stores are allotted each to one bit of a three bit code. The respective bits are separately mapped, each as described with reference to Figure 1. The three bits are interpreted at the CRT as defining either no bright-up or one of seven colours.
As was mentioned in the preamble to this specification, the amount --of information required to define an image is very large. It is con-venient for many purposes to operate in terms of quarter images, i.e. if the image consists of six hundred lines the quarter images would be 1~ lines 1 - 150, 151 - 300, 301 - 450, and 451 to 600, respectively. Thisscheme can be adopted in buffer 4 with suitable modification of the addressing circuitry. If it is assumed that buffer 4 consists of N
address locations (Figure 6), the first and second quarters of the image are assigned to locations 1 to N/2 and the third and fourth quarters are assigned to locations ~N/2) ~ 1 to N. The first quarter is loaded starting at location 1, the second quarter is loaded starting at loca-tion N/2 and continuing at (N/2) -1, ~N/2) -2, and so on, the third quarter is loaded starting at location (N/2) ~ 1, and the fourth quarter is loaded starting at location N and continuing at N-l, N-2, and so on, all as indicated by the arrows in Figure 6. This storage scheme is more flexible than assigning a quarter of the store rigidly to each quarter image, and easier to implement than allowing quarter images to follow directly after each other in the store, since an automatic starting address is provided for each quarter image. The addressing circuitry 8 (Figure 1) is modified by causing it to jump to the start address of the next quarter image and then incrementing or decrementing as required, when an end of quarter image indication is detected.
A particularly efficient application of the invention is the refreshing of images of which each raster point can, if illuminated, have two intensities of illumination. The bit map stores and addressing circuitry is duplicated but the two different intensity images are both stored in buffer store 4, one starting at the lowest address, and the ~085S10 1 other, at the highest. An extra register 5 and conductor path 7, 3, is also provided. Pulses in the respective paths are interpreted at the display device as defining respective different brightness levels.
Although certain of the described embodiments have related to an image in which white lines are superimposed on a black background, the invention can equally be applied to black white images in which case all black image areas represented by all ones are excluded from the buffer 4, and the shift register 5 is arranged to output ones in the absence of other data.

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Refresh circuitry for recording a digital representation of an image to be displayed on a transient display device wherein the display surface of said display device is subdivided into a plurality of digital image areas, said refresh circuitry comprising:
a first store for storing a digital indicator for each image area, said digital indicator being of one value where an area includes data bits of one type and being of another value where said area does not include bits of said one type;
a second store for storing a complete digital representation of each image area containing data bits of said one type, and data stream generating means for generating a data stream repre-sentative of said image to be displayed, said generating means sequentially reading out the indicators for each image area stored in said first store and generating a data stream by reading out the digital repre-sentation of the corresponding image area stored in said second store when said indicator stored in said first store is of said one value and generating a stream of bits of another type when said indicator stored in said first store is of said other value.

2. Refresh circuitry as claimed in claim 1, wherein said second store includes address circuitry arranged to sequentially access storage locations in said second store, and said data stream generating means is operative to inhibit operation of said address circuitry in response to readout of a bit of said other value from said first store, and to supply said data stream with a group of bits of said other type. When said address circuitry is so inhibited.

3. Refresh circuitry as claimed in claim 1, wherein said data stream consists of a plurality of digital images each consisting of equal digital image areas, said second store stores only those digital image areas which contain bits of said one type, and said second store con-tains for each digital image area of each digital image a bit, the value of which indicates whether the digital image area contains bits of a said one type.

4. Refresh circuitry as claimed in claim 2, wherein said data stream consists of a plurality of digital images each consisting of equal digital image areas, said second store stores only those digital image areas which contain bits of said one type, and said second store con-tains for each digital image area of each digital image a bit, the value of which indicates whether the digital image area contains bits of a said one type.

5. Refresh circuitry as claimed in claim 3 or claim 4, wherein said data stream generating means generates a data stream consisting of a selected one of said digital images.

6. Refresh circuitry as claimed in claim 3 or claim 4, wherein said data stream generating means generates a data stream consisting of said digital images in parallel.