CA1082469A - System for controlling the striking mechanism of a timepiece - Google Patents
System for controlling the striking mechanism of a timepieceInfo
- Publication number
- CA1082469A CA1082469A CA273,686A CA273686A CA1082469A CA 1082469 A CA1082469 A CA 1082469A CA 273686 A CA273686 A CA 273686A CA 1082469 A CA1082469 A CA 1082469A
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- 230000007246 mechanism Effects 0.000 claims abstract description 26
- 239000004020 conductor Substances 0.000 claims description 17
- 230000000295 complement effect Effects 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 2
- 230000003213 activating effect Effects 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000009826 distribution Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000008859 change Effects 0.000 description 3
- 210000002105 tongue Anatomy 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 101100006982 Mus musculus Ppcdc gene Proteins 0.000 description 1
- 101100410811 Mus musculus Pxt1 gene Proteins 0.000 description 1
- 235000006629 Prosopis spicigera Nutrition 0.000 description 1
- 240000000037 Prosopis spicigera Species 0.000 description 1
- 108010076504 Protein Sorting Signals Proteins 0.000 description 1
- 101100173636 Rattus norvegicus Fhl2 gene Proteins 0.000 description 1
- 101100128280 Sphingobium japonicum (strain DSM 16413 / CCM 7287 / MTCC 6362 / UT26 / NBRC 101211 / UT26S) linF gene Proteins 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000002301 combined effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000002674 ointment Substances 0.000 description 1
- 230000003334 potential effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G13/00—Producing acoustic time signals
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Electromechanical Clocks (AREA)
- Electric Clocks (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A first contact arm on the minute shaft of a clock-work switches, once every 30 minutes, the mode of energization of an electronic gating circuit with two sectlons in the inputs of an inverting anticoincidence (NOXOR) gate working into a set-ting input of a flip-flop which controls the driving circuit of a striking mechanism, each section having two parallel branches of relatively inverting character and with a relative phase de-lay whereby any switchover results in a brief de-energlzation of that setting input and thus in a setting of the flip-flop.
A pulse generator, included in or energized by the driving cir-cuit, works into a stepping input of a binary pulse counter pro-vided with four output leads whose pattern of enerqization re-presents the numerical values from 1 through 12. A logic net-work, connected to a resetting input of the flip-flop and to a clearing input of the pulse counter, discriminates between switch-overs at the full hour and at the half-hour in response to the state of energization of the gating circuit; on the half-hour, the flip-flop is reset and the pulse counter is cleared upon the energization of the No. 1 output lead of the counter, whereas on the full hour these events take place under the control of a second contact arm carried on the hour shaft of the clockwork whenever the pulse count matches the position of that contact arm.
A first contact arm on the minute shaft of a clock-work switches, once every 30 minutes, the mode of energization of an electronic gating circuit with two sectlons in the inputs of an inverting anticoincidence (NOXOR) gate working into a set-ting input of a flip-flop which controls the driving circuit of a striking mechanism, each section having two parallel branches of relatively inverting character and with a relative phase de-lay whereby any switchover results in a brief de-energlzation of that setting input and thus in a setting of the flip-flop.
A pulse generator, included in or energized by the driving cir-cuit, works into a stepping input of a binary pulse counter pro-vided with four output leads whose pattern of enerqization re-presents the numerical values from 1 through 12. A logic net-work, connected to a resetting input of the flip-flop and to a clearing input of the pulse counter, discriminates between switch-overs at the full hour and at the half-hour in response to the state of energization of the gating circuit; on the half-hour, the flip-flop is reset and the pulse counter is cleared upon the energization of the No. 1 output lead of the counter, whereas on the full hour these events take place under the control of a second contact arm carried on the hour shaft of the clockwork whenever the pulse count matches the position of that contact arm.
Description
~9o ~o~ s SPECIFICATION
The present invention relate~ to an electronic system for the control of a str~king mechani~m in a timepiece, preferably an electric clock of the crystal--eontrolled type.
,' m e sounding of the hour by a variable number of ~trikes~ and possibly also of the hal~-hour by a single st~ike, i8 conventionally accomplished with the aid of a ; trigger actuated by the minute shaft of the cloekwork.
The number of strikes is determined by a mechanieal eounter ~ whieh usually e~mprise~ a toothed segment or raek displaeed 3 b~ a~ hour eam befor~ eseh striking operation, the ca~
being tri~en b~ the hour shat of the eloekwork and having a genRrally spiral ramp ~urfaee composed of diserete dwells ~ of different radii which advanee the esm to a different ¦ e~tent from its bome positio~. A solenoid-operated pawl retraets the raek, one tooth at a time, during th~ eseeution of the strikes; when the raek retu D to its hom~ position, the oparation is~topped. Before the half-hour, th- eam i~
advanead by ~ust one tooth regardless of the position of , th~ hour eam.
1~ .
5ueh a~ eleetr~eally operated str~king meehaai~m, J: origi~ally intended mai~ly for tower eloe~s, has a large .1 number of ~ovable parts and is too bulky for uso in more eompaet timepieee~; it i~ al~o ~ub~eet to malfunctioa~ dua to wear.
.d~
,~
The ob~ect of the present ~nvention, accordingly, i8 to provide a more compact system ~or the control of an electric striking mechanism which has few moving parts, does not require any mechanical or electromechanical prime mover and i8 positively coupled wlth the clockwork so that its operation i8 unequivocally tied in with the position of the clock hands. Thus, an ad~ustment of the setting of the timepiece should not have~any effec~ upon the synchroni-zation between the time indication and the operatioa of the st~iking mechanism.
:, :
This ob~ect i~ realized, in accordanee with the present invention by the provision of a normally reset flip--flop with a set output connected to drive means for operating the stri~ing mechanism, trigger m~ans ineluding a first rotat~ng eontact Dember coupled with the minute shaft of the eloekwork for deliveri~g a start ~lgnal to the setting input of the flip-flop at lea~t onee per hour to activate the drive mean~, eleetronie pulsing means sgnchronized with the striking . meehan~sm ~or emitting a number of voltage pulses proportional '20 (and preferably equal) to the number of strike~, and a pulse . eounter with a stepp~ng input eoDnected to the pulsing means -` and with output cireuitry including a set of leads generatin8 a pattern of energization determined by the count of the voltage pul~es; this output elrcuitry forms part of deaetivatlng ~eans also ineluding a seeond rotating eontact m~mber coupled with the hour ~haft for deliver~ng a stop signal tc the resetting input of the flip-flop ant to a clearing input of th~ pu15~ :
The present invention relate~ to an electronic system for the control of a str~king mechani~m in a timepiece, preferably an electric clock of the crystal--eontrolled type.
,' m e sounding of the hour by a variable number of ~trikes~ and possibly also of the hal~-hour by a single st~ike, i8 conventionally accomplished with the aid of a ; trigger actuated by the minute shaft of the cloekwork.
The number of strikes is determined by a mechanieal eounter ~ whieh usually e~mprise~ a toothed segment or raek displaeed 3 b~ a~ hour eam befor~ eseh striking operation, the ca~
being tri~en b~ the hour shat of the eloekwork and having a genRrally spiral ramp ~urfaee composed of diserete dwells ~ of different radii which advanee the esm to a different ¦ e~tent from its bome positio~. A solenoid-operated pawl retraets the raek, one tooth at a time, during th~ eseeution of the strikes; when the raek retu D to its hom~ position, the oparation is~topped. Before the half-hour, th- eam i~
advanead by ~ust one tooth regardless of the position of , th~ hour eam.
1~ .
5ueh a~ eleetr~eally operated str~king meehaai~m, J: origi~ally intended mai~ly for tower eloe~s, has a large .1 number of ~ovable parts and is too bulky for uso in more eompaet timepieee~; it i~ al~o ~ub~eet to malfunctioa~ dua to wear.
.d~
,~
The ob~ect of the present ~nvention, accordingly, i8 to provide a more compact system ~or the control of an electric striking mechanism which has few moving parts, does not require any mechanical or electromechanical prime mover and i8 positively coupled wlth the clockwork so that its operation i8 unequivocally tied in with the position of the clock hands. Thus, an ad~ustment of the setting of the timepiece should not have~any effec~ upon the synchroni-zation between the time indication and the operatioa of the st~iking mechanism.
:, :
This ob~ect i~ realized, in accordanee with the present invention by the provision of a normally reset flip--flop with a set output connected to drive means for operating the stri~ing mechanism, trigger m~ans ineluding a first rotat~ng eontact Dember coupled with the minute shaft of the eloekwork for deliveri~g a start ~lgnal to the setting input of the flip-flop at lea~t onee per hour to activate the drive mean~, eleetronie pulsing means sgnchronized with the striking . meehan~sm ~or emitting a number of voltage pulses proportional '20 (and preferably equal) to the number of strike~, and a pulse . eounter with a stepp~ng input eoDnected to the pulsing means -` and with output cireuitry including a set of leads generatin8 a pattern of energization determined by the count of the voltage pul~es; this output elrcuitry forms part of deaetivatlng ~eans also ineluding a seeond rotating eontact m~mber coupled with the hour ~haft for deliver~ng a stop signal tc the resetting input of the flip-flop ant to a clearing input of th~ pu15~ :
-2-~o~ 9 counter upon the pattern of energ~zation of the SQt of leads in the output circuitry of that counb3rbears a predetermined relationship with the position of the hour shaft, thereby arresting the striking mechanism and establishing a zero pul~e count.
If the half-hour is also to be sounded, the trigger mean~ comprises an electronic gating circuit which is switch-able by the first contact member in a half-hour position and in a full-hour position thereof, the deactivating means further including a logic network connected to the gating circuit ~or generating the stop slgnal independently of ~-the position of the hour shaft coinciding with the half--hour position of the minute shaft. Thus, the logic netw~rk may comprise a first gate and a secoDd gate in csscade, the first gate ha~ing input connectioD~to the gating circuit a~d to the lead which is energized by the pulse counter upon i the sounding of the first strike, the second gate hav~ng an ... ..
input connection to a point of the output circuitry of the pul~e ¢ounter whose potential changes whene~er the pattern of energization of the counter-output lead~ bears the afore-mention~d predetermined relatioDsh~p with the position of the hour shsft. m at pattern of energization may be the marking o~ onR of 12 such output l~ads, connected to the counter via a decoding network; if the le~d~ emanate directly from the ~tage outputs of the binary counter, that relation-ship may be the matching of the code of the binary count with a complementary (or possibly identical) four-bit code ; e8tabliBhed by the coactio~ o~ the second contact member with
If the half-hour is also to be sounded, the trigger mean~ comprises an electronic gating circuit which is switch-able by the first contact member in a half-hour position and in a full-hour position thereof, the deactivating means further including a logic network connected to the gating circuit ~or generating the stop slgnal independently of ~-the position of the hour shaft coinciding with the half--hour position of the minute shaft. Thus, the logic netw~rk may comprise a first gate and a secoDd gate in csscade, the first gate ha~ing input connectioD~to the gating circuit a~d to the lead which is energized by the pulse counter upon i the sounding of the first strike, the second gate hav~ng an ... ..
input connection to a point of the output circuitry of the pul~e ¢ounter whose potential changes whene~er the pattern of energization of the counter-output lead~ bears the afore-mention~d predetermined relatioDsh~p with the position of the hour shsft. m at pattern of energization may be the marking o~ onR of 12 such output l~ads, connected to the counter via a decoding network; if the le~d~ emanate directly from the ~tage outputs of the binary counter, that relation-ship may be the matching of the code of the binary count with a complementary (or possibly identical) four-bit code ; e8tabliBhed by the coactio~ o~ the second contact member with
-3 ~ 8 ~ ~tX9 four eoneentric eontact arcs, three of them segmented.
Sueh a mateh can be detected by a comparis m ~ network eomprising four diseriminating stages, designed as E~elusive-OR (XOR) gates in the ease of complementary codes, w~rking into a common coincidenee (AND~ NAND or N0R) gate.
Aeeording to another important feature of the invention, the gating eircuit eonneeted to the setting input of the flip-flop eompriseR two substantially identical seetions terminating at respeetive inputs of an antieoin-eidenee gate of the Exelusive-OR typa, eaeh of these seetions being divided into a pair of parallel branehes of relatively invcrting eharaeter and with a relative phase delay whieh are eonneeted to the respeetive iDpUt of the antieoincidenee gate through a further logie gate whieh ehanges its state of eonduetion, in re~ponse to a switehover by the fir~t eontaet member, during a brief interval determined by that phase delay Ln whieh the two branehes earry signals of identieal logieal values. Depending upon the mode of eonnection of I the gating eireuit to the bank eontaet or contaets eoaeting with the f~rs~ eontaet member, as wlll beeome apparent herei~after, the further logie gate in eaeh of its seetions i may be either a ~umming (OR) gate or a coin~idenee (NAND) gate.
i Advantsgeously, the relativê ~nversion and phase dela~ i8 brought about by an odd number ~pre~erably three) of easeaded isverters in o~e of the branehes.
Sueh a mateh can be detected by a comparis m ~ network eomprising four diseriminating stages, designed as E~elusive-OR (XOR) gates in the ease of complementary codes, w~rking into a common coincidenee (AND~ NAND or N0R) gate.
Aeeording to another important feature of the invention, the gating eircuit eonneeted to the setting input of the flip-flop eompriseR two substantially identical seetions terminating at respeetive inputs of an antieoin-eidenee gate of the Exelusive-OR typa, eaeh of these seetions being divided into a pair of parallel branehes of relatively invcrting eharaeter and with a relative phase delay whieh are eonneeted to the respeetive iDpUt of the antieoincidenee gate through a further logie gate whieh ehanges its state of eonduetion, in re~ponse to a switehover by the fir~t eontaet member, during a brief interval determined by that phase delay Ln whieh the two branehes earry signals of identieal logieal values. Depending upon the mode of eonnection of I the gating eireuit to the bank eontaet or contaets eoaeting with the f~rs~ eontaet member, as wlll beeome apparent herei~after, the further logie gate in eaeh of its seetions i may be either a ~umming (OR) gate or a coin~idenee (NAND) gate.
i Advantsgeously, the relativê ~nversion and phase dela~ i8 brought about by an odd number ~pre~erably three) of easeaded isverters in o~e of the branehes.
-4-~ 8 ~ 4~9 The bank contscts coac~g with the tWD rotating contact members may be printed on a carrler plate traversed by the nested minute and hour shAfts on which the~e contact members are mounted directly.
If desired, a circuit breaker may be provided which iB controlled b~ the clockwork for disabling the drive means for the ~triking mechani~m during certain night-time hours, eOg. for an 8-hour period startlng at 11 Pff (2300 hours). Such a circuit breaker could prevent, ~0 for example, a switchover of the afordescribed gating circuit.
., ~; .
., ;, ~ -5-10824~9 9~ J~ri.ef ~escri t~tion Or thc Dral~linF
The above an~ other features of the invention will now be described in detail with reference to the accompanying drawinz in which: :-Fig. 1 is a circuit diagram of a system for the control of an electrical strikin~ mechanism representing a first embodiment of the invention;
Figs. 2 - 5 show part of the Gircuit diagram of ~ig.l '. -in fou.r different phases of operation;
~igs. ~ and 7 show another part of the circuit diagram LO of ~'ig. 1 in two different phases of operation;
~ig. 8 is a set of ~raphs showing the state of energization of various components of the system of ~ig. 1 -~ -during a one-hour operating cycle;
Fig. 9 is a cross-sectional view of part of a clock-~5 ~iork with members forming part of the system of Fig. 1;
Fig. 9a is a face view of one of the cont~ct members of Fig. 9;
: ~ig. 9b is a face view of another contact member shown in Fig. 9; ~ -Fig. 10 is a view similar to Fig. 9, showing a modi-ication;
1. ~ig. 11 is a bl.ock diagram of a control system ~-¦:~:1 representing a second embodiment of the invention;
ig. 12 iæ a circuit diagram similar to Fig. 1 but relating to this secona embodimen~;
Figs. 13 and 14 show p~rtial modifications o~ the system of Fig. 12;
igs. 15a - 15f show part of the circuit diagram of ~ig. 12 in six different phases of operation;
., .
~ 108Z469 Fig. 16 is an enlarge~ detail view of a contact assembly included in the sys-tcm of ~ig. 12;
~ig. 17 is a code diag~rar~ for the e~bodi~ent of ~i~s. 11 - 1~; and l~ig. 18 is a set of graphs similar to ~ig. 8 but relating to the second e~bodi~ent.
Specific Descr ~tion .
~ig. 1 shows a minute shaft 1 of a con~entional clockwork ~Jhich actuates a switch 2 comprisin~ a contact member 3 rotating with the minute shaft 1, designed as a O wiper; contact member 3 sweeps an arcuate bank contact 4 during the ~O-minute interval between half-hour and full hour.
~ank contact 4 is printed on a carrier plate 132 (~ig. 9) within the cloc~work controlling the eiectrical striking mechanism pursuant to the invention.
, The switch 2 is so positioned in relation to the ; minute hand (not sho~) mounted on shaft 1 that the wiper ~ wili ,; ~ .
arrive at the bank contact 4 exactly at the beginning ol the 8econd half hour, i.e. exactly at X30 o'clock, touching it an~
consequently closing the switch. ~he wiper 3 is permanently connected, as by a sliding contact, to a point o~ fixed potential (ground) of lo~ical value "O". ~ank contact 4, on the other hand~ is connecte~ to a source of potential of lo~ical value "1"
(designated by ~) via a resistor 5.
.. ~ .
Two sections of a gating circuit including a pair o~
~5 ~ ~hN~ gates 6 and 7 are connected in pa~allel to ban~ con-tact ~.
ND ~ate 7 has an input 8 connec~ed directly to a line 9, tied ... ,: ~, -_ 7 --.~ ~ - , ,. . . . ..
^ ~08Z469 0 to that bank contact, and an input 10 connec-~ed ~o a junction point 14 on line 9 by way of three cascaded inverters 11, 12 and 13 also having a delay function.
Similarlyt three cascaded inverters 15, 17 and 18 are inserted between an input 15 of NAND gate 6 and a junction point 19 tied to the other input 20 of the same NA~ID gate 6.
An additional inverter 21 lies between junction point 19 and bank contact 4.
~ig. 2 shows the signal distributions at various 0 points of the gating circuit controlled by switch 2, as it exists a short time before the initiation of the half-hour strike, i.e. at about ~25 o'cloc~ In this state, the signal L
prevails at the outputs 22, 23 of the two NAND ~ates ~, 7.
Fig. 3 shows the state of the circuit at the moment .5 the half-hour strike is initiated,i.e. exactly at ~ o'cloc~.
As a result of the inverters 16 - 18 and 11 - 13, phase delays ~:~ occur at the moment of switchover at X30 o'clock, i.e. when the switch 2 is closed, making the voltag~s at the inputs 15, 10 of the two NAND gates 6, 7 briefly e~ual to thosé of their b~ inpu~s 20 and 8, respecti~ely. As a consequence, at the ~; , ,._ . -moment the circuit between contact members 3 and l~ is closed, - the signal co~dition shown in Fig. 3 prevails for a short period with N~N~ gate 6 cut off.
hus, at instant X30 the signal 0/~ occurs at the outputs 22, 23 of the two N~D ~ates 6, 7, while according to . ~ .
'' 3X46~
-~ig. 2 the signal pair ~/L e~isted at those outputs up to tllen.
q'he signal conditions sho~m in Fig. 3 are maintained only for an extremely short time which is sufficient, ho~ever, to effect the switching processes described belo~J.
At the end of this brief interval, thus sho~tly after ; X30 o~clock, the signal sequence sho~ in ~ig. 4 occurs. This means that, with switch 2 still closed, the signal pair ~/~
reappears at the outputs 22, 23 of the two NA~D gates.
At X60 o'clock = (~ ~ 1) o'clock, the contact ~ member 3 of switch 2 leaves the arc 4, i.e. the switch is re-opened. With the recurrence of the aforedescribed phase delay, the signal distribution shown i~ Fig. 5 occurs briefly at the full hour. In this case, therefore, thP signal pair ~/0 appears at the outputs 22, 23, of the two NAND g~tes 6, 7.
It is evident from the foregoing tha~ at the l.loment the switch 2 is reversed, i.e. closed or opened, opposite ,, .
signals appear at the outputs 22, 23 of the two ~AND gates whereas identical signal pairs eYist there in the inte~mediate positions. According to a feature of the present invention, the emergence of unequal signals at the outputs of the I~7~7~ gates 6, 7 serves as a starti~g criterion for the activation of the electrical striking mechanism. ~or this purpose, a further ~ iogical relationship is required pursuant to the follo~Jing ~able.
; , -_ 9 _ .'' ~' ' .
)190 ~ 4f~9 TABLE S
NAND gate 6 NAND gate 7 Y Time range and, respectively, (output 22) (output 23) ~oint of time L L O X _ X30 X30 _ X60, (X ~ 1) L O L X , X~O , (X + 1~
O 0 O does not appear at any time (A) (B) Y hours/minutes .O In the Table, Y represents a start signal (ac-tually a complement thereof) satisfying the Boolean relationship B + AB = y which is the function of an Exclusive-OR (XOR) gate or anticoin-~idence circuit.
In accordance with a further feature of the in- --vRntion, the start signal generated by the switch 2 at X30 o'clock and ~t X~O? o'clock is fed to the setting input S of a flip-flop ~ ~O, here shown to comprise two cross-connected NAND gates 45, :
;.( 46. Such a circuit requires as a setting signal a logical "O"
;~o which is obtained, advantageously, by a negation of the above function:
. ~ .
y = A B + AB = A B AB
`.~ This logical function is performed by an invert1ng anticoincidence . ~, circuit also known as a NOXOR gate.
:
,,,, -' , !_ 10 -.
go ~ 469 This circuit comprises two inverters 30, 31 which are connected in series to the outputs 22, 23 of the NAND gates 6, 7 and work into respective inputs 34, 35 of two NAND gates 32, 33, whose two other inputs 36, 37, are tied directly to outputs 23 , and 22 respectively.
The outputs 38, 39 of the two NAND gates 32, 33 are combined in an AND ~ate 40 whose output 41 is connected to the setting input S of flip-flop 50.
FIG 6 illustrates the signal distribution along 0 the linkages of the NOXOR gate 30 - 33, 40 which results when unequal signals emitted by the NAND gates 6, 7 are applied to its inputs 22, 23. In this c~se, the signal L appears at the output of the AND gate 40 and at the input S of the NAND gate 45 of the flip-flop 50, i.e. the flip-flop 50 remains reset and its out-put 51 is not energized. If, however, a pair of unequal signals ¦ appear at the connections 22, 23, i.e. L/0 or 0/L, the signal distribution illustrated in FIG. 7 results, i.e. the signal 0 appears at the output of AND gate 40, resulting in a setting of the fl~.p-flop 50 and energization of output 51 which in turn umblocks a power transistor 53 feeding a drive motor ~ to ac-tuate the associated striking mechanism (not shown in these Figures). As a result, the sound generator of this mechanism begins to produce a series of strikes.
The sound ~enerator can comprise a conYentional bell, ~S gong tube or spiral gong. Strings of electronic oscillators could also be used. Another possibility is the provision of a .
:
iO8Z4~;9 mechanical tuning fork excited intermittently by the striker for conductively transmitting its audio frequencies to an amplifier for the energization of an electro-accoustic transducer.
A switch 56 has an arm 63 driven by motor 55 for alternately grounding two contacts 57, 58, thereby periodically setting and resetting a f~ip-flop 60 as long as the motor is energized. Flip-flop 60 serves to step a binary electronic counter 70 and insures that exactly one pulse per strike is transtnitted to.that counter. It consists of two cross-connected NAND gates D 61, 62; output 71 of gate 61 is connected to a stepping input 73 of counter 70 by way of a lead 72 In the well-known manner, this binary counter stores the pulse generated with each strike of the sounding mechanism and converts its count into a binary code which appears on four stage~.; outputs 75 - 78. This binary code is translated l~y a binary-decima~ decoder 80, connected to outputs 75 - 78, into a marking (i.e~ grounding) of one of ten output terminals 0 - IX
which normally carry signal voltage L. Terminal 0 is grounded in the cleared state of counter 70. ..
In decoder 80, therefore, nine terminals I - IX
are available for the counting of strikes. However, since up to 12 ~-3 strikes have to be counted, the NAND gates conventionally present .
.~¦ within the decoder are supplemented by three further NAND gates ~ 81, 82 and 83 with output terminals X, XI and XII.
-I
,3 The outpuc I of the binary-decimal decoder 80 is con-: nected to an input 91 of a NAND gate 95 by a ~ine 85 including an inverter 90. The other input 92 of this NAND gate 95 is tied to ^ the junction of inverters 13 and 12 which form part of one of the circuit branches feeding bhe NAND gate 7.
-- 12 _ 10 8 ~ 4 ~ 9 After the half-hour strike has been triggered by the switch 2 and a puls~ .has been transmitted to the binary counter 70 by the flip-flop 60, the pattern of energization of the outputs 75 - 78 is changed from 0000 to 0001, whereupon the signal L appears at the output 0 of decoder 80 while the signal L is replaced at the adjacent output I by the signal 0 (positive logic being assumed in this case)0 e signal 0 is fed to the inverter 90 by line 85 and its complement L ~8 thus delivered to the input 91 of NAND gate 95.
Since, however, bank contact 4 i8 grounded at this moment also by the wiper srm 3, the signal L appears also at the input 92 of NAND gate 95 which therefore switches fts output 96 to signal 0. :~
At the time of the hslf-hour strike a contact arm or wiper 101 forming part of a switch 102 snd rotating with the hour shaft 100 of the c~ockwork i8 located in a position between two tecoter terminals I ... XII and iB energized with signsl L vis a resistor 105. An inverter 103 tied to wiper 101 then grounds an input 106 of a NAND gate llO having another input 107 connected to ~unction point 14 which is al80 grounted 80 thst NAND gate 110 nss an output signal L
Thu8, unlike signals are found at outputs 96 and 97 of the two NAND gates 95 and 110 which constitute respective inputs of an inverting ant~coincidence ~NQXQR~ gste analogously to the one working into setting input S of flip-flop 50. Thi8 second NoX0 gate comprises two inverters 111, 112, two NAND gates 113, 114 and an AND gate 115. Unequal signals at the two outputs 96, 97 -~3_ ' 10824~
of the two NAND gates 95~ 110 produce an O-signal at the output 116 of AND gate llS which is tied to a resetting input R of the flip-flop 50. This results in a de-energiza-tion of line 51 and stops the drive motor SS by cutting off its supply transistor 53. Motor 55 is designed to come to a halt in a position in which the sw~tch arm 63 has reset the flip-flop 60. The flip-flop 50 does not switch over again until the signal O reappears~ at its setting input S~
regardless of the potential of its resetting input R. The output 116 of AND gate 115 is further connected by a lead 117 to a clearing input 74 of the binary counter 70 which therefore registers a zero count upon the resetting of flip-flop 50 so that signal L appears again at decoder output I.
~l 15 As a res~lt~ NAND gate 9S conducts and switches the , NOXOR gate 111 - 115, causing the signal L to reappear at its output 116; this change in signals~ however~ has no effect on the state of flip-flop 50 which remains reset.
During the execution of the hour strikes~ the wiper 101 of the switch 102 engages one of the outputs I - XII of decoding circuit 80 - 83 in accordance with the position of the hour hand of the clock mechanism. The wiper 101 is therefore electrically connected to the respective decoder output.
¦ 25 The start of the stri~ing operation for the hours occurs in the manner already descri~ed with reference to _14-:' , 10190 lOBZ4~9 FIGS. 5 and 6.
Durtng the hour strike~ the contact arc 4 ~ust dis-engaged by arm 3 applies signal L by way of line 9 to the lnput 107 of NAND gate 110 whose other input 106 is initially maintained ~y inverter 103 at signal level 0. The nonidenti-cal signals O/L at the inputs 106 and 107 of NAND gate 110 lead to an L-signal at the output 97 of this gate. At the same time~ an O~signal lies at the input 91 of NAND gate 95 because of the L-signal at decoder output I. An O-signal also appears at the input 92 of NAND gate 95~ resulting in a signal L at its output 96.
Therefore~ both outputs 96~ 97 exhibit L-signal and the NOXOR gate 111 - 115 ineffectually enerqizes lts oùtput 116 with an L-signal. As soon as the pulse count matches the lS position of wiper 101~ the ground~ng of the decoder terminal engaged by the wiper applie~ signal L to the input 106 of NAND gate 110~ resulting in a changeover of the output 97 to slgnal 0. Thi~ produce~ unequal signals at the inputs of `, NOXOR qate 111 - 115, giving rise to the stop signal O on 1, 20 resetting input R of flip-flop 50 and on clearing input 74 of ,'l binary counter 70~ thereby arresting the striking mechanism.
;~ The ~ode of energization of the logic elements parti-, .
^~ cipating in the operating cycle ~ust described has been out-;~ lined in FIG. 8.
FIG. 9 shows a specific construction of the switches 2~ 101 of FIG. 1 incorporated in the clockwork.
'' "'I
~ ~?~i The minute shaft 1~ hour shaft 100 and second-hand '. 1 ~ r,.
~ _15--.. . ~
,.
.. . .
- ~08Z46~
o~so - shaft 122 of the clockwor~ project through a clock dial 121 in their usual nested relationship. The minute shaft 1 carries a pinion 123; the hour shaft 100 is rigidly connected with a gear 124. Pinion 123 engages a gear 125 which is S rigid with a pinion 126 in mesh with gear 124. A stud 127 carrying gears 125~ 126 is mounted on a plate 130 which~ -together with another plate 131 and a set of connecting bolts 129~ forms part of a frame holding the clock mechanism.
A printed-circuit board~ constituting the aforemen-''! 10 tioned carrier plate 132~ is arranged between the plate 130 , and the dial 121. This printed-circuit board 132 is penetra-s ted by the minute shaft 1 and the pinions 123 and 126; gear ~ 124 lies between the printed-circuit board 132 and the dial -~ 121.
lS An extension 133 of pinion 123 carries the contact arm 3 between the hoard 132 and the gear 124. The contact arm 3 i~ designod as a resilient wiper (blade) 134 and scans J th- contact arc 4 on the board 132. This blade 134 is rigid-ly connected with pinion 123 and rotates together with the 3 20 latter. The blade 134 carries two resilient heads 135~ 136 head 135 scanning the contact arc 4 whirh extends over an angular range of 180 in the area of X30 _ X60~ i.e. over a path of 30 minutes. The other head 136 scans another contact arc connected to ground potential 0~ the latter arc being also carried on the board 132 and extending over a somewhat larger ang}e~ e.g. of about 200 .
~he gear 124 is made of an insulating material~ prefer-ably a plastic. It carries the wiper blade 101 of the switch _16-10190 lO~Z4~;9 102, that blade being also provided with two resilient heads 137, 138 which scan respective conductor banks on the printed--circuit board 132. ~he blade 101 extends beyond pinion 126 so that a full range of 360 is available for the scanning S of its conductor banks printed on the board.
The assembly shown in FIG. 9 permits a compact design of the control assembly for the electrical strikin~ mechanism ; pursuant to the invention. Essential components 139~ 140 of the electronic control circuit and of the clockwork itself ~such as a crystal-controlled oscillator) may be arranged on the board 132 and can be connected with the remainder of the circuit by way of their printed conductors.
The arrangement according to FIG. 9 is particularly suitable for flat timepieces.
A modified mounting for switches 2~ 102 has been illustrated in FIG. 10. In this instance~ a printed-circuit board 132~ i8 provided with conductor arrays on both sides.
The blade 134~ of contact member 3~ carrying heads 135~ 136~
i~ now arranged between pinion 123 and the board 132~ and scans ban~ contacts disposed on the side of the printed-circuit board remote from gear 124. The blade 101~ on the other hand~ is arranged between the printed-circuit board 132t and the gear 124~ rotating with the latter and carrying heads 137~, 138' - scanning contact banks which form the terminals I - XII, spaced 30 apart~ and a connection to res~stor 10~ and in-verter 103 ~FIG. 1). --The assembly of FIG. 10 is particularly suitable for .
,`~
, .
` , ~ " f = . - . ~
- , . .. . .. . . . . . .
0190 ~08Z~
use in timepieces of relatively small diameter.
FIGS. 9a and 9b are face views of contact members 101~ 137~ 138 and 134 - 136 of the two switches 2~ 102.
FIG. 11 shows the overall layout of a system generally S similar to the one just described but representing a second embodiment.
A clockwork 201 actuates~ by its minute shaft~ a trigger switch 202 which periodically activates~ at the full hour and at the half-hour~ an electronic gating circuit 203 to apply a start signal to an electronic control unit 204;
this control unit thereupon activates a drive unit 205 for the operation of a striking mechanism 206. A strike may con-sist of a single note or a sequence of notes.
With each strike~ an electronic pulse emitter 207 is ca w ed to transmit a counting pulse to a binary counter 208.
e reading of counter 208 is confronted by an electronic , comparator 209 with the output of a coder 210 coupled with the hour shaft of the clockwork 201. When the comparator 209 detects a match ~etween the readings of position coder 210 and counter 208~ it emits a pulse which deactivates the drive unit 205 via control unit 204 and also clears the electronic counter 208.
FIG. 12 shows details of the system of FIG. 11.
The ~inute shaft 211 of clockwork 201 carries a ;
~ 25 wiper arm 212 of trigger switch 2~2 which engages a bank con- ~
.. .
tact 213 at the top and a bank contact 214 at the bottom of each hour. The two bank contacts 212 and 213 are mounted on ~.
.
_18-1l~8Z4~;9 a printed-circuit board 259 (FIG. 16) as described with refer-ence to FIGS. 9 and 10. Wiper 212 is permanently connected~
by way of an annular contact strip 215 on the printed-circuit board~ to a line 216 held at ground potential 0.
Gating circuit 203 comprises a flip-flop formed by two cross-connected NAND gates 217~ 218 whose inputs 219, 220 are connected by lines 221~ 222 with contacts 213~ 214 of ~ switch 202. Each NAND gate 217~ 218 has an output 223~ 224 ; connected directly to one input 227~ 228 and by way of three cascaded inverters 231, 232 to the other input 228~ 230 of a respective OR gate 225~ 226 whose outputs 233~ 234 are com-bined in a NOXOR gate 235. In the general manner described above~ th1s NOXOR gate 235 is switched whenever the arm 212 touches the contact 213 on the full hour or the contact 214 -on the half-hour~ thereby grounding either the input 219 of NAND gate 217 or the input 220 of NAND gate 218. This results in switching either the output 223 or the output 224 perma-nently to L-potential. Becau~e of the phase delay introduced by inverters 231 or 232~ a brief start signal is thereby again generated in the output 236 of gate 235 as will be apparent from FIGS. 15a - 15f.
In the position of FIG. 15a the wiper 212 has already left the contact 214 but has not yet reached the contact 213.
NAND gate 218 conducts whereas NAND ~ate 217 is blocked.
Their outputs 224~ 223~ therefore~ carry potential L and potential O~ respectively. At the output 236 of the NOXOR
gate 235 there appears potential L~ which therefore lies also . :
, , . . .
1~8Z469 ` .0190 at the setting input 238 of the flip-flop constituting the electronic control unit 204 comprising NAND gates 240 and 241.
In the position of FIG. 15b the wiper 212 has engaged the contact 213 of switch 202 precisely at the full hour~
grounding that contact. The output 223 of NAND gate 217 is switched to potential L while potential O appears simultan-eously at output 224 of NAND gate 218. Accordingly~ the potentials at inputs 227 and 230 of the OR gates 225~ 226 change too. Owing to the delay lines 231~ 232 in series with inputs 228 and 229~ the potentials there change slightly later~ with the result that the output 236 of gate 235 is briefly switched to potential O; this acts as a start signal for setting the flip-flop 204. Shortly thereafter~ the mode of energization of circuit 203 changes to that shown in FIG. l5c~ output 236 being switched back to potential L.
After an interYal sufficient for the execution of the `~ maximum number of strikes (12), wiper 212 leaves the contact 7 213. The potential distribution then existing~ shown in FIG. 15d~ i8 the same as that of FIG. 15c. The engagement of the bank contacts 213 and 214 during the maximum period of the corresponding strike signal is designed to obviate any possible malfunction caused~ for instance~ by downstream I switching operations which could reverse the flip-flop formed I by NAND gates 217~ 218.
FIG. 15e shows the conditions which prevail at the exact half-hour~ i.e. at the moment of conductive engagement between wiper 212 and contact 214. m e flip-flop 217~ 218 of . .
i -20-~ .
`:
:' 108Z4~g .' the electronic pulse emitter 203 then switches over~ i.e. the output 224 of NAND gate 218 carries potential L while the output 223 of NAND gate 217 carries potential O. Because of the delay introduced by lines 231, 232~ a potential O again S appears briefly at the output 236 of NOXOR gate 235 as a start signal for control unit 204. NAND gate 240 of unit 204 is now conductive and energizes its output 242.
After the end of the delay introduced by inverters 231, 232~ the potential distribution illustrated in FIG. lSf is attained and is maintained at least for the duration of the half-hour strike. When after this time the contact between the wiper 212 and the conductor 214 is interrupted~ the poten-tial distribution of F~G. 15a recurs.
When ~e NAND gate 240 of flip-flop 204 conducts~ a transistor 205a is turned on and cutS in a drive motor 205b to activate the striking mechanism here shown to comprise a hammer 206a and a bell or gong 206b.
The drive motor 205b also operates the electronic pulse emitter 207 by way of a shaft 245. With the shaft 245 rotates a contact arm 246 which sweeps with each full rotation a pair of bank contacts 247 and 248 in succession. The grounding of contact 247 by the arm 246 sets a flip-flop formed by two cross-connected NAND gates 249~ 250 whereby a counting pulse is transmitted via a lead 253 to the stepping input 254 of an ~` 25 electronic counter 208~ this counting pulse being repeated with each additional strike.
The position coder 210 comprises four contact arcs 260 ' '"' 10~;~469 .0190 261~ 262~ 263~ which are arranged concentrically within carrier plate 259 (FIG. 16) with progressively smaller radii and are brushed by a wiper blade 264 rotated on an hour shaft 265. Attached to the blade are four elastic tongues 266 - 269 which sweep the four contact arcs 260 - 263 during rotation of the hour shaft 265.
A continuous annular bank contact 270~ which is swept by a fifth tongue 271 of wiper 264 and connects that wiper to ground potential 0~ is concentrically pro-vided within arcs 260 - 263.
The contact arcs 260 - 263 are arrayed pursuant to a binary code illustrated in FIG. 17. Arc 260 is divided into six seqments 260a~ 260b~ 260c~ 260d~ 260e~ 260f; arc 261 has three segments 261a~ 261b~ 261c; arc 262 is split into two segments 262a~ 262b; and arc 263 consists of a single segment 263a. m e several segments of a divided arc are interconnected by anclllary conductors 273~ 274~ 275.
~' ~:, :, ~08Z46g me 4-bit binary code shown in FIG. 17 affords 24 = 16 combinations of which, however, only 13, that is O and 1 - 12, are used.
In FIG. 17, the column 205/206 shows the number of strikes executed ~t successive hours. Column 208 is a truth table showing the energization of the stage outputs 300 - 303 of the electronic countsr 208 tied to respective inputs 291, 293, 295, 297 of a set of XOR gates 285 - 288 forming part of the comparator 209 of FIG. 11. ~-In contrast, column 210/260 - 263 shows the sequence of engagement of the contact arcs 260 - 263 by wiper 264 during consecutive hours. It will be seen that the code of the arcs 260 - 263 on plate 259 is complementary to the pattern of energization of output leads 300 - 303 of counter 208. A bit "O"
in column 21Q/260 - 263 is represented by the grounding of the corresponding arc se8ment through wiper 264 brought about by the segment position shown in coluDn210/259 of FIG. 1~.
; me coder 210 is connected via four leads 280, 281, 282, 283, originating at contact arcs 260~ 261, 262, 263, to respective inputs 290, 292, 294, 296 of XOR gates 285, 286, 287 and 288 serv-ing as discriminating stages of comparator 210~ mese XOR gates work into respective inputs 305 - 308 of a NAND gate 310 which is cut off; two complementary and therefore matching codes are read out from coder 210 and counter 2Q80 At that instant the potential O appears at the output 311 of NAND gate 310 to serve as a stop signal for arresting the striking mechanism 206a, 206b and clearing the counter 2080 An advantageous layout of the co~er 210 provides that the arc segments 261a - 261c, 262a, 262b and 263a for the higher-ranking 1 ~ 8 ~ 4 6 bit positions are arranged on circles of progressively decreasing radii; conductor 270 lies on an inner circle of the smallest radius.
mis arrangement results in a more exac~ scanning of the more n w rous shorter ~rc segments 260a - 260f for the wiper 2640 me reduced scanning accuracy for the segments of greater arc length is easily toleratedO
In order to guarantee safe operation of the stri~ing mechanism, an overlap A iæ provided between arc segments ending and beginning at a given level in the scanning direction, as illustrated in column 210/259 of FIG. 170 me extent of this overlap is determined by the possible tolerances of the segments 260a - 260f; 2601a - 261c; 262a, 262b; 263a on the one hand and the scanning tongues 266 - 269 of the wiper 264 on the other hand. Such an overlap is particularly required at locations where the complete interruption of the scan is otherwise possible, ~' ~8 for instance at the transition from code L00~ to code OLLL
between the 12th and 1st hours. mus, there should be no pos~i-Z bility of energizing all four gate inputs 290, 292, 294, 296 simultaneously with potential L since the code LLLL is comple-mentary to the normal pattern of energization (0000) of the , counter output80 Should this occur in an intermediate pos~tion, j e.g. ~hile the cloc~ is being set, continuous strikes might be f executed by the striker mechanism, unt~l the wiper 264 is ;~ 25 sufficiently advanced by the hour shaft 2~5.
-~ An~ther advantageous feature of the coder 210 is apparent from FIG. 16 and lies in the ~act thst the ancil-lary conductors 273 - 275 are interrupted at aligned locations to form a radial gap through which associated leads 281, 282, 283 are brought out in the form of nsrrow, c7Osely -9o adjoinin~ conductor strips. ~he lead 2~0 to arc 260 can be connected to any of its segments 2vOa - 260f or to the ancillal~y conductor 273, because no overlappin~
problems occur there.
~he lead 272 for the inne~nost conductor 270 passes through the same gap.
i A~vantageously, the interruption of the ancillar~
conductors 273 - 275 occurs between positions lOOO (seg~ents 262a, 261b, 260d) and O~LL (segments 2~3a).
. I .
~10 ~he trigger mechanism 202 can also be desi~ned in a ;~ form similar to codes 210, with the contacts 213 and 214 I carried on the same printed-circuit board 259.
!
~he output 311 of ~JAND gate 310 is tied by a lead 312 to an input 313 of a NO~OR gate 315 having a second input 114 connected to the output of a NAND gate 316.
~he input 317 of this N~D gate 316 is connected to -the output lead 300 o~ counter 208 which is the first lead energized. The other input 318 of NAND gate 31~ is tied to the output 224 of ~AND gate 218 in circuit 203. ~he output 31 '~20 of ~OXO~ ~ate 315 is connected to the resetting input 320 of ... . .
flip-flop 204. A lead ~21 extends from the output 319 of ~O~OR
gate 315 to the clearing input 322 of counter 208.
If the striking mechanism is activated on the full hour, the pulses generated by the electronic pulse emitter 207 25 ~ advance the counter 208 until the number of strikes corresponcs to the position of the hour hand ~nd of coder 210.
108'~4f~?
This results ln the grounding of the output 311 of ~ND
gate 310 and of the input 313 of gate 3150 -At the ou~put 224 of the ~D gate 218 there now also exists the potential 0, 80 that J~D gate 316 i8 not switchable at this tim~o Thus the potential O lies at the input 313 of the I~OæOR gate 315, the potential L at its input 314. As a result, potential O appears at the output 319 of gate 315 and at the input 320 of flip-flop 204, resotting the latter and cutting off the transistor 205.
~' :
On the other band, if the activation of the striking mechanism ls initiated on the half-hour by the grounding of contact 214, potential L lies at the output 224 of ~ID
gate 218. After the counter 208 has counted the first strilce, potential L 8180 appears at its output 300. mese tim~ potentials are delivered - on the one hand by lead 323, l and on the other hand by lead 324 - to the inputs 317 and 318 Il of 17A~D gate 316, 80 that potentlal O is deliver~d at its i.-. output 314. At input 313 of gate 315 lies, however, potentlal L rom output 311 of I~A~D gate 310, 80 that already '~:20 after the f~rst stri1ee 11~ gate 315 i8 ~witched to reset the flip-flop 204. The graphs of FIG. 18 show the energi~zation ....
of the indilvidl~al logic sle~ents ~n the system of F~G. 12.
FIG. 13 show~ a m~dlflcation of ~hat 8y8tem in ~`: which a strllcing mechani~m 206' is actuated by an astable ltivibrator 205'; mechanl~m 206' may be a one-stroke bell.
, . .
, , .
' '.
i . !
~ 4 ~ 9 Such an arrangement works without contact, displays little ~usceptibility to trouble and exhibit~ a favorable current consumption.
Thi8 pulse emiiter 2071 i8 here shown as a pulse shaper in the output of multivibrator 205'.
FI~. 14 is a schematic representation of another modification of the circuit arrangement according to FIG.12.
In this instance a plurality of stage outputs 333, 334, 33 of a blnary frequency divided 331, driven by a crystal-10-controlled oscillator 330, are combiDed in an AND gate 205c to generate driving pulses of low du~y ratio which are pa~sed by another AND gate 205d as long as flip-flop 204 is set. Oscillator 330 and divider 331 also drive the clockwor~ 332 as part of unit 201.
Drive unit 205 and pul~e emitter 207 could be co~bined into a ~ingle unit.
, -27-., , ,
If desired, a circuit breaker may be provided which iB controlled b~ the clockwork for disabling the drive means for the ~triking mechani~m during certain night-time hours, eOg. for an 8-hour period startlng at 11 Pff (2300 hours). Such a circuit breaker could prevent, ~0 for example, a switchover of the afordescribed gating circuit.
., ~; .
., ;, ~ -5-10824~9 9~ J~ri.ef ~escri t~tion Or thc Dral~linF
The above an~ other features of the invention will now be described in detail with reference to the accompanying drawinz in which: :-Fig. 1 is a circuit diagram of a system for the control of an electrical strikin~ mechanism representing a first embodiment of the invention;
Figs. 2 - 5 show part of the Gircuit diagram of ~ig.l '. -in fou.r different phases of operation;
~igs. ~ and 7 show another part of the circuit diagram LO of ~'ig. 1 in two different phases of operation;
~ig. 8 is a set of ~raphs showing the state of energization of various components of the system of ~ig. 1 -~ -during a one-hour operating cycle;
Fig. 9 is a cross-sectional view of part of a clock-~5 ~iork with members forming part of the system of Fig. 1;
Fig. 9a is a face view of one of the cont~ct members of Fig. 9;
: ~ig. 9b is a face view of another contact member shown in Fig. 9; ~ -Fig. 10 is a view similar to Fig. 9, showing a modi-ication;
1. ~ig. 11 is a bl.ock diagram of a control system ~-¦:~:1 representing a second embodiment of the invention;
ig. 12 iæ a circuit diagram similar to Fig. 1 but relating to this secona embodimen~;
Figs. 13 and 14 show p~rtial modifications o~ the system of Fig. 12;
igs. 15a - 15f show part of the circuit diagram of ~ig. 12 in six different phases of operation;
., .
~ 108Z469 Fig. 16 is an enlarge~ detail view of a contact assembly included in the sys-tcm of ~ig. 12;
~ig. 17 is a code diag~rar~ for the e~bodi~ent of ~i~s. 11 - 1~; and l~ig. 18 is a set of graphs similar to ~ig. 8 but relating to the second e~bodi~ent.
Specific Descr ~tion .
~ig. 1 shows a minute shaft 1 of a con~entional clockwork ~Jhich actuates a switch 2 comprisin~ a contact member 3 rotating with the minute shaft 1, designed as a O wiper; contact member 3 sweeps an arcuate bank contact 4 during the ~O-minute interval between half-hour and full hour.
~ank contact 4 is printed on a carrier plate 132 (~ig. 9) within the cloc~work controlling the eiectrical striking mechanism pursuant to the invention.
, The switch 2 is so positioned in relation to the ; minute hand (not sho~) mounted on shaft 1 that the wiper ~ wili ,; ~ .
arrive at the bank contact 4 exactly at the beginning ol the 8econd half hour, i.e. exactly at X30 o'clock, touching it an~
consequently closing the switch. ~he wiper 3 is permanently connected, as by a sliding contact, to a point o~ fixed potential (ground) of lo~ical value "O". ~ank contact 4, on the other hand~ is connecte~ to a source of potential of lo~ical value "1"
(designated by ~) via a resistor 5.
.. ~ .
Two sections of a gating circuit including a pair o~
~5 ~ ~hN~ gates 6 and 7 are connected in pa~allel to ban~ con-tact ~.
ND ~ate 7 has an input 8 connec~ed directly to a line 9, tied ... ,: ~, -_ 7 --.~ ~ - , ,. . . . ..
^ ~08Z469 0 to that bank contact, and an input 10 connec-~ed ~o a junction point 14 on line 9 by way of three cascaded inverters 11, 12 and 13 also having a delay function.
Similarlyt three cascaded inverters 15, 17 and 18 are inserted between an input 15 of NAND gate 6 and a junction point 19 tied to the other input 20 of the same NA~ID gate 6.
An additional inverter 21 lies between junction point 19 and bank contact 4.
~ig. 2 shows the signal distributions at various 0 points of the gating circuit controlled by switch 2, as it exists a short time before the initiation of the half-hour strike, i.e. at about ~25 o'cloc~ In this state, the signal L
prevails at the outputs 22, 23 of the two NAND ~ates ~, 7.
Fig. 3 shows the state of the circuit at the moment .5 the half-hour strike is initiated,i.e. exactly at ~ o'cloc~.
As a result of the inverters 16 - 18 and 11 - 13, phase delays ~:~ occur at the moment of switchover at X30 o'clock, i.e. when the switch 2 is closed, making the voltag~s at the inputs 15, 10 of the two NAND gates 6, 7 briefly e~ual to thosé of their b~ inpu~s 20 and 8, respecti~ely. As a consequence, at the ~; , ,._ . -moment the circuit between contact members 3 and l~ is closed, - the signal co~dition shown in Fig. 3 prevails for a short period with N~N~ gate 6 cut off.
hus, at instant X30 the signal 0/~ occurs at the outputs 22, 23 of the two N~D ~ates 6, 7, while according to . ~ .
'' 3X46~
-~ig. 2 the signal pair ~/L e~isted at those outputs up to tllen.
q'he signal conditions sho~m in Fig. 3 are maintained only for an extremely short time which is sufficient, ho~ever, to effect the switching processes described belo~J.
At the end of this brief interval, thus sho~tly after ; X30 o~clock, the signal sequence sho~ in ~ig. 4 occurs. This means that, with switch 2 still closed, the signal pair ~/~
reappears at the outputs 22, 23 of the two NA~D gates.
At X60 o'clock = (~ ~ 1) o'clock, the contact ~ member 3 of switch 2 leaves the arc 4, i.e. the switch is re-opened. With the recurrence of the aforedescribed phase delay, the signal distribution shown i~ Fig. 5 occurs briefly at the full hour. In this case, therefore, thP signal pair ~/0 appears at the outputs 22, 23, of the two NAND g~tes 6, 7.
It is evident from the foregoing tha~ at the l.loment the switch 2 is reversed, i.e. closed or opened, opposite ,, .
signals appear at the outputs 22, 23 of the two ~AND gates whereas identical signal pairs eYist there in the inte~mediate positions. According to a feature of the present invention, the emergence of unequal signals at the outputs of the I~7~7~ gates 6, 7 serves as a starti~g criterion for the activation of the electrical striking mechanism. ~or this purpose, a further ~ iogical relationship is required pursuant to the follo~Jing ~able.
; , -_ 9 _ .'' ~' ' .
)190 ~ 4f~9 TABLE S
NAND gate 6 NAND gate 7 Y Time range and, respectively, (output 22) (output 23) ~oint of time L L O X _ X30 X30 _ X60, (X ~ 1) L O L X , X~O , (X + 1~
O 0 O does not appear at any time (A) (B) Y hours/minutes .O In the Table, Y represents a start signal (ac-tually a complement thereof) satisfying the Boolean relationship B + AB = y which is the function of an Exclusive-OR (XOR) gate or anticoin-~idence circuit.
In accordance with a further feature of the in- --vRntion, the start signal generated by the switch 2 at X30 o'clock and ~t X~O? o'clock is fed to the setting input S of a flip-flop ~ ~O, here shown to comprise two cross-connected NAND gates 45, :
;.( 46. Such a circuit requires as a setting signal a logical "O"
;~o which is obtained, advantageously, by a negation of the above function:
. ~ .
y = A B + AB = A B AB
`.~ This logical function is performed by an invert1ng anticoincidence . ~, circuit also known as a NOXOR gate.
:
,,,, -' , !_ 10 -.
go ~ 469 This circuit comprises two inverters 30, 31 which are connected in series to the outputs 22, 23 of the NAND gates 6, 7 and work into respective inputs 34, 35 of two NAND gates 32, 33, whose two other inputs 36, 37, are tied directly to outputs 23 , and 22 respectively.
The outputs 38, 39 of the two NAND gates 32, 33 are combined in an AND ~ate 40 whose output 41 is connected to the setting input S of flip-flop 50.
FIG 6 illustrates the signal distribution along 0 the linkages of the NOXOR gate 30 - 33, 40 which results when unequal signals emitted by the NAND gates 6, 7 are applied to its inputs 22, 23. In this c~se, the signal L appears at the output of the AND gate 40 and at the input S of the NAND gate 45 of the flip-flop 50, i.e. the flip-flop 50 remains reset and its out-put 51 is not energized. If, however, a pair of unequal signals ¦ appear at the connections 22, 23, i.e. L/0 or 0/L, the signal distribution illustrated in FIG. 7 results, i.e. the signal 0 appears at the output of AND gate 40, resulting in a setting of the fl~.p-flop 50 and energization of output 51 which in turn umblocks a power transistor 53 feeding a drive motor ~ to ac-tuate the associated striking mechanism (not shown in these Figures). As a result, the sound generator of this mechanism begins to produce a series of strikes.
The sound ~enerator can comprise a conYentional bell, ~S gong tube or spiral gong. Strings of electronic oscillators could also be used. Another possibility is the provision of a .
:
iO8Z4~;9 mechanical tuning fork excited intermittently by the striker for conductively transmitting its audio frequencies to an amplifier for the energization of an electro-accoustic transducer.
A switch 56 has an arm 63 driven by motor 55 for alternately grounding two contacts 57, 58, thereby periodically setting and resetting a f~ip-flop 60 as long as the motor is energized. Flip-flop 60 serves to step a binary electronic counter 70 and insures that exactly one pulse per strike is transtnitted to.that counter. It consists of two cross-connected NAND gates D 61, 62; output 71 of gate 61 is connected to a stepping input 73 of counter 70 by way of a lead 72 In the well-known manner, this binary counter stores the pulse generated with each strike of the sounding mechanism and converts its count into a binary code which appears on four stage~.; outputs 75 - 78. This binary code is translated l~y a binary-decima~ decoder 80, connected to outputs 75 - 78, into a marking (i.e~ grounding) of one of ten output terminals 0 - IX
which normally carry signal voltage L. Terminal 0 is grounded in the cleared state of counter 70. ..
In decoder 80, therefore, nine terminals I - IX
are available for the counting of strikes. However, since up to 12 ~-3 strikes have to be counted, the NAND gates conventionally present .
.~¦ within the decoder are supplemented by three further NAND gates ~ 81, 82 and 83 with output terminals X, XI and XII.
-I
,3 The outpuc I of the binary-decimal decoder 80 is con-: nected to an input 91 of a NAND gate 95 by a ~ine 85 including an inverter 90. The other input 92 of this NAND gate 95 is tied to ^ the junction of inverters 13 and 12 which form part of one of the circuit branches feeding bhe NAND gate 7.
-- 12 _ 10 8 ~ 4 ~ 9 After the half-hour strike has been triggered by the switch 2 and a puls~ .has been transmitted to the binary counter 70 by the flip-flop 60, the pattern of energization of the outputs 75 - 78 is changed from 0000 to 0001, whereupon the signal L appears at the output 0 of decoder 80 while the signal L is replaced at the adjacent output I by the signal 0 (positive logic being assumed in this case)0 e signal 0 is fed to the inverter 90 by line 85 and its complement L ~8 thus delivered to the input 91 of NAND gate 95.
Since, however, bank contact 4 i8 grounded at this moment also by the wiper srm 3, the signal L appears also at the input 92 of NAND gate 95 which therefore switches fts output 96 to signal 0. :~
At the time of the hslf-hour strike a contact arm or wiper 101 forming part of a switch 102 snd rotating with the hour shaft 100 of the c~ockwork i8 located in a position between two tecoter terminals I ... XII and iB energized with signsl L vis a resistor 105. An inverter 103 tied to wiper 101 then grounds an input 106 of a NAND gate llO having another input 107 connected to ~unction point 14 which is al80 grounted 80 thst NAND gate 110 nss an output signal L
Thu8, unlike signals are found at outputs 96 and 97 of the two NAND gates 95 and 110 which constitute respective inputs of an inverting ant~coincidence ~NQXQR~ gste analogously to the one working into setting input S of flip-flop 50. Thi8 second NoX0 gate comprises two inverters 111, 112, two NAND gates 113, 114 and an AND gate 115. Unequal signals at the two outputs 96, 97 -~3_ ' 10824~
of the two NAND gates 95~ 110 produce an O-signal at the output 116 of AND gate llS which is tied to a resetting input R of the flip-flop 50. This results in a de-energiza-tion of line 51 and stops the drive motor SS by cutting off its supply transistor 53. Motor 55 is designed to come to a halt in a position in which the sw~tch arm 63 has reset the flip-flop 60. The flip-flop 50 does not switch over again until the signal O reappears~ at its setting input S~
regardless of the potential of its resetting input R. The output 116 of AND gate 115 is further connected by a lead 117 to a clearing input 74 of the binary counter 70 which therefore registers a zero count upon the resetting of flip-flop 50 so that signal L appears again at decoder output I.
~l 15 As a res~lt~ NAND gate 9S conducts and switches the , NOXOR gate 111 - 115, causing the signal L to reappear at its output 116; this change in signals~ however~ has no effect on the state of flip-flop 50 which remains reset.
During the execution of the hour strikes~ the wiper 101 of the switch 102 engages one of the outputs I - XII of decoding circuit 80 - 83 in accordance with the position of the hour hand of the clock mechanism. The wiper 101 is therefore electrically connected to the respective decoder output.
¦ 25 The start of the stri~ing operation for the hours occurs in the manner already descri~ed with reference to _14-:' , 10190 lOBZ4~9 FIGS. 5 and 6.
Durtng the hour strike~ the contact arc 4 ~ust dis-engaged by arm 3 applies signal L by way of line 9 to the lnput 107 of NAND gate 110 whose other input 106 is initially maintained ~y inverter 103 at signal level 0. The nonidenti-cal signals O/L at the inputs 106 and 107 of NAND gate 110 lead to an L-signal at the output 97 of this gate. At the same time~ an O~signal lies at the input 91 of NAND gate 95 because of the L-signal at decoder output I. An O-signal also appears at the input 92 of NAND gate 95~ resulting in a signal L at its output 96.
Therefore~ both outputs 96~ 97 exhibit L-signal and the NOXOR gate 111 - 115 ineffectually enerqizes lts oùtput 116 with an L-signal. As soon as the pulse count matches the lS position of wiper 101~ the ground~ng of the decoder terminal engaged by the wiper applie~ signal L to the input 106 of NAND gate 110~ resulting in a changeover of the output 97 to slgnal 0. Thi~ produce~ unequal signals at the inputs of `, NOXOR qate 111 - 115, giving rise to the stop signal O on 1, 20 resetting input R of flip-flop 50 and on clearing input 74 of ,'l binary counter 70~ thereby arresting the striking mechanism.
;~ The ~ode of energization of the logic elements parti-, .
^~ cipating in the operating cycle ~ust described has been out-;~ lined in FIG. 8.
FIG. 9 shows a specific construction of the switches 2~ 101 of FIG. 1 incorporated in the clockwork.
'' "'I
~ ~?~i The minute shaft 1~ hour shaft 100 and second-hand '. 1 ~ r,.
~ _15--.. . ~
,.
.. . .
- ~08Z46~
o~so - shaft 122 of the clockwor~ project through a clock dial 121 in their usual nested relationship. The minute shaft 1 carries a pinion 123; the hour shaft 100 is rigidly connected with a gear 124. Pinion 123 engages a gear 125 which is S rigid with a pinion 126 in mesh with gear 124. A stud 127 carrying gears 125~ 126 is mounted on a plate 130 which~ -together with another plate 131 and a set of connecting bolts 129~ forms part of a frame holding the clock mechanism.
A printed-circuit board~ constituting the aforemen-''! 10 tioned carrier plate 132~ is arranged between the plate 130 , and the dial 121. This printed-circuit board 132 is penetra-s ted by the minute shaft 1 and the pinions 123 and 126; gear ~ 124 lies between the printed-circuit board 132 and the dial -~ 121.
lS An extension 133 of pinion 123 carries the contact arm 3 between the hoard 132 and the gear 124. The contact arm 3 i~ designod as a resilient wiper (blade) 134 and scans J th- contact arc 4 on the board 132. This blade 134 is rigid-ly connected with pinion 123 and rotates together with the 3 20 latter. The blade 134 carries two resilient heads 135~ 136 head 135 scanning the contact arc 4 whirh extends over an angular range of 180 in the area of X30 _ X60~ i.e. over a path of 30 minutes. The other head 136 scans another contact arc connected to ground potential 0~ the latter arc being also carried on the board 132 and extending over a somewhat larger ang}e~ e.g. of about 200 .
~he gear 124 is made of an insulating material~ prefer-ably a plastic. It carries the wiper blade 101 of the switch _16-10190 lO~Z4~;9 102, that blade being also provided with two resilient heads 137, 138 which scan respective conductor banks on the printed--circuit board 132. ~he blade 101 extends beyond pinion 126 so that a full range of 360 is available for the scanning S of its conductor banks printed on the board.
The assembly shown in FIG. 9 permits a compact design of the control assembly for the electrical strikin~ mechanism ; pursuant to the invention. Essential components 139~ 140 of the electronic control circuit and of the clockwork itself ~such as a crystal-controlled oscillator) may be arranged on the board 132 and can be connected with the remainder of the circuit by way of their printed conductors.
The arrangement according to FIG. 9 is particularly suitable for flat timepieces.
A modified mounting for switches 2~ 102 has been illustrated in FIG. 10. In this instance~ a printed-circuit board 132~ i8 provided with conductor arrays on both sides.
The blade 134~ of contact member 3~ carrying heads 135~ 136~
i~ now arranged between pinion 123 and the board 132~ and scans ban~ contacts disposed on the side of the printed-circuit board remote from gear 124. The blade 101~ on the other hand~ is arranged between the printed-circuit board 132t and the gear 124~ rotating with the latter and carrying heads 137~, 138' - scanning contact banks which form the terminals I - XII, spaced 30 apart~ and a connection to res~stor 10~ and in-verter 103 ~FIG. 1). --The assembly of FIG. 10 is particularly suitable for .
,`~
, .
` , ~ " f = . - . ~
- , . .. . .. . . . . . .
0190 ~08Z~
use in timepieces of relatively small diameter.
FIGS. 9a and 9b are face views of contact members 101~ 137~ 138 and 134 - 136 of the two switches 2~ 102.
FIG. 11 shows the overall layout of a system generally S similar to the one just described but representing a second embodiment.
A clockwork 201 actuates~ by its minute shaft~ a trigger switch 202 which periodically activates~ at the full hour and at the half-hour~ an electronic gating circuit 203 to apply a start signal to an electronic control unit 204;
this control unit thereupon activates a drive unit 205 for the operation of a striking mechanism 206. A strike may con-sist of a single note or a sequence of notes.
With each strike~ an electronic pulse emitter 207 is ca w ed to transmit a counting pulse to a binary counter 208.
e reading of counter 208 is confronted by an electronic , comparator 209 with the output of a coder 210 coupled with the hour shaft of the clockwork 201. When the comparator 209 detects a match ~etween the readings of position coder 210 and counter 208~ it emits a pulse which deactivates the drive unit 205 via control unit 204 and also clears the electronic counter 208.
FIG. 12 shows details of the system of FIG. 11.
The ~inute shaft 211 of clockwork 201 carries a ;
~ 25 wiper arm 212 of trigger switch 2~2 which engages a bank con- ~
.. .
tact 213 at the top and a bank contact 214 at the bottom of each hour. The two bank contacts 212 and 213 are mounted on ~.
.
_18-1l~8Z4~;9 a printed-circuit board 259 (FIG. 16) as described with refer-ence to FIGS. 9 and 10. Wiper 212 is permanently connected~
by way of an annular contact strip 215 on the printed-circuit board~ to a line 216 held at ground potential 0.
Gating circuit 203 comprises a flip-flop formed by two cross-connected NAND gates 217~ 218 whose inputs 219, 220 are connected by lines 221~ 222 with contacts 213~ 214 of ~ switch 202. Each NAND gate 217~ 218 has an output 223~ 224 ; connected directly to one input 227~ 228 and by way of three cascaded inverters 231, 232 to the other input 228~ 230 of a respective OR gate 225~ 226 whose outputs 233~ 234 are com-bined in a NOXOR gate 235. In the general manner described above~ th1s NOXOR gate 235 is switched whenever the arm 212 touches the contact 213 on the full hour or the contact 214 -on the half-hour~ thereby grounding either the input 219 of NAND gate 217 or the input 220 of NAND gate 218. This results in switching either the output 223 or the output 224 perma-nently to L-potential. Becau~e of the phase delay introduced by inverters 231 or 232~ a brief start signal is thereby again generated in the output 236 of gate 235 as will be apparent from FIGS. 15a - 15f.
In the position of FIG. 15a the wiper 212 has already left the contact 214 but has not yet reached the contact 213.
NAND gate 218 conducts whereas NAND ~ate 217 is blocked.
Their outputs 224~ 223~ therefore~ carry potential L and potential O~ respectively. At the output 236 of the NOXOR
gate 235 there appears potential L~ which therefore lies also . :
, , . . .
1~8Z469 ` .0190 at the setting input 238 of the flip-flop constituting the electronic control unit 204 comprising NAND gates 240 and 241.
In the position of FIG. 15b the wiper 212 has engaged the contact 213 of switch 202 precisely at the full hour~
grounding that contact. The output 223 of NAND gate 217 is switched to potential L while potential O appears simultan-eously at output 224 of NAND gate 218. Accordingly~ the potentials at inputs 227 and 230 of the OR gates 225~ 226 change too. Owing to the delay lines 231~ 232 in series with inputs 228 and 229~ the potentials there change slightly later~ with the result that the output 236 of gate 235 is briefly switched to potential O; this acts as a start signal for setting the flip-flop 204. Shortly thereafter~ the mode of energization of circuit 203 changes to that shown in FIG. l5c~ output 236 being switched back to potential L.
After an interYal sufficient for the execution of the `~ maximum number of strikes (12), wiper 212 leaves the contact 7 213. The potential distribution then existing~ shown in FIG. 15d~ i8 the same as that of FIG. 15c. The engagement of the bank contacts 213 and 214 during the maximum period of the corresponding strike signal is designed to obviate any possible malfunction caused~ for instance~ by downstream I switching operations which could reverse the flip-flop formed I by NAND gates 217~ 218.
FIG. 15e shows the conditions which prevail at the exact half-hour~ i.e. at the moment of conductive engagement between wiper 212 and contact 214. m e flip-flop 217~ 218 of . .
i -20-~ .
`:
:' 108Z4~g .' the electronic pulse emitter 203 then switches over~ i.e. the output 224 of NAND gate 218 carries potential L while the output 223 of NAND gate 217 carries potential O. Because of the delay introduced by lines 231, 232~ a potential O again S appears briefly at the output 236 of NOXOR gate 235 as a start signal for control unit 204. NAND gate 240 of unit 204 is now conductive and energizes its output 242.
After the end of the delay introduced by inverters 231, 232~ the potential distribution illustrated in FIG. lSf is attained and is maintained at least for the duration of the half-hour strike. When after this time the contact between the wiper 212 and the conductor 214 is interrupted~ the poten-tial distribution of F~G. 15a recurs.
When ~e NAND gate 240 of flip-flop 204 conducts~ a transistor 205a is turned on and cutS in a drive motor 205b to activate the striking mechanism here shown to comprise a hammer 206a and a bell or gong 206b.
The drive motor 205b also operates the electronic pulse emitter 207 by way of a shaft 245. With the shaft 245 rotates a contact arm 246 which sweeps with each full rotation a pair of bank contacts 247 and 248 in succession. The grounding of contact 247 by the arm 246 sets a flip-flop formed by two cross-connected NAND gates 249~ 250 whereby a counting pulse is transmitted via a lead 253 to the stepping input 254 of an ~` 25 electronic counter 208~ this counting pulse being repeated with each additional strike.
The position coder 210 comprises four contact arcs 260 ' '"' 10~;~469 .0190 261~ 262~ 263~ which are arranged concentrically within carrier plate 259 (FIG. 16) with progressively smaller radii and are brushed by a wiper blade 264 rotated on an hour shaft 265. Attached to the blade are four elastic tongues 266 - 269 which sweep the four contact arcs 260 - 263 during rotation of the hour shaft 265.
A continuous annular bank contact 270~ which is swept by a fifth tongue 271 of wiper 264 and connects that wiper to ground potential 0~ is concentrically pro-vided within arcs 260 - 263.
The contact arcs 260 - 263 are arrayed pursuant to a binary code illustrated in FIG. 17. Arc 260 is divided into six seqments 260a~ 260b~ 260c~ 260d~ 260e~ 260f; arc 261 has three segments 261a~ 261b~ 261c; arc 262 is split into two segments 262a~ 262b; and arc 263 consists of a single segment 263a. m e several segments of a divided arc are interconnected by anclllary conductors 273~ 274~ 275.
~' ~:, :, ~08Z46g me 4-bit binary code shown in FIG. 17 affords 24 = 16 combinations of which, however, only 13, that is O and 1 - 12, are used.
In FIG. 17, the column 205/206 shows the number of strikes executed ~t successive hours. Column 208 is a truth table showing the energization of the stage outputs 300 - 303 of the electronic countsr 208 tied to respective inputs 291, 293, 295, 297 of a set of XOR gates 285 - 288 forming part of the comparator 209 of FIG. 11. ~-In contrast, column 210/260 - 263 shows the sequence of engagement of the contact arcs 260 - 263 by wiper 264 during consecutive hours. It will be seen that the code of the arcs 260 - 263 on plate 259 is complementary to the pattern of energization of output leads 300 - 303 of counter 208. A bit "O"
in column 21Q/260 - 263 is represented by the grounding of the corresponding arc se8ment through wiper 264 brought about by the segment position shown in coluDn210/259 of FIG. 1~.
; me coder 210 is connected via four leads 280, 281, 282, 283, originating at contact arcs 260~ 261, 262, 263, to respective inputs 290, 292, 294, 296 of XOR gates 285, 286, 287 and 288 serv-ing as discriminating stages of comparator 210~ mese XOR gates work into respective inputs 305 - 308 of a NAND gate 310 which is cut off; two complementary and therefore matching codes are read out from coder 210 and counter 2Q80 At that instant the potential O appears at the output 311 of NAND gate 310 to serve as a stop signal for arresting the striking mechanism 206a, 206b and clearing the counter 2080 An advantageous layout of the co~er 210 provides that the arc segments 261a - 261c, 262a, 262b and 263a for the higher-ranking 1 ~ 8 ~ 4 6 bit positions are arranged on circles of progressively decreasing radii; conductor 270 lies on an inner circle of the smallest radius.
mis arrangement results in a more exac~ scanning of the more n w rous shorter ~rc segments 260a - 260f for the wiper 2640 me reduced scanning accuracy for the segments of greater arc length is easily toleratedO
In order to guarantee safe operation of the stri~ing mechanism, an overlap A iæ provided between arc segments ending and beginning at a given level in the scanning direction, as illustrated in column 210/259 of FIG. 170 me extent of this overlap is determined by the possible tolerances of the segments 260a - 260f; 2601a - 261c; 262a, 262b; 263a on the one hand and the scanning tongues 266 - 269 of the wiper 264 on the other hand. Such an overlap is particularly required at locations where the complete interruption of the scan is otherwise possible, ~' ~8 for instance at the transition from code L00~ to code OLLL
between the 12th and 1st hours. mus, there should be no pos~i-Z bility of energizing all four gate inputs 290, 292, 294, 296 simultaneously with potential L since the code LLLL is comple-mentary to the normal pattern of energization (0000) of the , counter output80 Should this occur in an intermediate pos~tion, j e.g. ~hile the cloc~ is being set, continuous strikes might be f executed by the striker mechanism, unt~l the wiper 264 is ;~ 25 sufficiently advanced by the hour shaft 2~5.
-~ An~ther advantageous feature of the coder 210 is apparent from FIG. 16 and lies in the ~act thst the ancil-lary conductors 273 - 275 are interrupted at aligned locations to form a radial gap through which associated leads 281, 282, 283 are brought out in the form of nsrrow, c7Osely -9o adjoinin~ conductor strips. ~he lead 2~0 to arc 260 can be connected to any of its segments 2vOa - 260f or to the ancillal~y conductor 273, because no overlappin~
problems occur there.
~he lead 272 for the inne~nost conductor 270 passes through the same gap.
i A~vantageously, the interruption of the ancillar~
conductors 273 - 275 occurs between positions lOOO (seg~ents 262a, 261b, 260d) and O~LL (segments 2~3a).
. I .
~10 ~he trigger mechanism 202 can also be desi~ned in a ;~ form similar to codes 210, with the contacts 213 and 214 I carried on the same printed-circuit board 259.
!
~he output 311 of ~JAND gate 310 is tied by a lead 312 to an input 313 of a NO~OR gate 315 having a second input 114 connected to the output of a NAND gate 316.
~he input 317 of this N~D gate 316 is connected to -the output lead 300 o~ counter 208 which is the first lead energized. The other input 318 of NAND gate 31~ is tied to the output 224 of ~AND gate 218 in circuit 203. ~he output 31 '~20 of ~OXO~ ~ate 315 is connected to the resetting input 320 of ... . .
flip-flop 204. A lead ~21 extends from the output 319 of ~O~OR
gate 315 to the clearing input 322 of counter 208.
If the striking mechanism is activated on the full hour, the pulses generated by the electronic pulse emitter 207 25 ~ advance the counter 208 until the number of strikes corresponcs to the position of the hour hand ~nd of coder 210.
108'~4f~?
This results ln the grounding of the output 311 of ~ND
gate 310 and of the input 313 of gate 3150 -At the ou~put 224 of the ~D gate 218 there now also exists the potential 0, 80 that J~D gate 316 i8 not switchable at this tim~o Thus the potential O lies at the input 313 of the I~OæOR gate 315, the potential L at its input 314. As a result, potential O appears at the output 319 of gate 315 and at the input 320 of flip-flop 204, resotting the latter and cutting off the transistor 205.
~' :
On the other band, if the activation of the striking mechanism ls initiated on the half-hour by the grounding of contact 214, potential L lies at the output 224 of ~ID
gate 218. After the counter 208 has counted the first strilce, potential L 8180 appears at its output 300. mese tim~ potentials are delivered - on the one hand by lead 323, l and on the other hand by lead 324 - to the inputs 317 and 318 Il of 17A~D gate 316, 80 that potentlal O is deliver~d at its i.-. output 314. At input 313 of gate 315 lies, however, potentlal L rom output 311 of I~A~D gate 310, 80 that already '~:20 after the f~rst stri1ee 11~ gate 315 i8 ~witched to reset the flip-flop 204. The graphs of FIG. 18 show the energi~zation ....
of the indilvidl~al logic sle~ents ~n the system of F~G. 12.
FIG. 13 show~ a m~dlflcation of ~hat 8y8tem in ~`: which a strllcing mechani~m 206' is actuated by an astable ltivibrator 205'; mechanl~m 206' may be a one-stroke bell.
, . .
, , .
' '.
i . !
~ 4 ~ 9 Such an arrangement works without contact, displays little ~usceptibility to trouble and exhibit~ a favorable current consumption.
Thi8 pulse emiiter 2071 i8 here shown as a pulse shaper in the output of multivibrator 205'.
FI~. 14 is a schematic representation of another modification of the circuit arrangement according to FIG.12.
In this instance a plurality of stage outputs 333, 334, 33 of a blnary frequency divided 331, driven by a crystal-10-controlled oscillator 330, are combiDed in an AND gate 205c to generate driving pulses of low du~y ratio which are pa~sed by another AND gate 205d as long as flip-flop 204 is set. Oscillator 330 and divider 331 also drive the clockwor~ 332 as part of unit 201.
Drive unit 205 and pul~e emitter 207 could be co~bined into a ~ingle unit.
, -27-., , ,
Claims (29)
1. In a timepiece comprising a clockwork with a minute shaft and an hour shaft, and a striking mechanism for announcing at least the full hour by sounding a variable number of strikes, the combination therewith of:
normally inactive drive means for operating said striking mechanism;
a normally reset flip-flop with a setting input, a re-setting input, and a set output connected to said drive means for activating same;
trigger means including a first rotating contact member coupled with said minute shaft for delivering a start signal to said setting input at least once per hour to activate said drive means;
electronic pulsing means synchronized with said strik-ing mechanism for emitting a number of voltage pulses proportion-al to said number of strikes;
a pulse counter with a stepping input connected to said pulsing means, output circuitry including a set of leads genera-ting a pattern of energization determined by the count of said voltage pulses, and a clearing input for establishing a zero pulse count; and deactivating means including said output circuitry and a second rotating contact member coupled with said hour shaft for delivering a stop signal to said resetting and clearing in-puts upon said pattern of energization bearing a predetermined relationship with the position of said hour shaft.
normally inactive drive means for operating said striking mechanism;
a normally reset flip-flop with a setting input, a re-setting input, and a set output connected to said drive means for activating same;
trigger means including a first rotating contact member coupled with said minute shaft for delivering a start signal to said setting input at least once per hour to activate said drive means;
electronic pulsing means synchronized with said strik-ing mechanism for emitting a number of voltage pulses proportion-al to said number of strikes;
a pulse counter with a stepping input connected to said pulsing means, output circuitry including a set of leads genera-ting a pattern of energization determined by the count of said voltage pulses, and a clearing input for establishing a zero pulse count; and deactivating means including said output circuitry and a second rotating contact member coupled with said hour shaft for delivering a stop signal to said resetting and clearing in-puts upon said pattern of energization bearing a predetermined relationship with the position of said hour shaft.
2. The combination defined in claim 1 wherein said trigger means comprises an electronic gating circuit switchable by said first contact member in a half-hour position and in a full-hour position thereof, said deactivating means further in-cluding a logic network connected to said gating circuit for generating said stop signal independently of the position of said hour shaft in said half-hour position.
3. The combination defined in claim 2 wherein said gating circuit comprises two substantially identical sections terminating at respective inputs of an anticoincidence gate of the Exclusive-OR type, each of said sections being divided into a pair of parallel branches of relatively inverting character and with a relative phase delay connected to the respective in-put of said anticoincidence gate through a further logic gate changing its state of conduction in response to a switchover during a brief interval determined by said phase delay in which said branches carry signals of identical logical values.
4. The combination defined in claim 3, further com-prising conductor means connected between said sections and a source of input voltage therefore, said conductor means being en-gageable by said first contact member for changing said input voltage in said half-hour and full-hour positions.
5. The combination defined in claim 4 wherein said conductor means comprises a single bank contact connected in parallel to said sections and engageable by said first contact member during a 30-minute sweep between said half-hour and full--hour positions.
6. The combination defined in claim 5 wherein said further logic gate is a NAND gate, further comprising an inverter inserted between said bank contact and one of said sections.
7. The combination defined in claim 4 wherein said conductor means comprises a pair of bank contacts respectively connected to said sections and engageable by said first contact member for a short period in said half-hour and full-hour posi-tions, respectively.
8. The combination defined in claim 7 wherein said further logic gate is an OR gate, further comprising a multi-vibrator with two cross-connected NAND gates respectively inserted between said bank contacts and said sections.
9. The combination defined in claim 4, 6 or 8 wherein one of said branches of each section includes an odd number of cascaded inverters establishing said relatively inverting charac-ter as well as said phase delay.
10. The combination defined in claim 2 wherein said logic network comprises a first gate and a second qate in cascade, said first gate having input connections to said gating circuit and to a lead of said output circuitry energized by said pulse counter upon the sounding of the first strike, said second gate having an input connection to a point of said output circuitry whose potential changes upon said pattern of energization and the position of said hour shaft bearing said predetermined relation-ship.
11. The combination defined in claim 10 wherein said second gate is an NAND gate.
12. The combination defined in claim 11 wherein said leads are twelve in number and are cyclically energized by a decoder forming part of said output circuitry, said leads ter-minating in an array of bank contacts swept by said second con-tact member in a 12-hour period, said point being tied to said second contact member.
13. The combination defined in claim 11 wherein said output circuitry further comprises a comparison network with in-put connections to said leads and to a set of contact arcs swept by said second contact member in a 12-hour period, said point being an output of said comparison network.
14. The combination defined in claim 13 wherein said comparison network comprises a plurality of discriminating stages working into a coincidence gate, each discriminating stage having one input tied to one of said leads and another input tied to one of said contact arcs.
15. The combination defined in claim 14 with four con-tact arcs and four discriminating stages, three of said contact arcs being divided into different numbers of segments arrayed according to a four-bit binary code assuming different values from one hour to the next.
16. The combination defined in claim 15 wherein said binary code is the complement of the pattern of energization of said leads by said pulse counter, said discriminating stages be-ing XOR gates.
17. The combination defined in claim 15 wherein said contact arcs are printed on a carrier plate traversed by said hour shaft.
18. The combination defined in claim 17 wherein said contact arcs have progressively larger number of segments with increasing distance from said hour shaft.
19. The combination defined in claim 17 wherein said carrier plate also supports an annular conductive strip engaged by said second contact member and connected to a source of fixed potential.
20. The combination defined in claim 17, 18 or 19 wherein said carrier plate also supports conductor means coacting with said first contact member.
21. The combination defined in claim 17, 18 or 19 wherein said carrier plate also supports integrated circuitry forming part of said clockwork.
22. The combination defined in claim 10, 12 or 13 wherein said second gate is an anticoincidence gate of the Exclusive-OR type.
23. The combination defined in claim 1, 2 or 3 where-in said drive means comprises a motor, said pulsing means com-prising a pulse generator driven by said motor.
24. The combination defined in claim 1, 2 or 3 where-in said drive means comprises an astable multivibrator, said pulsing means being an output circuit of said multivibrator.
25. The combination defined in claim 1, 2 or 3 where-in said drive means a crystal-controlled oscillator forming part of said clockwork and a binary frequency divider connected to said oscillator, said frequency divider having a plurality of stage outputs logically interconnected to generate a train of driving pulses with a duty ratio substantially smaller than 1:2.
26. The combination defined in claim 1, 2 or 3, fur-ther comprising a circuit breaker controlled by said clockwork for disabling said drive means during certain night-time hours.
27. The combination defined in claim 1 wherein said trigger means and said deactivating means comprise bank contacts on a common carrier respectively engaged by said first and second members.
28. The combination defined in claim 27 wherein said carrier is a printed-circuit board.
29. The combination defined in claim 28 wherein said printed-circuit board is traversed by said minute shaft and said hour shaft, said first and second contact members being wiper blades directly mounted on said minute and hour shafts, respec-tively.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19762609871 DE2609871C2 (en) | 1976-03-10 | 1976-03-10 | Electric hammer mechanism |
| DEP2609871.5 | 1976-03-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1082469A true CA1082469A (en) | 1980-07-29 |
Family
ID=5971989
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA273,686A Expired CA1082469A (en) | 1976-03-10 | 1977-03-10 | System for controlling the striking mechanism of a timepiece |
Country Status (4)
| Country | Link |
|---|---|
| CA (1) | CA1082469A (en) |
| DE (1) | DE2609871C2 (en) |
| FR (1) | FR2344061A1 (en) |
| GB (1) | GB1581066A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2753733A1 (en) | 1977-12-02 | 1979-06-07 | Kienzle Uhrenfabriken Gmbh | TIMED DRIVING GEAR |
| DE2817762A1 (en) * | 1978-04-22 | 1979-10-31 | Kieninger & Obergfell | CLOCK WITH STRIKING GLASS |
| DE9106112U1 (en) * | 1991-05-17 | 1992-09-10 | Junghans Uhren GmbH, 7230 Schramberg | Alarm clock |
| GB2436153A (en) * | 2006-03-14 | 2007-09-19 | David Hunt | Electronic clock with percussive audible time signal device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2109138C3 (en) * | 1971-02-26 | 1975-07-03 | Heinz Dr. 7220 Schwenningen Jauch | Large clockwork with Westminster chime or similar mechanism and battery-driven gear motor for the striking mechanism |
-
1976
- 1976-03-10 DE DE19762609871 patent/DE2609871C2/en not_active Expired
-
1977
- 1977-03-10 FR FR7707149A patent/FR2344061A1/en not_active Withdrawn
- 1977-03-10 GB GB1028277A patent/GB1581066A/en not_active Expired
- 1977-03-10 CA CA273,686A patent/CA1082469A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB1581066A (en) | 1980-12-10 |
| FR2344061A1 (en) | 1977-10-07 |
| DE2609871C2 (en) | 1982-05-27 |
| DE2609871A1 (en) | 1977-09-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |