CA1049144A - Vending control system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A vending control system including circuit means which control events and sequences of events involved in vending and paying out or refunding amounts deposited, the system employing a novel combination of full adder circuit means, binary stages, and input-output interconnections all of which provide increased versatility and flexibility. The system include means for the control of a number of vending price leads, with change making capability and without requiring interpricing lock-out systems in the vendor. To accomplish this the present system includes means to sense when a selection switch closes high impedance sensing means and for comparing the selection that is made to the amount of accumulation that has been entered before energy is applied to produce a vend operation.

Description

~491~
The present invention relates to a vending control system including circuit means which control events and sequences of events involved in the vending and paying out of amounts deposited. :
In recent years there has been a continuing evolution in the development of control circuits for vending ~.
machines and other coin controlled devices. The evolution has been from mechanical and electromechanical devices to .
relatively simple switch and relay controlled circuits and ~ :
devices, to fairly simple electronic circuits, through a ~`
transistor stage and silicon controlled rectifier stage and .
to even more sophisticated solid state circuits including integrated circuits. This evolution has produced more complicated and more sophisticated control circuits and has produced control circuits and systems of much greater flexibility, capability and dependability. Several recent developments in the evolutionary process are disclosed in Levasseur U.S. Patents 3,828,903, issued August 13, 1974 B and 3,829,634, issued August 13, 1974. The invention covered ~s by these -a_ represent significant advances and are stepping stone inventions to the present case. The construction disclosed in the present application contains some features that are somewhat similar to the contructions disclosed in the ..
aforesaid patents. ~:.
Vending control circuits and systems generally become more complex and more costly in relation to the number .:
of selections that are available at the discretion of the i customer, to the number of different or simultaneous price setting, to the change making capability that is provided, and to the optional features which are available including features such as escrowing, product selection, money value :.

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capability and so forth. The nature of the product or products being vended may also effect these matters.
The use of solid state logic to provide these and other functions in vend control devices has been utilized in many different vending control circuits including those mentioned above, and the number and complexity of the required logic gating circuitry increases rapidly with the number of possible vend prices and the number and value of different coins and coinage systems that can be accommodated in the coin unit and in change making.
The present system has the capability to provide a large number of different control sequences which can be programmed in many different ways to provide a control system which is much more flexible and versatile than any known system including those disclosed in the above-mentioned ~plicatio~s.
It is therefore a principal object of the present invention to provide a more versatile vending control system.
Another object is to increase the flexibilities, versatility and capability of vending control circuits.
Another object is to combine in a single vending control circuit selection monitoring means using optical couplers to direct set a particular vend price established by a pricing matrix.
Another object is to combine in a vend control ~ -circuit vend selection means and deposit-price comparison means.
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Another object is to compare the vend price with the amount accumulated due to coin deposits or otherwise and to allow particular selections to be made to enable a particular vend control line and at the same time to inhibit ;. . . . , :

~al49~L44 further selections and prevent simultaneous selections from being made in a vending control circuit.
Another object is to provide programmable means for con-trolling the operations and events that take place in vending machines and the like.
Another object is to provide a selection monitoring and deposit price comparison means in a vending control circuit.
Another object is to provide novel selection means for use in a vending control circuit.
In accordance with one embodiment, a control circuit comprises an adder network formed by a plurality of bi-stable -adder stages each including first and second inputs and an output, a first source of signals connected to the first adder network "
inputs, a second source of input signals connected to the second adder network inputs, said adder network including means to combine inputs from the first and second sources to produce out-puts at the adder output, and means for applying selected outputs of the adder network to selected ones of the second adder inputs `
to produce changes which further effect the adder outputs.
-20 In accordance with a further embodiment, a control logic circuit comprises first and second input signal sources ~ -and multi-stage adder circuit means for responding to combinations of the inputs from said sources to produce output responses for control purposes, said adder circuit means having a first input connected to the first signal source and a second input connected to the second signal source, said adder circuit means having output means at which binary control signals are produced depending on a binary combination of the inputs from the first and second sources present on the first and second adder circuit inputs, and means for selectively combining binary outputs of the adder circuit means with inputs applied to the second adder circuit inputs from the second input signal source.

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1~9~L~4 From a different aspect, in a vending logic control circuit for controlling vending functions, an embodiment consists of the improvement comprising a multi-stage binary adder circuit each stage of which has first and second inputs and an output, a first source of input signals and means connecting said first source to the first inputs of the adder circuit, said first source establishing a predetermined binary condition on the first adder circuit inputs, second input means including a multi-stage binary logic circuit having a binary stage corresponding to each of the .-adder circuit stages, each of the logic circuit stages having a ~.
direct set input and an output, means connecting the respective :
stage outputs of the logic circuit to corresponding second inputs :~
of the adder circuit stages, means for applying binary operating input signals to a selected direct set input of the logic circuit .
and to the corresponding second adder circuit input whereby binary :
outputs are produced at the outputs of the adder circuit which .
take into account a combination of the inputs present on the first and second adder circuit inputs, and other means for applying selected stage outputs of the adder circuit to selected direct set inputs of the logic circuit to modify the scheme of output signals present on the adder circuit.outputs. ~ :
In accordance with a still further embodiment, a vendcontrol circuit comprises means to receive and accumulate amounts ~
deposited in a vending machine, a multi-stage comparator circuit .~ ~ .
having first input means connected to the means to accumulate amounts deposited to feed said amounts to.the comparator circuit9 second comparator input means, a pricing matrix including customer actuated means operable by a customer to make a vend . -~
selection, said pricing matrix having outputs connected to the :.
second comparator input means to feed signals thereto to represent the price of a selected vend, said comparator circuit including :
means for comparing inputs representing the amounts deposited with ; .~.. ..... . .

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~049~4 the signals that represent the selected vend price and Eor pro-ducing outputs to represent the extent of the difference there-between, control logic circuit means to control the functioning of the vending machine including to control the production of the vending machine operations, said control logic circuit means including a multi-stage adder circuit each stage of which has a first input, a second input and an output at which binary ' responses are produced that represent a combination of binary :
signals applied to the first and seeond inputs, a first souree of binary input signals and means for applying input signals from the first source to the respective first inputs of the adder circuit stages, a second souree of binary input signals including multi-stage register means having direct set inputs :
at which signals from the seeond source are applied depending on a selection made by a customer, means for connecting the respective stage outputs of the register means to the ~. .
respective stage seeond inputs of the adder eireuit, and operator means eonneeted to seleeted stage outputs of the :
adder eireuit to produee a desired operating eondition when the eondition of the seleeted stage outputs are in a predetermined :
binary eondition. ~ ~:
In aeeordanee with a still further embodiment, there is provided, in a vend logie eontrol eireuit for eontrolling vending and related funetions, the improvement eomprising a multi-stage binary adder eireuit eaeh stage of whieh has first and seeond .
inputs and an output, a first souree input signals and means eonneeting said first souree to the first inputs of the adder eireuit, said first souree establishing a predetermined binary eondition at the first adder eireuit inputs, seeond input means ineluding a multi-stage binary logie eireuit having a binary stage eorresponding to each of the adder cireuit stages, each of the logic eireuit stages having a direet set input and ~ - 3b -~ . . . .

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an output, means connecting the respective stage outputs of the logic circuit to corresponding second inputs of the adder cireuit stages, means for applying a binary operating input signal to a selected direct set input of the logic circuit and to the corresponding second adder cireuit input whereby a binary output is produeed at the output of the adder eireuit whieh takes into aecount a combination of the inputs present on the first and second adder circuit inputs, said means for applying a binary operating input signal to a selected direct set input of the logie eireuit including a plurality of input eireuits each in-cluding an optical coupler having a light emitting diode portion responsive to an associated operating input signal and a photo-transistor portion responsive to light generated by the diode portion when an operating input signal is applied to the diode portion, the phototransistor portions of the respective optieal -:
eouplers being eonneeted in eireuit to respeetive direet set .;~
inputs of the logie eireuit stages, and other means for applying seleeted stage outputs of the adder eireuit to seleeted direet : :
set inputs of the logie eireuit to modify a seheme of binary ::: .
output signals present at the adder circuit outputs.
In the drawings which illustrate embodiments of the invention: , .
FIGURE 1 is a bloek diagram showing the more important eomponents and their intereonneetions in a vending eontrol eir-euit eonstrueted aeeording to the present invention, FIGURE 2 is a diagram showing more of the details , of the vend/payout eontrol logie of the eireuit in FIGURE 1, FIGURES 3-8b show different eombinations of binary outputs available from the subjeet eireuits, FIGURE 9a is a bloek diagram similar to FIGURE 2 but showing a modified embodiment of the vend/payout eontrol logie ~ .

and is found on the drawing page with FIGURES 9b and 16, 1, :
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FIGURE 9b is a truth table in explanation of the operation of the modified circuit portions shown in FIGURE 9a and is found on the drawing page with FIGURES 9a and 16;
FIGURES 10-15b show some of the possible binary outputs for the circuit shown in FIGURE 9a and is found on the drawing page with FIGURES 3-8b, FIGURE 16 shows another embodimen-t of the circuit ::
portions shown in FIGURES 2 and 9a and is found on the drawing - 3d - :

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page with FIGURES 9a and 9b, and, FIGURE 17 is a circuit diagram of the vend selection and reset input coupling circuits for the present system.
Referring to the drawings more particularly by reference numbers, number 20 in FIGURE 1 refers to a vend control circuit constructed according to one form of the present invention. The circuit 20 has a coin unit 22 which includes coin switches 24, 26 and 28 operated by the deposit of coins -of different denominations such as by nickels, dimes and quarters. Coin units of this general type are well known and are disclosed in many prior art patents including for example, Shirley U.S. Patent No. 3,307,671, dated March 7, 1967, assigned to Applicant's assignee. The coin unit 22 produces outputs when coins are deposited which are fed to an accumulation pulse circuit 30 which may also be of a known construction such as being a plurality of serially connected binary stages as shown in for example the same Shirley U.S. Patent, in - -Shirley U.S. Patent No. 3,521,733, dated July 28, 1970 and in Levasseur U.S. Patent No. 3,820,642, issued June 28, 1974.
The accumulator 30 has an output lead 32 connected to the CA input 34 of a comparator logic circuit 36. The comparator circuit 36 may be constructed similar to corresponding comparator circuit shown and described in Applicant's U.S. patent ~;
No. 3,841,456, issued October 15, 1974. The details of the comparator logic circuit 36 will not be described here except to the extent necessary for a full and complete understanding of the invention. The circuit 36 has other input and output connections including a first reset input 38 labelled RA, a second payout input 40 labelled CB, and a second reset ' , ~.

: ' , : ' ' , ,' .: ,'' . '. ' .' :. .'.. , :'. : ' .: ' ' '' : ' . . : ,'' .' ' . ", ' ' '' ,, ,' ~" : " ' '' '' " . ' ' ' ' ' ' ~ - ' , ; ,: , . ., : , input 42 labeled RB.
In addition, the comparator circuit 36 has a plurality of pricing inputs 44, 46, 48, 50 and 52 (also labeled SDl - SD5) connected to corresponding output stages of a pricing matrix 54.
The matrix 5~ provides vend price inputs corresponding to a selected vend product -to the comparator circuit 36 for comparison -therein with an amount deposited into the coin unit 22.
The comparator 36 has a plurality of output connections :.
at which signals are produced to represent different existing :-comparisons at different times. For example, the comparator has an A = B output 56 at which outputs are produced whenever the amount appli.ed to the comparator circuit from the accumulator 30 is the same as the vend price applied to the comparator from the pricing matrix 54. The outputs on the lead 56 are applied as one of two inputs to a comparator reset AND gate 58, the output of which is connected to the RA comparator reset input 38.
Another comparator output 60 is the ~ 2 output, and when a signal occurs on this output it is used to control the paying out of dimes. This can only occur in a nickel, dime, quarter system at times when there is at least two units of difference between the amount deposited and the vend price. Whenever the amount deposited equals or exceeds the vend price by at least five units (each unit representing a nickel) an output will occur on another comparator output 62 which is labeled > 5. This is the quarter payout control and is used to make re~unds of quarter coins.
Two other output condi.tions are available from the comparator circuit 36. One is the carry output condition COut ::
which is available on output lead 64 and the other outputs are ..
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available on lead 66 labeled B>O. The B >O condition is the condition when B is greater than zero; B being the vend price output. The output leads 64 and 66 are both connected as inputs to an OR gate 68 which has its output 70 connected to reset input RB f a vend/payout eontrol logic circuit 72 to be described later. The carry output lead 64 is also connected to the RB reset input terminal 42 of the comparator circuit 36.
The pricing matrix 54 provides a binary priee to the comparator circuit 36 whenever a selection interface 10 circuit 74 is activated by a price selection pulse which is made available by a customer activating a vend selection switch. The price selection signals or pulses occur at one or more of the vend selection terminals 76, 78, 80 and 82. The means that activate the terminals 76-82 are under control of switches and related circuitry in the vending maehine itself, and are not part of the present circuit as such. It is sufficient to note that almost any different eombination o~ switches can be u~ed depending on the number of products and vend prices available to the customer. The vend 20 selection terminals 76-82 are connected to the selection interfaee 74 by leads 84-90, respeetively, and the seleetion interfaee 74 is eonnected to the pricing matrix 54 by leads 92-98 and by other leads 100-106 to eorresponding input terminals 108-114 (labeled SD5, SD4, SD3, and SD2) of the vend payout eontrol logie eireuit 72. The construetion and operation of the cireuit 72 are important to the invention and several different embodiments will be deseribed.
The seleetion interfaee 74 i5 preferably formed using high input impedanee optical coupling devices whieh provide a low condition as seen by the price matrix 54 and '. '. ' ` ' ' ;' '. ' : ' ' '~

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provide any combination of lows to price inputs SD1 - SD5 of the comparator circuit 36. The circuit of these coupling devices is shown in Fig. 17 and will be described later.
When the selection price as established by the matrix 54 does not exceed the accumulation entered from the coin unit 22, the carry output (CO~ 64 and the B > O output 66 are both in low conditions providing lows to both inputs of the OR gate 68. This produces a low on the gate output lead 70 thereby removing the high that was present on the reset input RB of the logic circuit 72. This will allow the particular activated input lead 100-lQ6 to direct set the corresponding inputs of the logic circuit at input termina]; SD2 - SDs.
The vend/payout control logic 72 will generally have low outputs at output terminals S2 - S5 on leads 116-122 whenever an allowed selection is made while, at the same time, it will operate to inhibit any further selection by a signal that appears at carry output tCo) lead 124. This is accomplished by connecting the carry out lead 124 to inhibit input terminal 126 of the selection interface circuit 74.
This assures that only one selection will be allowed at any one time regardless of how many are possible to make.
The lows produced on the logic outpu-t leads 116-122 ;
are used to energize respective vend relays 116A-122A all of which have their opposite sides connected to a common high ~ voltage input. The low conditions on the leads will be terminated when a vend takes place. This occurs because of the action of another si~nal produced at terminal 128 during the vend cycle. When a vend takes place, vend motor 130 (or 131, 133 or 135) is energized and opens a respective motor switch 130A, 131A, 133A, or 135A that causes a signal ,' . .
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to be applied at the terminal 128 and to the input of a delivery interface circuit 134. The circuit 134 then applies its output to the first stage SDl input 136 of the logic circuit 72. This signal indicates that the vend has been successful or has been successfully initiated, and as soon as the vend operation is completed the output on lead 138 .. .
of the circuit 72 will go low for the purpose of initiating a change making operation i.f one is required. .- -If a payout or refund operation is required, the A = B output 56 of the comparator 36 will be low and will prevent the reset RA input 38 of the comparator 36 from going high until the payout pulsing is completed. The payout pulsing ~;
is from pulse payout circuit 1~0 under control of payout switch ~ .
142 and is applied to the payout input CB40 of the comparator .
logic 36 to increase the amount entered into the register from the price matrix 54 until it equals the amount accumulated and entered in the comparator A register from the coin accumulation circuit 30. When these amounts are equal the A = B output 56 will go high and cause the AND yate 58 to provide a high to the .-RA reset input 38 to reset the coin accumulation A register. .. ~ .
The same set of conditions will also cause the Cout output 64 .- ~- -to go high since the A register 30 now has less accumulation .. ~.: .
than the B register or matrix 54 (A s B). This condition in turn will reset the B register RB which at this time contained ..
an amount equal to the vend price plus the amount of the payback.
When this has happened there is total reset. -~
It is important to note that vend selection is made .: . :
possible and the power to produce the vend is provided through - .
a common connection under control of the four vend lines 84-90 . -and the associated terminals 76-82. Each of the terminals 76-82 ~ :

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may be connected to respective parallel connected vend selection switches 144, 145, 146 and 147 and to the associated vend motors 130, 131, 133 and 135. The means which make possible the effective operation of these inputs including the construction and operation of the interface means 74 and 134 may be somewhat similar to the means disclosed in Applicant's U.S. Patent No.
3,828,903, issued August 13, 1974, although there are also important differences. The present form of these means are disclosed in FIGURE 17 and will be described later.

VEND/PAYOUT CONTROL LOGIC

FIGURE 2 shows more of the details of one embodiment of the vend/payout logic circuit 72. The circuit 72 includes a full adder circuit 150, a five stage flip-flop input B register 152 with means to directly set each stage, and means including reset input (RB) 70 to totally reset the B register. The circuit of `
FIGURE 2 also includes means to feed certain of the outputs of the full adder 150 to certain direct set inputs of the B register 152 as will be described.
The full adder 150 has five A inputs (A1 ~ A5) which occur at terminals 156-16~. These inputs are all connected to a common positive (+) voltage source making them all have logical l's a condition represented as (11111). ~-Carry in (Cin) input 166 to the full adder 150 and clock input CB 167 of the B register 152 are shown grounded and therefore are in logical ~ero(0) states. The other inputs to the full adder 150 are applied at terminals 168-176 (labelled Bl -B5), and these inputs are connected to corresponding Ql ~ Q5 outputs ~ -178-186 of the B register 152. The flip-flops included in the B register 152 (not shown) are in total reset condition _ 9 _ ' .
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whenever a logic 1 is applied to reset inputs (RB) 70.
Under this condition the register Q outputs 178-186 are at logic zeros represented as (00000). Adding the A binary inputs ~11111~ at Al - A5 to the B binary inputs (00000) at Bl - B5 plus the binary (0) at the carry input (Cin) 166 results in a binary output sum (11111) present at adder output terminals (Sl - S5~ 13~, 116, 118, 120 and 122. This reset condition also produces a binary (1~ at carry output (C~ut) terminal 124. .
The adder output terminals 116-122 (S2 - S5) are connected respectively to corresponding sides of resistors 200-206, and the opposite sides o the resistors 200-206 are connected respectîvely to the direct set (SD2 - SD5) inputs 114, 112, 110 and 108 o~ the B register 152. The SDl B~register input 136 is connected through another resistor 208 to a positive voltage source and therefore always is at a binary (1~ state.
FIGURE 3 shows in binary language the resultant reset state of the ~ull adder circuit 150. The upper row of numbers refer to the respective circuit stages, the A row shows the binary condition of the A register inputs (Al - A5), the B
row shows the binary condition of the B-register inputs (Bl - B5), and the. S row is the binary condition of the adder outputs (Sl - S5~ plus the binary condition on the carry output ~ ., (COUt~ on lead 124. The Al - A5 inputs to the full adder 150 are in their binary (11111) state because of the connection of the A register inputs to the positive voltage source, the Bl - B5 adder inputs at reset are at (00000), and the sum adder outputs at Sl - Ss are there~ore (11111) with a carry out condition of (0). The Al - As inputs at reset are in the condition described because of the connections to a positive source to the A register inputs 156-164 and the A register :

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is held in its reset condition by ground connections to the CA and RA terminals 210 and 212 as shown in FIGURE 1.
FIGURE 4 shows what happens to the sum outputs at Sl - S5, which become 11110 with a carry out logic 1 also present on output lead 124, when a logic 0 input is present at vend selection terminal 76. This condition will occur when vend selection switch 144 is activated and causes a logic 0 to be present at terminal 76. The logic 0 is at S5 on lead 122 operates through the resistor 206 to apply a loyic 0 to the direct set input terminal (SD53 108 of the B register 152, and occurs even if the original logic 0 on terminal 76 is no longer present due : -to the inhibit function of the carry out signal on the lead 124 which prevents passage of other inputs through the selection interface circuit 74. In other words, the change that takes place in going from the condition represented by FIGURE 3 to the ~ .
condition represented by FIGURE 4 occurs because of a vend selection signal (logic 0~ initially having been present at the terminal 76 and also because of the change that takes place when :
a logic 0 is present on terminal tss~ 122. The condition shown in FI.GURE 4 which has a logic 0 on the S5 output lead 122 is :. :
therefore used to energi.ze vend relay 122A to cause the ~::
corresponding vend cycle. This is accomplished by the closing of the relay contacts 122B. :~
FIGURES 5a and 5b show similar types o~ changes that occur when a vend signal ~logic 0~ is present on the vend selection input terminal 78 due to customer actuation of the price selection switch 145 instead of on the terMinal 76 due ~-to actuation of the switch 144. In FIGURE 5a the logic 0 in this case is applied to the direct set input terminal (SD4) 110 of ~:~
the B register 152 and causes the adder input terminal B4 on the .

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lead 174 to be logical 1. This in turn causes the sum outputs on the leads Sl - S5 to change to 11100 with the carry out at terminal 124 being logic 1. This condition is illustrated in FIGURE 5a. The logic 0 condition on the S4 and S5 output terminals 120 and 122 are applied respectively to and -through the resistors 204 and 206 to the direct set B register inputs 110 and 108. The SD4 input has already caused the B4 adder input to go to a logic 1 and now the B5 input will also change to a logic 1 thus providing the conditions illustrated in FIGURE 5b where the B output is 00011. ~hen this new B register output is added to the A
register output 11111 at the adder input termi-nals 156-164 it causes the Sl - S5 outputs to change to 11101 with a logic 1 on the carry output on lead 124. The logic 0 at output S4 on lead 120 energizes vend relay 120A thereby closing relay contacts 120B to initiate the selected vend operation.
FIGURES 6a and 6b illustrate the conditions where a '' loyic 0 is applied to the vend selection input terminal 80 on the lead 88 due to customer actuation of th~ selection switch 146. This input is applied through the selection interface 74 to the direct set (SD3~ input terminal 112 of the B register 152 and results in an adder sum output of 11000 at terminals Sl - Ss and a logic 1 at the carry ou~ terminal 124. The logic O's at output terminals S3, S4 and Ss causes logic O's to be applied to the direct set input terminals SD3, SD4 and SD5 of the B register 152 through the respective resistors 202, 204 and 206. This provides a 00111 condition at the Bl - B5 inputs 168-176 of the full adder 150 as shown in FIGURE 6b, ~nd a sum output on terminals Sl - Ss of 11011 with a loyic 1 also at the carry output terminal 124. ~ence for this condition the vend relay 118A is eneryized and its contacts 118B close to produce the corresponding selected vend operation. ~ -. . ~ : :.
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FIGURES 7a and 7b illustrate the conditlon where a logic 0 is present on -the vend selection terminal 82 due to customer actuation of the selection switch 147 resulting in a 01000 condition on the Bl - Bs inputs to the full adder 150 and a sum output of 10000 at the S1 - Ss output terminals. This in turn is applied to the direct set inputs SDl - SD5 of the B
register 152 through the respective resistors 200, 202, 204 and 206 and results in a 01111 being applied to the Bl - Bs inputs of the adder circuit 150. As shown in FIGURE 7b, the new logic sum output on terminals Sl - S5 is 10111 again with a logic 1 at the carry output terminal 124. This is the condition necessary to energize the vend relay 116A and to close the contacts 116s to cause the appropriate vend operation to take place.
FIGURES 8a and 8b illustra-te the condition where a lo~ic 0 is present on the vend delivery input terminal 128 as a result o~ the opening o~ any one o~ the vend motor switches 13QA, 131A, 133A or 135A. This binary 0 input signal is applied to the delivery interface circuit 134 instead of to the selection interface circuit 74, and from there it is applied to the direct set (SDl~ input terminal 136 o~ the B register 152 resulting in a lOOQ0 condition at the Bl ~ B5 inputs 168-176 of the adder circuit 150, and a full adder sum output of 00000 at the output ~erminals Sl ~ S5 plus a logic 1 at the carry out terminal 1240 Four of these outputs are applied through the resistors 200-206 to respective direct set inputs SD2 - SD5 of the B register 152 resulting in a 11111 condition at adder inputs Bl - B5. When these inputs are added to the Al _ A5 inputs of 11111 the resultant adder sum outputs on terminals Sl - Ss is 01111 and a logic 1 on the carry out 124. This is the condition that is needed to energize the payout motor (not ,,: ' . -' .: ': ' .,, ., . ' . ., . : ': , ... ,: . ..
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shown~ which is connected to the adder output -terminal 138.
It can now be seen that in all of the situations described there is only one resultant logic 0 in the adder sum output Sl - Ss as shown in FIGURES 4, 5b, 6b, 7b and 8b for each input, and this is true regardless of when and how many inputs are directed to a logic 0 condition.
It is now apparent that with the circuit arranged and connected as shown in FIGURES 1 and 2 it is possible to obtain many different logic output conditions for logic control inputs .
such as from a plurality of logic conditions corresponding for example to different possible vend selections made at the discretion of a customer of a vending machine. There are many advantages to be obtained from the present form of control :
including the fact that it provides input control logic in the form of high impedance inputs and low impedance outputs while simultaneously inhibiting further selections from being ma~e effective by means of outputs that occur on the carry output lead 124 which is connected to the inhibit input terminal 126 of the selection interface circuit 74. Signals present at this terminal prevent other vend inputs from being able to pass through the circuit 74.
FIGURE 9a shows a circuit somewhat similar to that shown .
in FIGURE 2 except that it has different connections between the Sl - S5 outputs o~ the full adder 150 and the direct set input ~ ' terminals SDl - SD5 to the B register 152. In the FIGURE 9a construction these connections are scrambled as compared to similar connections in FIGURE 2 so that the S2 output lead 116 is connected through another resistor 222 to the direct ;
set input (SD4) 110 of the B register 152 instead of to the SD2 input 114 as in FIGURE 2. Also, in FIGURE 9a the S3 output of , .: . : , , - '' . :.
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the adder 150 on lead 118 is connected through another resistor 228 to the SD2 input 114 of the s register 152, and the S4 adder output on lead 120 is connected through resistor 232 to the SD5 input of the B register. These changed connections in FIGURE 9a as compared to FIGURE 2 provide a totally different logic scheme as will be explained. In the FIGURE 9a arrangement, certain combinations of logic 0 inputs are produced at the adder outputs Sl - Ss ana are used to control certain operations including certain operations in a vending machine or other device to be controlled. For example, one combination of adder outputs such as a logic 0 on the output lead 116 can be used to control a nickel payout motor used in the refundiny of nickels, another combination of adder outputs such as a logic 0 on the output lead 118 can be used to control the paying out of quarters, and still another combination such as a logic 0 on the output Ss on output lead 122 can be used to produce a vend output, The circuits as shown in FIGURES 2 and 9a and in any other desired combinations can also be constructed and used to provide and control a prescribed sequence of events as will be explained in connection with FIGURE
16. The output states of the adder circuit will always assume proper states even when a sequence of events is altered as by providing inputs at the direct set inputs SDl - SDs of the B
register.
In FIGURE 9a the inputs to the B register 152 are labe~led as to particular unctions which are to be controlled and may be -ontrolled by input signals received from customer actuated means as in the constructions already described. For example, a vend enable input may be produced by an input siynal directed to B register input SD5, and escrow enable input by a signal directed to B register input SD4, a nic~el enable input by a signal : ~

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directed to the B register input SD3r a dime enable input by a signal directed to the B register input SD2, and a coin return electromagnet operation (CREM) enable input by a signal directed to B register input SDl. Obviously other inputs and other conditions and/or sequences can also be provided using the same or similar formats.
FIGURE 9b shows a truth table ~or the circuit of FIGURE 9a using the inputs to the B register 152 just described.
In the truth table the ~irst position o~ the logic is ignored ~;
since this position does not change. The conditions of the second through the fifth positions (S2 ~ Ss) do change and are shown. For a vend control enable output the required output logic from the positions~S2 - S5 is 1110, for quarter payout enable the logic required is 1101, for dime payout it is 0011, for nickel payout 0111, and for CREM control the required output logic is 1011. These conditions and how they are obtained using the subject circuit are illustrated in FIGURES 10-15b which ~igures also show the order o~ a complete sequence covering all of the named situations. FIGURE 11 shows the vend state, FIGURE 12b shows the quarter payout state, FIGURE 13b -~
shows thedime payout state, FIGURE 14c shows the nickel payout ~
state, and FIGURE 15b shows the CREM control state. These states ;
are produced by logic 0's generated on the input leads and applied at the appropriate inputs to the B register 152 and to the ~ull adder circuit 150.
In FIGURE 12a a payout or escrow condition is initiated by a logic 0 at the register direct set input SD4 and at the B4 input to the adder. This input provides an adder sum output of 11100 and a logic 1 at the carry out. The logic 0 output on adder output S4 is applied through resistor 232 .
, , , , , , : .. , , . . :

~L~4~
to the register SD5 input causing the corresponding adder input B5 to go to logic 1 condition. This provides the adder logic output 11101 and a 1 carry out as shown in FIGURE 12b.
As aforesaid this is the condition necessary to enable a quarter payout operation.
In FIGURE 13a dime enable logic 0 is applied to the register input SD2 causing a logic 01000 to be present at the :
adder inputs Bl - Bs. This results in a logic output of 10000 at the adder sum outputs Sl - Ss. The logic O's present at the S2 and S4 outputs are applied through resistors 222 and 232 respecti~ely to the SD4 and SD5 inputs of the B register now causing a logic 01011 at the Bl - Bs adder inputs and changing the adder logic sum output to 10011 with a logic 1 carry out. This is the condition needed to enable dime payout as aforesaid. -.
In FIGURE 14a a nickel logic 0 input is applied to the SD3 input of the B register to produce a nickel payout condition. .:
This input causes a logic input to the adder on inputs Bl - B
of 00100 and a sum output at Sl - S5 of 11000 with a logic 1 carry out. This in turn applies logic O's to the resistors ~
228 and 232 and to the respective B register inputs SD2 and SD5 . -.
(FIGURE 14b) thereb~ producing logic l's at the corresponding adder inputs B2 and B5 making the output logic 10101. This logic output of the adder produces a further change in the adder output as illustrated in FIGURE 14c because of the logic O's present on S2 and S4 which change the adder input logic to 01111 at the Bl - Bs and the adder output logic to 10111 at the adder outputs Sl - Ss. A logic 1 carry out is also produced. .. -.
This output condition, which is produced in two steps instead ~ ~
3~ of one, establishes the condition necessary to enable the paying ..

9~4~ ~
out of nickels, see FIGURE 9b.
In FIGURE 15a an input logic 0 is present a-t the S
input to the B register to establish the output necessary to enable a CREM operation. This input produces a logic 10000 at the adder inputs Bl - B5 and results in a logic 00000 at the adder outputs Sl - S5. In this case, logic O's are applied through all three resistors 222, 228 and 232 to the respective direct set inputs SD4~ SD2 and SD5 of the B register, and corresponding logic l's are produced at the B4, B2 and B5 inputs of the adder resulting in adder input logic of 11011 (FIGURE 15b~. This in turn produces adder output logic of 01011 with a logic 1 at the carry out position and is the condition necessary to enable a CREM operation.
The circuits of FIGURES 2 and 9a represent only two of many possible variations of the subject means that can be made, and it is clear that the number of binary bit positions as well as the number and variation in the connections between the adder outputs and the B register inputs can be varied substantially to increase or decrease the number of possible situations and controls that can be accommodated. It is also contemplated to vary the form of the input logic applied to the A reyister to still further increase the number of output possibilities.
FIGURE 16 shows another possible embodiment of the connection means between the outputs of the adder and the inputs to the B register. The embodiment of FIGURE 16 has special usefulness as a means not only to produce various possible outputs but also as a means to control the sequencing of the inputs for some purposes when re~uired. The same operating procedures and rules apply to this construction as .
,, ", .. .. ...
:

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apply to the others except that with the FIGURE 16 construction the outputs must occur in a definite order. For instance when B register input SD5 is enabled by a logic 0, the logic 0 on the adder output S5 ~FIGURE 11~ starts time delay means 240 which delays the application of the logic 0 which is applied through diode 242 to the register input SD4 to enable the payout caused by having a lo~ic 0 occur at the adder output S4 to first be applied to register input lead SD2. It thereby applies a logic 0 to the register input SD2 removing the forced logic l from SD2 so that an inpu-t resistor 246, also connected thereto, may apply the logic 0 from the dime enable .:
input consequently causing the adder outputs S~ and S3 to go to their logic 0 states (FIGURE 13b). This in turn removes .
the forced logic 1 from being applied to B register input SD3 by way of another diode 248 to provide a logic 0 by way ;
of resistor 250 fxom -the nickel enable input. This completes the function as shown in FIGURE 14c. Thus the time delay provides that the vend output will remain on for a delay period as -:~
determined by the delay means 240 and will remain on for the ::
delay period before quarters are attempted to be paid ahead ~
of dimes, and thereafter nickels. :
The diode 244 and the resistor 246 provide an ~ND function ~:-. .
so that the adder output at terminal S4, which is in response to a dime enable input, must go to logic 0 before register input SD2 will go to a logic 0. In like manner, the diode 24~ :
and the resistor 250 provide an AND function from the adder output S3 to the register nickel input at terminal SD3. .
Other resistors 252 and 254 are connected respectively ~etween the adder outputs S2 and S4 and the B register direct set inputs SD4 and SD5, and they function in manners already described.

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It is possible as aforesaid to formulate other schemes using other variations and parameters including producing di~ferent arrangements o~ inputs on the A input terminals of the adder circuit. This can be done with and without interconnects and other changes in the adder outputs Sl - S5 and in the adder inputs Bl - B5. The present construction therefore provides a myriad of circuit and circuit control possibilities depending on the requirements of the particular application or applications, the applications described herein being for use with vending machines and is offered only by way of example. Not only does the present system offer an extremely large number of control possibilities, but it also offers the possibility of establishing priorities and priorities of sequences which may be useful in situations such as are described above to establish sequencing priorities whereby a payback function takes place in the least possible number o~
coins and in a way which tests each succeeding higher order coin denomination as to its availability, moving to test each -lower coin denomination in a particular order of priority and on a delayed sequence basis.
FIGURE 17 shows the details of a particular embodiment of the selection interface and delivery or reset inter~ace circuits 7~ and 134. In FIGURE 17 the vend selection inputs at terminal 76 are applied to a circuit which includes a capacitor 270 connected in parallel across a diode 272 in series with the light emitting portion of an optical coupling device 274. The opposite side of the parallel circuit is connected to one side o~ a resistor 276 which is connected to an intermediate location in a voltage divider circuit across the power supply formed by diode 278, resistor 280 and a parallel circuit formed by resistor 282 and capacitor 284. ~:
In the normal condition of this circuit the capacitor 284 has a charge that is about equal to the voltage across the power supply. When a signal (logic 0~ is present on the te.rminal 76 the charge present on the capacitor 284 will discharge through a low impedance circuit formed by the resistor 276 and the circuit which includes the light emitting diode 274 causing the light emitting diode to emit light and to activate the associated phototransistor portion 288 thereof. ~ .
The phototransistor portion 288 of the optical coupler 274 is physically located in the same envelope with the light emitting diode portion but is connected in another circuit which includes ~ :~
another diode 290 which has its opposite side connected to ::
the direct set input SD2 of the B register 152 in the vend payout control logic circuit 72. In the circuit as shown in FIGURE 17 the adder output S2 which is effected by a signal on -~ -SD2 is also connected through resistor 292 to the same direct set input SD2 and operates in a manner already described. ~ .
Similar circuits are included in the selection ~ :
interface circuit 74 in association with each of the other - .
input connections 78, 80 and 82. Each of these circuits has :: .
its own optical coupler formed by a light emitting diode and aasociated phototransistor connected in a manner similar to that described in connection with the i.nput circuit for the terminal 76, and it is not deemed necessary to describe each of these circuits in detail since they operate in the same way all usiny the capacitor 284 as the source of charge to energize the respective light emitting diodes.
The input terminal 128 is connected to one side of the power supply through a circuit which includes another ~D4~
capacitor 294 in parallel cross diode 296 in series with light emitting diode portion of another optical coupler 298. This circuit also includes another resistor 300. The input terminal 128 is also connected through the one or more coin return electromagnet coils 302 and 304 to the opposite side o~ the line at terminal 306. When an input or vend reset signal is indicated by the removal of power on power lead 310 because of operation of one of the motor switches 130A, 131A, 133A -or 135A when the associated motor 130, 131, 133 or 135 is energized this removal of the short (which was shorting the diode portion of the optical coupler 298 and other associated circuitry~ causes the path of current to energize the optical coupler 298 through a circuit which includes the CREM coils 302 and 304 to the lead 306. When this occurs it also enables current to flow through the phototransistor portion 308 of the same optical coupler 298. The phototransistor 308 is connected into a circuit with the direct set input S~l to the B register 152 as already described and as shown. The current flow through the coin return electromagnets tCREMS~ 302 and 304 from one side of a power supply on the lead 310 through the CREMS to the other side of the power supply is not sufficient to energize the CREMS even through sufficient to energize the optical coupler 298.
The carry out COut terminal of the circuit 72 is eonnected to lead 124 and has a connection to one side of the transistor portions of the four light emitting diode portions of the optical eouplers associated with the input terminals 76, 78, 80 and 82 so that whenever the lead 124 is at a logic 1 condition it prevents or inhibits any further input signals from effeetively actuating the selection interface ' '~
.: , ,.- ,. , . . :

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1~91~9~
circuit 74 in the manner indicated. This is because when lead 124 is at logic 1 it will then no longer be possible -for a signal to be applied to the corresponding direct set inputs SD2 - SD5 of the B register 152.
The subject control system differs :from prior art systems including the one disclosed in Applicant's own U.S.
Patent No. 3,841,456, issued October 15, 1974, in that it includes many other features and is able to perform many more control functions. This includes being able to provide multiple ~ ~.
vend control functions utilizing a unique combination of a full adder, a binary register, and interconnecting circuitry. ~.
Nothing like this is disclosed in the prior art. The subject ~.
system can also be used with any other accumulation and price selection circuits including those shown in Applicant's ~
patents, and in many other systems for that matter, and :~:
when this is done it provides versatile means to accomplish .
simple as well as complex control functions lncluding simple .
and complex vending control and change making functions. The .
subject system lends itself to easily providing numerous .
different vending and other types of control applications using the same basic circuit design and circuit elements and in some cases requiring only relatively minor changes in the circuitry and in the interconnections, including particularly the interconnections between the outputs of the adder circuit and the inputs to the registers. It can therefore be seen that .
the circuit means shown in F~GURE 17 represent an important more versatile improvement over selection monitoring means such as shown in Applicant's patents 3 7 841,456, issued October 15, 1974 and 3,828,903, issued August 13, 1974. Note especially in this regard the present circuit employs a capacitor which is charged , ~" '.' ',' .
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., ,, : ,, ,, . . , , . : .

and remains charged because of the way it is connected to the line vol-tage, and it discharges through a selected light emitting diode only when a selection circuit is closed by operation of a selection switch under control of the customer.
In prior constructions such as disclosed in Applicant's above-mentioned patents, a capacitor is charged through circuit means only after a selection switch is closed. This is opposite from the present capacitor charging circuit and is an important structural and operational difference between them. This is important because it means that the capacitor in the present circuit is always ready and able to discharge immediately and in a very short time duration and is able to provide sufficient current flow through the selected light emitting diode to perform its necessary functions. The advantage of this over prior constructions is that the capacitor discharge cycle (time constant) dictates how long the light emitting diode will be signaled or energized, and without having to have the light emitting diode look through a capacitor to a power source as in prior constructions but instead has the diode look to a capacitor that has already looked through to the energy source and been charged thereby. ~Ience, the present circuit teaches a different technique to interface input signals in a control circuit including reset input signals used to terminate a vend operation and signals used to control the change over from a vend to a payout operation. The present circuit also utilizes the same power supply line which controls the energizing of the coin return electromagnets (CREMS3 to charge the capacitor, and the light emitting diode portion ~ ;
of the optical coupler 298 which operates in the circuit ~-with the CREMS when deenergized by removing the line voltage

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appearing on the lead 310 from the opposite side of the line voltage which appears at terminal 306. In other words, in :
the present circuit the lead 128 is always connected to the lead 310 and to the lead 312 through the CREM coils 302 and 304. This means that when the CREMS are energized they will remain energized until the lead 128 opens which occurs at the time a product is being delivered. This is because the optical coupler 298 will be shorted out until such a time as the input on lead 128 is open as explained, and thereafter .:
the lead 128 will no longer be shorted and will draw current ~:
through the CREMS 302 and 304 sufficient to activate the .. .
light emitting diode 298 but not sufficient to energize the CREMS. For these reasons the present circuit is substantially ~ -different from anything known heretofore including the circuits shown in Applicant's above-mentioned patents.
Thus there has been shown and described several embodiments of a novel control circuit for controlling vending and other operations which fulfill all of the objects and advantages sought therefor. It will be apparent to those skilled in the art, however, that many changes, variations, modifications and other uses and applications of the invention in addition to those already mentioned and disclosed, are possible and are contemplated. A11 such changes, variations, modifications and other uses and applications which do not depart from the .. ~ .
spirit and scope of the invention are deemed covered by the .. .
invention which is limited only by the claims which follow. . .

- 25 - ~

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Claims (27)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A control circuit comprising an adder network formed by a plurality of bi-stable adder stages each including first and second inputs and an output, a first source of signals connected to the first adder network inputs, a second source of input signals connected to the second adder network inputs, said adder network including means to combine inputs from the first and second sources to produce outputs at the adder output, and means for applying selected outputs of the adder network to selected ones of the second adder inputs to produce changes which further effect the adder outputs.

2. The control circuit of claim 1 wherein all of the signals from the first source applied to the stages of the adder network are similar binary signals.

3. The control circuit of claim 1 wherein the second source of input signals includes means for selectively applying binary signals to the respective second inputs to the adder stages.

4. The control circuit of claim 1 wherein the second source of input signals includes a plurality of input signal connections at which input signals for different purposes are produced, means interfacing said input signal connections to the second stage inputs to the adder network, and means operatively connected between the second adder network inputs and the interface means including a multi-stage bi-stable register having inputs for connection to the respective input signal connections and outputs for connection to respective second inputs to the adder network.

5. The control circuit of claim 4 including means connected between a selected adder network output and the interface means to prevent more than one input signal appearing on the input signal connections from the second input source from being applied to the second adder network input during any one operation.

6. The control circuit of claim 1 wherein the means for applying selected adder network outputs to selected ones of the second adder inputs include a resistive circuit connection therebetween.

7. The control circuit of claim 1 wherein the means for applying selected adder network outputs to selected ones of the second adder inputs include signal rectifier means.

8. The control circuit of claim 1 wherein the means for applying selected adder network outputs to selected ones of the second adder inputs include signal delay means.

9. The control circuit of claim 1 wherein the means for applying selected adder network outputs to selected ones of the second adder inputs include connections between the outputs of selected adder stages and inputs to different stages of the adder network.

10. The control circuit of claim 1 including an output connection to each stage of the adder network, an operator member connected to selected ones of said output connections for energization when the associated output is in a predetermined binary condition, and switch means actuated when the associated operator members are energized, said switch means controlling the application of input signals from said second source to the second adder network inputs.

11. The control circuit of claim 10 including other means for applying an input signal from said second source to a second adder network input, said last named means including second interface means having an input operatively connected to said second signal source, an output operatively connected to a selected second adder input, and second switch means actuatable during operation of a function under control of energizing of an operator member.

12. A control logic circuit comprising first and second input signal sources and multi-stage adder circuit means for responding to combinations of the inputs from said sources to produce output responses for control purposes, said adder circuit means having a first input connected to the first signal source and a second input connected to the second signal source, said adder circuit means having output means at which binary control signals are produced depending on a binary combination of the inputs from the first and second sources present on the first and second adder circuit inputs, and means for selectively combining binary outputs of the adder circuit means with inputs applied to the second adder circuit inputs from the second input signal source.

13. The control logic circuit of claim 12 wherein the adder circuit means include a multi-stage full adder circuit.

14. The control logic circuit of claim 12 wherein one of the first and second input signal sources includes a multi-stage bi-stable register circuit.

15. The control circuit of claim 12 wherein the second input signal source includes means for selectively applying a binary input signal to a stage of the adder circuit means.

16. The control circuit of claim 15 including means operatively connected between the output of the adder circuit means and one of the input signal sources to control the application therefrom to the adder circuit means of input signals.

17. The control circuit of claim 12 wherein the adder circuit output means includes a terminal at which binary carry output signals are produced.

18. In a vending logic control circuit for controlling vending functions, the improvement comprising a multi-stage binary adder circuit each stage of which has first and second inputs and an output, a first source of input signals and means connecting said first source to the first inputs of the adder circuit, said first source establishing a predetermined binary condition on the first adder circuit inputs, second input means including a multi-stage binary logic circuit having a binary stage corresponding to each of the adder circuit stages, each of the logic circuit stages having a direct set input and an output, means connecting the respective stage outputs of the logic circuit to corresponding second inputs of the adder circuit stages, means for applying binary operating input signals to a selected direct set input of the logic circuit and to the corresponding second adder circuit input whereby binary outputs are produced at the outputs of the adder circuit which take into account a combination of the inputs present on the first and second adder circuit inputs, and other means for applying selected stage outputs of the adder circuit to selected direct set inputs of the logic circuit to modify the scheme of output signals present on the adder circuit outputs.

19. The control circuit of CLAIM 18 including means to prevent the application of more than one binary operating input signal to the direct set inputs of the logic circuit during any one operating function.

20. The control circuit of claim 18 wherein more than one adder circuit stage output is connected to direct set stage inputs of the logic circuit.

21. The logic control circuit of claim 20 wherein a resistor is connected in the circuit between at least one adder circuit stage output and a direct set input of the logic circuit.

22. The control circuit of claim 20 wherein a diode is connected in the circuit between at least one adder circuit stage output and a direct set input of the logic circuit.

23. The control circuit of claim 20 wherein a time delay device is connected in the circuit between at least one adder circuit stage output and a direct set input of the logic circuit.

24. A vend control circuit comprising means to receive and accumulate amounts deposited in a vending machine, a multi-stage comparator circuit having first input means connected to the means to accumulate amounts deposited to feed said amounts to the comparator circuit, second comparator input means, a pricing matrix including customer actuated means operable by a customer to make a vend selection, said pricing matrix having outputs connected to the second comparator input means to feed signals thereto to represent the price of a selected vend, said comparator circuit including means for comparing inputs representing the amounts deposited with the signals that represent the selected vend price and for producing outputs to represent the extent of the difference therebetween, control logic circuit means to control the functioning of the vending machine including to control the production of the vending machine operations, said control logic circuit means including a multi-stage adder circuit each stage of which has a first input, a second input and an output at which binary responses are produced that represent a combination of binary signals applied to the first and second inputs, a first source of binary input signals and means for applying input signals from the first source to the respective first inputs of the adder circuit stages, a second source of binary input signals including multi-stage register means having direct set inputs at which signals from the second source are applied depending on a selection made by a customer, means for connecting the respective stage outputs of the register means to the respective stage second inputs of the adder circuit, and operator means connected to selected stage outputs of the adder circuit to produce a desired operating condition when the condition of the selected stage outputs are in a predetermined binary condition.

25. The vend control circuit of CLAIM 24 including at least one connection between a selected adder circuit stage output and a selected direct set input to the register means, occurrence of a predetermined binary condition on said selected adder circuit stage output producing a further change in the adder circuit output and in the control function produced thereby.

26. In a vend logic control circuit for controlling vending and related functions the improvement comprising a multi-stage binary adder circuit each stage of which has first and second inputs and an output, a first source input signals and means connecting said first source to the first inputs of the adder circuit, said first source establishing a predetermined binary condition at the first adder circuit inputs, second input means including a multi-stage binary logic circuit having a binary stage corresponding to each of the adder circuit stages, each of the logic circuit stages having a direct set input and an output, means connecting the respective stage outputs of the logic circuit to corresponding second inputs of the adder circuit stages, means for applying a binary operating input signal to a selected direct set input of the logic circuit and to the corresponding second adder circuit input whereby a binary output is produced at the output of the adder circuit which takes into account a com-bination of the inputs present on the first and second adder circuit inputs, said means for applying a binary operating input signal to a selected direct set input of the logic circuit including a plurality of input circuits each including an optical coupler having a light emitting diode portion responsive to an associated operating input signal and a phototransistor portion responsive to light generated by the diode portion when an operating input signal is applied to the diode portion, the phototransistor portions of the respective optical couplers being connected in circuit to respective direct set inputs of the logic circuit stages, and other means for applying selected stage outputs of the adder circuit to selected direct set inputs of the logic circuit to modify a scheme of binary output signals present at the adder circuit outputs.

27. The vend logic control circuit of claim 26 at least one of said optical couplers is connected in parallel with a shorting circuit across a power source, and means to energize the optical coupler including means to momentarily remove the shorting circuit.