BRPI0922986B1 - SELF-ADJUSTMENT OF SIGNAL PATH DELAY IN CIRCUIT EMPLOYING MULTIPLE VOLTAGE DOMAINS - Google Patents

Abstract

SELF-ADJUSTING SIGNAL PATH DELAY IN CIRCUIT EMPLOYING MULTIPLE VOLTAGE DOMAINS Disclosed are circuits and methods provided in multiple voltage domains that include self-adjusting or timing a signal path. A plurality of paths are provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-adjusted or adjusted according to the delay in the plurality of paths. Such auto-tuning may be particularly suitable for controlling the delay of a first signal path relative to a second signal path where the delay in the paths may vary relative to each other during operation.

Description

FIELD OF INVENTION

Revealing technology generally refers to the timing of one or more signal paths in a multi-voltage domain circuit. Revealing technology also refers to the timing of one or more signal paths in memory circuits.

DESCRIPTION OF THE PRIOR ART

Circuits are increasingly being designed with energy conservation in mind. This is particularly the case for portable electronic devices that are battery powered. Common examples include mobile phones and laptop computers, among others. Higher power consumption undesirably results in faster battery depletion and reduced battery life. One method of conserving energy is to decrease the operating frequency of the circuit according to the active power equation P = CV2f. However, reducing the operating frequency results in lower circuit performance (i.e., speed). Another method of conserving energy is to decrease the operating voltage level since generally, active power decreases quadratically for a given reduction in operating voltage level. However, decreasing the operating voltage level in a circuit decreases speed performance, which may also be undesirable. Furthermore, certain cells or components in a circuit may have a minimum operating voltage below which they will not operate properly. To address the trade-off between performance and power consumption, multiple operating voltage domains ("voltage domains") are increasingly being provided in circuits. Circuit paths are provided that pass through the multiple voltage domains to provide different operating voltages to different components in a circuit. Providing multiple voltage domains allows a lower voltage domain to provide power to components that do not require minimum voltage levels to conserve power. Components that have a minimum operating voltage level for proper operation or that provide critical paths where performance cannot be sacrificed can be driven by the higher voltage domain. Providing multiple voltage domains also allows the lower voltage domain to be reduced to conserve power during a power conservation mode, or expanded to provide more performance (i.e., hyper performance), without affecting the operation of components in the higher voltage domain.

Examples of circuits where multiple voltage domains are commonly employed are memory circuits and memory systems. One example is static random access memory (SRAM). SRAM can be used in cache memory. SRAM cells have a minimum operating voltage level to maintain stability and retain data properly. In addition, the minimum operating voltage is higher to address minimum operating voltage issues for SRAM cells provided in sub-micrometer, sub-one hundred (100) nanometer (nm) deep geometries, such as sixty-five (65) nm and forty-five (45) nm geometries as examples. An example of a SRAM system employing multiple voltage domains is illustrated in Figure 1. Provided herein is an exemplary SRAM memory system 10 (referred to as "memory system 10"). Input lines 12 and output lines 14 are coupled to memory system 10. Input lines 12 and output lines 14 carry signals to enable data and command communication between memory system 10 and other system components that write or read data to and from an array of SRAM cells 16, which operates as a mass memory device. A control system 18 controls the operation of the SRAM cell array 16. The memory system 10 contains two signal paths, labeled "access path" 20 and "detect path" 22. The access path 20 transfers access signals from the control system 18 to word line drivers 26 (i.e., row selector), possibly through intermediate logic 24. In response, the word line drivers 26 activate a specific row of memory cells within the SRAM cell array 16 in response to address information from the control system 18. The address information identifies a specific row in the SRAM cell array 16 to be selected. The row may be selected for a read or write operation. In response, data from the selected row in SRAM cell array 16 is placed on bit lines 28. To read the data placed on bit lines 28, control system 18, and possibly intermediate logic 30, communicates a sense signal to sense amplifiers 32 to perform a read on bit lines 28. Sense amplifiers 32 detect data from bit lines 28 and place the data on output lines 14.

In memory system 10, the timing for signals to traverse access path 20 and detection path 22 is compatible. Specifically, memory system 10 is designed such that a sense pulse signal communicated by control system 18 via sense path 22 does not cause sense amplifiers 32 to sense data on bit lines 28 before access signals are communicated by control system 18 via access path 20 to cause SRAM cell array 16 to assert data on bit lines 28. Otherwise, sense amplifiers 32 will sense data on bit lines 28 before SRZXM cell array 16 has asserted valid data on bit lines 28. It is acceptable for access signals communicated via access path 20 to reach SRAM cell array 16 before sense signals reach sense amplifiers 32 via sense path 22. In this scenario, data on bit lines 28 will be present before sense amplifiers are activated. 32 to detect data on bit lines 28. The access path delay 20 in memory system 10 provides the minimum delay for which sense signals must traverse sense path 22 to sense amplifiers 32. Memory system 10 of FIG. 1 operates in an upper voltage domain VH provided at the minimum voltage level VMIN sufficient to provide stable operation and data storage in SRAM cell array 16. Input lines 12 and output lines 14 are provided from components that are provided in a lower voltage domain VL. In this regard, one or more level shifters 34 are provided to convert the signals on input lines 12 from the lower voltage domain VL to the upper voltage domain VH. The signals communicated from the sense amplifiers 32 to the output lines 14 may be converted from the upper voltage domain VH to the lower voltage domain VL with or without one or more level shifters 36. It may be desirable to drive certain components or portions of the memory system 10 in a lower voltage domain VL. Providing multiple voltage domains in a circuit allows the scaling of one voltage domain to conserve power without affecting the operation of components driven by other voltage domain(s). However, since the different voltage domains operate independently, the voltage level differential between them may vary. Variations in voltage levels between different voltage domains may cause discrepancies in signal path delays in a circuit. Large discrepancies may render the circuit nonfunctional.

SUMMARY OF THE INVENTION

Embodiments disclosed in the detailed description include circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path. In this regard, multiple paths are provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be suitable for use in circuits and methods where it is desired to control the delay of a first signal path relative to a second signal path, and the timings in the paths may vary relative to each other due to delay variations caused by voltage level variations between multiple voltage domains.

In certain embodiments disclosed herein, a first path is provided which traverses a first portion of the plurality of voltage domains. The first portion is a subset of the plurality of voltage domains which may consist of any number or combination of the plurality of voltage domains. A second path is provided which traverses a second portion of the plurality of voltage domains. The second portion is also a subset of the plurality of voltage domains which may consist of any number or combination of the plurality of voltage domains. A delay circuit is coupled to the first path. The delay circuit includes at least a first delay element whose voltage is configured to be supplied by a first voltage supplied by the first portion among the plurality of voltage domains, and at least a second delay element whose voltage is configured to be supplied by a second voltage supplied by the second portion among the plurality of voltage domains. In this manner, the delay circuit, by including delay elements being supplied with voltage from the first and second portions of the plurality of voltage domains, will monitor delay changes in the second portion caused by variations between the plurality of voltage domains. The delay circuit generates a delay output in response to the largest delay between the first portion and the second portion of the plurality of voltage domains. The circuits and methods disclosed herein can be employed in memory systems where the timing or delay of an access path and a detection path is controlled to access memory. Such memory systems include those included in processor-based systems. For example, the circuits and methods disclosed herein can be employed in a memory system employing static random access memory (SRAM). The memory system may be designed such that certain components are included in a lower voltage domain to conserve power, while the SRAM is included in an upper voltage domain to provide a minimum operating voltage level for cell operation. The memory system includes an access path to cause the SRAM to assert data on bit lines and a sense path to control when the sense amplifiers sense the bit lines. Changes in voltage levels between the upper and lower voltage domains may change the delay of the access path and the sense path. In this regard, at least one delay element whose voltage is supplied by both the upper voltage domain and the lower voltage domain is provided in the sense path. In this manner, the at least one delay element adjusts or self-adjusts the delay of the sense path according to the path having the largest delay between the lower and upper voltage domains so that the sense amplifiers do not sense the bit lines before the SRAM asserts valid data on the bit lines.

BRIEF DESCRIPTION OF THE FIGURES

Figure 1 is a block diagram of an exemplary memory circuit and system; Figure 2 is a block diagram of an exemplary memory circuit and system employing a delay element to auto-adjust the delay of a detection path; Figure 3 is a block diagram of an exemplary delay element to auto-adjust the delay of a signal according to the longest delay path between a lower voltage domain; Figure 4 is a block diagram of an alternative exemplary delay element to auto-adjust the delay of a signal according to the longest delay path between multiple voltage domains; Figure 5 is a block diagram of another alternative exemplary delay element to auto-adjust the delay of a signal according to the longest delay path between multiple voltage domains; Figure 6 is a block diagram of another alternative exemplary delay element for auto-adjusting delay of a signal according to the longest delay path between multiple voltage domains; and Figure 7 is a block diagram of an exemplary processor-based system in which circuitry and methods according to embodiments described herein may be provided.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to the drawing figures, several exemplary embodiments of the present disclosure are described. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be considered as preferred or advantageous over other embodiments. The embodiments disclosed in the detailed description include circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path. In this regard, multiple paths are provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. Such self-tuning may be suitable for use in circuits and methods where it is desired to control the delay of a first signal path relative to a second signal path, and the timings in the paths may vary relative to each other due to delay variations caused by variations in voltage levels between multiple voltage domains.

In certain embodiments disclosed herein, a first path is provided that traverses a first portion of the plurality of voltage domains. The first portion is a subset of the plurality of voltage domains that may consist of any number or combination of the plurality of voltage domains. A second path is provided that traverses a second portion of the plurality of voltage domains. The second portion is also a subset of the plurality of voltage domains that may consist of any number or combination of the plurality of voltage domains. A delay circuit is coupled to the first path. The delay circuit includes at least a first delay element whose voltage is configured to be supplied by a first voltage supplied by the first portion among the plurality of voltage domains; and at least a second delay element whose voltage is configured to be supplied by a second voltage supplied by the second portion among the plurality of voltage domains. In this manner, the delay circuit, by including delay elements being supplied with voltage from the first and second portions among the plurality of voltage domains, will track delay changes in the second portion caused by variations among the plurality of voltage domains. The delay circuit generates a delay output in response to the largest delay between the first portion and the second portion among the plurality of voltage domains. The circuits and methods disclosed herein may be employed in memory systems where the timing or delay of an access path and a detection path is controlled to access memory. Such memory systems may include processor-based systems. In this regard, Figure 2 illustrates an exemplary memory system 44 that may employ at least one delay element to adjust the delay of a signal path to the path having the largest delay among multiple voltage domains. The memory system 44 employs static random access memory (SRAM), but any type of memory may be employed. Input lines 46 and output lines 48 are coupled to the memory system 44. The input lines 46 and output lines 48 carry signals to enable data and command communication between the memory system 44 and other system components that read data from, and write data to, an array of SRAM cells 50. The array of SRAM cells 50 operates as a mass storage device in this embodiment. The memory system 44 contains two signal paths: an access path 54 and a sense path 56. A control system 52 is provided to communicate an access signal via the access path 54 to word line drivers 58 (i.e., row selectors). Access signals may pass through intermediate logic 60 in access path 54. In response, word line drivers 58 operate to activate a specific row of memory cells within SRAM cell array 50 in response. The row in SRAM cell array 50 may be selected for a read operation or for a write operation. In response, data from the selected row in SRAM cell array 50 is asserted on bit lines 62. To read the data asserted on bit lines 62 via SRAM cell array 50, control system 52 communicates a sense signal to one or more sense amplifiers 66 via sense path 56. The sense signal may pass through intermediate logic 61, 64 in sense path 56. In response to receiving the sense signal, sense amplifiers 66 perform a read on bit lines 62 to sense data from bit lines 62. Sense amplifiers 66 direct the sensed data to output lines 48 for passing to other components or systems outside of memory system 44.

In memory system 44, the delays for signals to traverse access path 54 and sense path 56 are compatible. Specifically, the components of memory system 44 are tuned such that a sense signal communicated through sense path 56 does not cause sense amplifiers 56 to sense data on bit lines 62 before SRAM cell array 50 asserts data on bit lines 62. Otherwise, sense amplifiers 66 will sense data on bit lines 62 before SRAM cell array 50 has asserted valid data on bit lines 62. It is acceptable for access signals communicated through access path 54 to reach SRAM cell array 50 before sense signals reach sense amplifiers 66 within a certain delay margin. In this scenario, data on bit lines 62 will be present when sense amplifiers 66 are activated. The access path delay 54 in memory system 44 provides the minimum delay for which a sense signal can traverse sense path 56 to sense amplifiers 66. To conserve power and/or to improve voltage scaling for memory system 44, two voltage domains are provided in memory system 44. A lower voltage domain VL in a first portion 45 of memory system 44 and an upper voltage domain VH in a second portion 47 of memory system 44 are provided. Both lower voltage domain VL and upper voltage domain VH are supplied with voltages from the first and second voltage supplies, respectively. A lower voltage domain VL is a voltage domain that generally provides a lower voltage level than the upper voltage domain VH. As an example, a default voltage level provided by the lower voltage domain VL may be 0.75 volts, and the default voltage level provided by the upper voltage domain VH may be 1.1 volts. In this example, the first portion 45 traverses the lower voltage domain VL exclusively, and the second portion 47 traverses the upper voltage domain VH exclusively. However, a first portion and/or a second portion of the memory system 44 could be provided that traverses both the lower voltage domain VL and the upper voltage domain VH. Alternatively, the first portion 45 may traverse both the lower voltage domain VL and the upper voltage domain VH and the second portion 47 may traverse only the upper voltage domain VH or vice versa. The first and second portions 45, 47 may be provided to traverse any combination of multiple voltage domains.

The voltage domains may be adjusted during operation, such as to provide voltage scaling for hyper performance or reduced power consumption, as examples. In this example, input lines 46 and output lines 48 are sourced from components provided in a lower voltage domain VL. The control system 52 and intermediate logic 60, 61 are driven by the lower voltage domain VL to conserve power. Thus, components in both access path 54 and sense path 56 are driven by the lower voltage domain VL. Thus, the delay in access path 54 and sense path 56 is affected by the voltage level of the lower voltage domain VL. In this example, components in access path 54 and sense path 56 are also driven by the upper voltage domain VH in memory system 44 of Figure 2. The upper voltage domain VH is provided to operate SRAM cell array 50. SRAM cell array 50 is provided in the upper voltage domain VH to provide a minimum operating voltage level, VMIN, independent of the lower voltage domain VL, for proper operation of the SRAM cells. For example, VMIN may be 0.95 volts. Word line drivers 58, intermediate logic 64, and sense amplifiers 66 are also provided in upper VH to optimize their operation. Level shifters 68, 70, 73 are provided to convert signals carried from components in the lower voltage domain VL to the upper voltage domain VH. In this regard, signals from control system 52 and passing through intermediate logic 60, 61 on access path 54 and sense path 56, respectively, are level shifted from the lower voltage domain VL to the upper voltage domain VH via one or more level shifters 68, 70, 73. Intermediate logic 64 is located in the upper voltage domain VH and thus does not need to be level shifted. Another level shifter 72 is provided to shift output lines 48 from the upper voltage domain VH back to the lower voltage domain VL. Providing an independent lower voltage domain VL and upper voltage domain VH allows the lower voltage domain VL to be adjusted dynamically, such as through dynamic voltage scaling (DVS) techniques, for example, either to conserve power or to enable hyper performance. The lower voltage domain VL can be reduced or dismantled during sleep modes to conserve standby power. If further performance improvements are desired, the upper voltage domain VH can be increased to provide an operating voltage level higher than VMIN.

The performance (i.e., speed) of the components is affected by their operating voltage level. Generally, a higher operating voltage level results in less delay and faster performance. Generally, a lower operating voltage level results in more delay and slower performance. Thus, the timing of access path 54 and sense path 56 is designed with voltage domains in mind so that access path 54 has the same or less delay than sense path 56. Otherwise, sense amplifiers 66 will sense data on bit lines 62 before valid data is asserted on bit lines 62 by SRAM cell array 50. Since the voltage level in a voltage domain can vary due to variations in a power supply, the delay in access path 54 and sense path 56 can change during operation as a result. By providing multiple voltage domains, voltage level variations in the lower voltage domain VL, the upper voltage domain VH, or both may contribute to delay variations in access path 54 and sense path 56. Natural tolerances between level shifters 68, 70, and/or 73 may also cause additional delay variations that contribute to the overall delay variations in access path 54 and sense path 56.

If voltage level variations occur in access path 54 and/or sense path 56 such that the delay of sense path 56 increases relative to the delay of access path 54, memory system 44 still operates properly. In this case, SRAM cell array 50 will still place data on bit lines 62 before sense amplifiers 66 detect data on bit lines 62. However, if voltage level variations occur such that the delay of sense path 56 decreases relative to the delay of access path 54, memory system 44 may be inoperable. In this case, sense amplifiers 66 may be activated to detect data on bit lines 62 before valid data is placed on bit lines 62 by SRAM cell array 50. For this reason, memory system 44 is designed to provide a delay margin for sense path 56. A delay margin is an amount of delay by which the delay of sense path 56 can be decreased relative to access path 54 and memory system 44 still function properly (i.e., valid data is present on bit lines 62 when sense amplifiers 66 detect data on bit lines 62). The delay margin comes with a tradeoff. The delay margin decreases the performance of the memory system 44 by increasing the delay of the sense path 56. Performance is decreased for all operating conditions although variations in voltage level may cause the delay of the sense path 56 to decrease at certain times or under limited conditions. Thus, it is desirable to limit the delay margin for the sense path 56 as much as possible to maximize the performance of the memory system 44 without rendering the memory system 10 inoperable.

Even with the delay margin provided for sense path 56, the voltage levels in the lower voltage domain VL or the upper voltage domain VH may still vary such that the delay of sense path 56 relative to access path 54 decreases by more than the delay margin. In such cases, memory system 44 will be inoperable. The decreased delay of sense path 54 will cause sense amplifiers 66 to detect data on bit lines 62 before valid data is asserted on bit lines 62 by SRAM cell array 50. The delay margin of sense path 56 may be increased, but performance is sacrificed as a result. It may not be possible to provide sufficient delay margin to permit proper operation of memory system 44 under all operating conditions while achieving acceptable performance. To address this problem, one or more delay circuits 74 are provided in the sense path 56, as illustrated in Figure 2. The one or more delay circuits 74 are configured to self-adjust the delay in the sense path 56. By self-adjusting, it is meant that the delay in the sense path 56 is self-adjusting. The delay in the sense path 56 is prevented from being less than the delay in the access path 54. Otherwise, the sense amplifiers 66 may sense data from the bit lines 62 before the SRAM cell array 50 asserts valid data on the bit lines 62 under certain operating circumstances. The one or more delay circuits 74 are configured to dynamically adjust the delay during operation of the memory system 44.

Figure 3 illustrates an example of a delay circuit 74A that may be coupled in-line in the sense path 56 of the memory system 44 of Figure 2. The memory system 44 of Figure 2 shows two possible locations for the delay circuits 74 in the sense path 56. The delay circuits 74 may be provided in the sense path 56 before the intermediate logic 64, after the intermediate logic 64, or before and after the intermediate logic 64. However, the delay circuits 74 may be provided anywhere in the sense path 56. As illustrated in Figure 3, the delay circuit 74A includes a delay element that is exemplified by the buffer 76. An input signal 78 configured to load an upper voltage domain sense signal VH into the sense path 56 is coupled to the input of the buffer 76. The buffer 76 adds delay to the detection signal passing through detection path 56. The operating voltage driving buffer 76 is provided by a voltage source driving the lower voltage domain VL. In this manner, delay circuit 74A is configured to generate a delay output 80 from buffer 76, and thus the delay of detection path 56, which is solely controlled by the path having the largest delay in the lower voltage domain VL. One or more level shifters 79 may be provided to shift the voltage level of the output of buffer 76 to the upper voltage domain VH. The largest delay path is often in the lower voltage domain VL. Thus, if a delay or reduction occurs due to variations in the lower voltage domain VL during operation of memory system 44, the delay output 80 of buffer 76 will be dynamically transported to the higher delay path in the lower voltage domain VL. Thus, the delay of sense path 56 will be increased by the delay or reduction caused by the lower voltage domain VL. This prevents exhaustion of the delay margin in sense path 56, where the delay in sense path 56 is less than the delay in access path 54.

The delay circuit 74A illustrated in FIG. 3 can adjust the delay of the sense path 56 in response to a delay or reduction caused by the lower voltage domain VL. However, the delay circuit 74A cannot increase the delay of the sense path 56 in response to a delay or reduction caused by the upper voltage domain VH. An effective reduction can occur in the upper voltage domain VH even if the voltage level of the upper voltage domain VH does not decrease. In some situations, the lower voltage domain VL may provide a higher voltage level than the upper voltage domain VH. Thus, the upper voltage domain VH may be slower than the lower voltage domain VL in this case depending on the design of a particular circuit.

The delay circuit 74B in Figure 4 adjusts for situations where the longer delay path is caused by either the lower voltage domain VL or the upper voltage domain VH. As illustrated in Figure 4 , a delay circuit 74B is coupled in-line to the sensing path 56 and configured to dynamically adjust or auto-adjust the delay in the sensing path 56. The delay circuit 74B is configured to generate a delay output 87 to dynamically adjust or auto-adjust the delay in the sensing path 56 due to a delay, or reduction, caused by either the lower voltage domain VL or the upper voltage domain VH. In the voltage circuit 74B of Figure 4 , first and second delay elements exemplified as first buffer 82 and second buffer 84, respectively, are coupled in parallel. The input signal 78 configured to carry a detection signal is coupled to the inputs of the first and second buffers 82, 84. The first buffer 82 is driven by a first voltage supply energizing the lower voltage domain VL exactly as provided in the delay circuit 74A of FIG. 3. One or more level shifters 83 may be provided to shift the voltage level of the output of the first and second buffers 82, 84 to the upper voltage domain VH. However, the second buffer 84 is driven by a second voltage supply energizing the upper voltage domain VH. The outputs of the first and second buffers 82, 84 are fed into a combination circuit exemplified as combination gate 86, which in one embodiment may be an AND gate. The delay output 87 of the combination gate 86 carries a sense signal provided in the input signal 78 to the sense amplifiers 66 in the sense path 56. By providing the first and second buffers 82, 84 that are driven by both voltage domains, the delay output 87 of the first and second buffers 82, 84, and thus the delay of the sense path 56, will be controlled by the greater delay path caused by either the lower voltage domain VL or the upper voltage domain VH. Thus, delay circuit 74B is capable of dynamically adjusting or self-adjusting the delay in sense path 56 regardless of whether the lower voltage domain VL caused the greater delay path relative to the upper voltage domain VH, or whether the upper voltage domain VH caused the greater delay path relative to the lower voltage domain VL. Figure 5 illustrates another example of a delay circuit 74. Herein, a delay circuit 74C is provided that is similar to the delay circuit 74B illustrated in Figure 4, except that additional buffers are provided to further increase the delay in sense path 56. A first set of delay elements exemplified as buffers 88 coupled in a series chain are provided and driven by the lower voltage domain VL to provide delay buffers. A second set of delay elements exemplified as buffers 90 coupled in a series chain and driven by the upper voltage domain VH is coupled in parallel to the first set of buffers 88. Input signal 78 configured to load a detection signal into detection path 76 is coupled to the inputs of the first set of buffers 88 and the second set of buffers 90. The outputs of the first and second sets of buffers 88, 90 are coupled to the inputs of a combination circuit exemplified by combination gate 92, which in one embodiment may be an AND gate. One or more level shifters 89 may be provided to shift the voltage level of the output of the first and second sets of buffers 88, 90 into the upper voltage domain VH. A delay output 91 of combination gate 92 carries a sense signal provided in input signal 78 to sense amplifiers 66 in sense path 56. As provided in delay circuit 74B of FIG. 4, by providing first and second sets of buffers 88, 90 that are driven by both voltage domains, the delay output 91 of first and second sets of buffers 88, 90, and thus the delay of sense path 56, will be transmitted over the path of the greater delay caused by either the lower voltage domain VL or the upper voltage domain VH. Thus, delay circuit 74C is capable of dynamically adjusting or self-adjusting the delay in sensing path 76 regardless of whether lower voltage domain VL caused the longer delay path relative to upper voltage domain VH, or whether upper voltage domain VH caused the longer delay path relative to lower voltage domain VL. Figure 6 illustrates another example of a delay circuit 74 that may be provided in sensing path 56. A delay circuit 74D generates a delay output 93 according to the slowest delay among a plurality of voltage domains. Delay circuit 74D illustrated in Figure 6 is configured to provide delay mixing between two or more voltage domains; however, this delay circuit 74D may be provided in a dual voltage domain system, such as the memory system 44 illustrated in FIG. 2. A plurality of delay elements 94, 96, 98 for providing multiple delay chains (i.e., one delay element or a plurality of delay elements provided in series), each driven by a different voltage domain, are individually driven by input signal 78. The resulting delay chains are then level shifted, via level shifters 95, 97, 99, to the upper voltage domain VH, and each provides an input to a combining circuit exemplified by combining gate 100, which in one embodiment may be an AND gate. In this manner, the voltage domains are mixed with the slower delay transmitting the output of combining gate 100. Delay output 93 of combination gate 100 controls and adjusts the delay of the sense signal according to the path having the largest delay between the voltage domains. The self-adjusting delay circuit and related methods described herein may be used in any circuit or system, including, but not limited to, a memory circuit or system. If employed in a memory circuit or system, the memory circuit or system may employ any type of memory. Examples include, without limitation, SRAM, dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, two double data rate (DDR2) SDRAM, three double data rate (DDR2) SDRAM, Mobile DDR SDRAM (MDDR), low capacity (LP) DDR SDRAM, and LP DDR2 SDRAM. Any of the components of a memory circuit or system employing the self-tuning delay circuit may be provided in any voltage domain among a plurality of voltage domains so long as the memory is driven by a voltage domain providing a voltage level sufficient to maintain the memory cell functional, if required by the memory technology and/or design. Figure 7 illustrates a processor-based system 120 that may employ the circuits and systems described above. The processor-based system 120 may be included in an electronic device 121. The processor-based system 120 includes a central processing unit (CPU) 122 that includes a processor 124 and an integrated cache system 126. The cache system 126 includes a cache management unit 127 that controls access to a cache memory 128 accessible to the processor 124 for fast access to temporary storage for frequently accessed data. The cache memory 128 may employ the circuitry and methods described above. The CPU 122 is coupled to the system bus 129, which interconnects the other devices included in the processor-based system 120. As is well known, the CPU 122 communicates with these other devices by exchanging address, control, and data information over the system bus 129. These devices may include any types of devices. As illustrated in Figure 7, these devices may include system memory 130, one or more input devices 132, one or more output devices 134, a network interface device 136, and a display controller 138, as examples. The input devices 132 may include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output devices 134 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device 136 may be any device configured to allow data exchange to and from a network 140. The network 140 may be any type of network including, but not limited to: wired or wireless network; private or public network; local area network (LAN); wide area network (WLAN); and the Internet. The network interface device 136 may support any desired type of communication protocol. The CPU 122 may also access the system memory 130 via the system bus 31. The system memory 130 may include circuitry and methods previously described above for accessing the system memory 130. The system memory 130 may include static memory 141 and/or dynamic memory 142. The system memory 130 may include a program storage medium 144 and a data storage medium 146 for the CPU 122. The CPU 122 may also access the display controller 130 via the system bus 31 to control information sent to a display 154. The display controller 138 may include a memory controller 148 and memory 150 for storing data to be sent to the display 154 in response to communications with the CPU 122. The display controller 138 sends information to the display 154 for display by means of a video processor 152. which processes information to be displayed in a format suitable for display 154. Display 154 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

A circuit in accordance with the embodiments described herein may also be provided in any electronic device for controlling a signal path, including, but not limited to, a signal path for accessing memory. Such electronic devices may employ a processor-based system similar to or including one or more components of the processor-based system 120 of Figure 7. Examples of such electronic devices include, without limitation, mobile telephones, cellular telephones, computers, portable computers, desktop computers, personal digital assistants (PDAs), monitors, computer displays, televisions, tuners, radios, satellite radios, digital music players, portable music players, digital video players, digital video disc (DVD) players, and portable digital video players. Those skilled in the art would further appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations thereof. To clearly illustrate this interchangeability of hardware and software, several illustrative components, blocks, modules, circuits, and stages have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of the present invention. The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or realized with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designs to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller or state machine. A processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

It is also noted that the operational steps described in any of the exemplary embodiments presented herein are described for the purpose of providing examples and discussion. The operations described may be performed in a number of different sequences other than the sequences illustrated. Furthermore, the operations described in a single operational step may be effectively performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary embodiments may be combined. It should be understood that the operational steps illustrated in the flow diagrams may be subject to a number of different modifications as will be readily apparent to those skilled in the art. Those skilled in the art would also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. The foregoing description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications of the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, it is not intended that the disclosure be limited to the examples and designs described herein, but should be given the broadest scope consistent with the novel principles and features disclosed herein.

Claims (10)

1. A method for producing a delay output in a memory system (44), comprising: receiving an input signal (78) from a sensing path (56) traversing a first portion (45) of a plurality of voltage domains, wherein the sensing path (56) has a first delay responsive to the first portion (45), wherein an access path (54) traversing a second portion (47) of the plurality of voltage domains has a second delay responsive to the second portion (47), wherein the plurality of voltage domains comprises a lower voltage domain (VL) and an upper voltage domain (VH), and wherein each of the sensing path (56) and the access path (54) traverses both the lower voltage domain (VL) and the upper voltage domain (VH); generating a delay output related to the first and second delays from one or more delay circuits (74) provided in the detection path (56) and receiving the input signal (78), wherein generating the delay output comprises: delaying the input signal (78) using one or more first delay elements (82, 88) whose voltages are supplied by a first voltage source among the plurality of voltage domains; delaying the input signal (78) using one or more second delay elements (84, 90) whose voltages are supplied by a second voltage source among the plurality of voltage domains; the method characterized in that it further comprises: combining the delayed input signal from the one or more first delay elements (82, 88) and the delayed input signal from the one or more second delay elements (84, 90) to generate the delay output; and receiving the delay output at a plurality of sense amplifiers (66) configured to sense data from bit lines (62) output from at least one memory cell (50) coupled to the access path (54). 2. The method of claim 1, wherein generating the delay output further comprises delaying the input received from the detection path by the second delay in the access path. 3. The method of claim 1, wherein generating the delay output further comprises generating at least one gate output from the one or more delay circuits receiving the input signal. 4. The method of claim 1, wherein receiving the input signal comprises receiving the input signal through both the lower voltage domain and the upper voltage domain. 5. A memory system (44), comprising: a control system (52); a plurality of voltage domains comprising a lower voltage domain (VL) and an upper voltage domain (VH); a sensing path (56) traversing a first portion (45) of the plurality of voltage domains and having a first delay responsive to the first portion (45); an access path (54) traversing a second portion (47) of the plurality of voltage domains having a second delay responsive to the second portion (47), wherein each of the sensing path (56) and the access path (54) traverses both the lower voltage domain (VL) and the upper voltage domain (VH); a delay circuit (74) coupled to the sensing path (56) and configured to produce a delay output related to the first and second delays, wherein the delay circuit comprises: one or more first delay elements (82, 88) whose voltages are supplied by a first voltage source among the plurality of voltage domains and are configured to generate one or more first outputs (D1); one or more second delay elements (84, 90) whose voltages are supplied by a second voltage source among the plurality of voltage domains and are configured to generate one or more second outputs (D2); the memory system characterized in that the delay circuit further comprises: at least one combination circuit (86, 92) configured to generate the delay output in response to receiving the one or more first outputs (D1) and the one or more second outputs (D2); and a plurality of sense amplifiers (66) configured to receive the delay output and sense data from bit lines output (62) from a memory cell array (50). 6. The memory system of claim 5, wherein the delay circuit is comprised of a plurality of delay elements, each configured to generate the delay output (80, 87, 91). 7. The memory system of claim 5, wherein the one or more first delay elements and one or more second delay elements are each comprised of one or more buffers. 8. The memory system of claim 5, wherein the first portion spans at least the lower voltage domain, and wherein the second portion spans at least the upper voltage domain. 9. The memory system of claim 5, further comprising at least one level shifter in one or more of the detection path or the access path. 10. The memory system of claim 5, wherein the memory system is included in an electronic device comprised from the group consisting of a mobile telephone, a cellular telephone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer display, a television, a tuner, a radio, a satellite radio, a digital music playback device, a portable music playback device, a digital video playback device, a digital video disc (DVD) playback device, and a portable digital video playback device.