BRPI0808226B1 - computer system and method for debugging system memory - Google Patents

Abstract

computer system and method for debugging system memory. a computer system (100) is provided, the computer system (100) having a processor (104) and a system memory (108) coupled to the processor (104). computer system (100) also includes a basic input / output system (bios) (130) in communication with processor (104). bios (130) selectively debug system memory (108) during a computer system shutdown process (100).

Description

COMPUTER SYSTEM AND METHOD FOR PURING A SYSTEM MEMORY.

The Trustworthy Computing Group (TCG) specified the concept of a memory debug bit (MOR). If the 5 bit MOR is set, a Basic Data Entry / Exit System (BIOS) performs a memory debugging during a boot process to ensure that the secrets stored in the system's memory are erased before being exposed.

Although the MOR bit can be used to prevent attacks (eg, reconnection or power cycling attacks) from being effective, some existing implementations lack sophistication. For example, some computer systems keep the MOR bit in an activated condition, which causes the BIOS to unnecessarily debug the memory during each boot process. Also, each debugging of memory causes a delay in the boot process, which can make a user believe that the computer system is hanging.

Brief description of the drawings

For a detailed description of exemplary configurations of the invention, reference will now be made to the attached drawings in which:

Figure 1 illustrates a system according to configurations;

Figure 2 illustrates access and use of a memory debug (MOR) bit according to configurations;

Figure 3 illustrates a method according to configurations;

Figure 4 illustrates another method according to 30 configurations; and

Figure 5 illustrates yet another method according to configurations.

Notation and nomenclature

Certain terms are used throughout the description and the following 35 claims to refer to particular components of the system. As someone skilled in the art would appreciate, computer companies may refer to a component by different names. This document is not intended to distinguish between components that differ in name but not in function. In the following discussion and in the claims, the terms including and comprising are used and should be interpreted limited to .... Also, the term an unlimited way, and therefore but not coupled is intended to mean an indirect electrical connection, meaning including, coupling or mean any of a direct, optical or wireless.

device if

Therefore, if a first device, that direct electrical connection, via other devices and attaches to a second indirect connection can be connected by an electrical connection, by an optical electrical connection, or by a wireless electrical connection.

Detailed Description

The following discussion is directed to various configurations of the invention. Although one or more of these configurations may be preferred, the disclosed configurations should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, someone skilled in the art will understand that the following description has broad application, and the discussion of any configuration is intended to be only exemplary of that configuration, and not intended to suggest that the scope of the disclosure, including the claims, is limited to that configuration .

Settings allow memory debugging to be performed selectively during a shutdown process or a boot process. The shutdown process can be part of a shutdown, a restart, or a hibernation process. Debugging memory can be based on a debugging memory bit (MOR) or another control mechanism. If the memory debugging is performed during a shutdown process, the MOR bit is cleared such that the Basic Input / Output System (BIOS) does not perform another memory debugging during the subsequent boot process. In at least some configurations, a memory debug indicator is provided such that a user is aware that a memory debug is being performed.

Figure 1 illustrates a system 100 according to configurations. System 100 comprises a computer 102 having a processor 104 coupled to system memory 108, which may be Random Access Memory (RAM). System memory 108 has at least one confidential area 110 which is used to store secrets such as passwords, encryption keys or other sensitive information. Confidential area 110 can be fixed or variable within system memory 108. In at least some configurations, a host bridge (sometimes referred to as the North bridge) 106 is placed between processor 104 and system memory 108. In alternative configurations , an explicit bridge module between processor 104 and system memory 108 is not required.

As shown, an input / output (I / O) bridge (sometimes referred to as a South bridge) 112 couples several components to the host bridge 106. In at least some configurations, a display 118 and a memory debug indicator 120 if connect to the 112 I / O bridge.

Display 118 may comprise a liquid crystal display (LCD) or another display that depends on a video card and / or video drivers. If a memory debug is performed during a boot process, the video card and / or the video drivers may not be initialized and therefore the display 118 cannot be used to notify a user that the memory debug is being performed. In contrast, if a memory debug is performed during a shutdown process, the video card and video drivers can be operational and messages can be delivered to a user via display 118. For example, messages on display 118 can indicate how much of a memory debug was performed, the time remaining before the memory debugging and / or other information is finished.

Even if display 118 is non-operative (during the boot process or the shutdown process), the memory debug indicator 120 can provide information to a user. In at least some configurations, the memory debug indicator 120 comprises a light emitting diode (LED) that indicates the duration or end of a memory debug. For example, a certain flashing pattern or solid LED activity can indicate when a memory debug is being performed and / or when a memory debug is finished. In alternative configurations, the 15 memory debug indicator 120 comprises an LCD that does not depend on a video card and / or video drivers as the display 118 does. In such a case, the memory debug indicator 120 can display text which indicates how much of a memory debug was performed, time remaining for a memory debug and / or other information even though the display 118 is non-operative. The memory debug indicator 120 can be located on the display 118, on the keyboard, or some other location visible to a user of the system 100. 25 audio alerts can additionally or alternatively be used subject to similar conditions (eg, alerts do not depend on an audio card and / or audio drivers).

In at least some configurations, the I / O bridge 112 30 also attaches to a Super I / O 114 controller, a

BIOS 130, a disk drive 140 and a Trusted Platform Module (TPM) 150. The Super I / O controller 114 provides an interface for a keyboard / mouse 116. In at least some configurations, the Super 35 I / O controller The 114 and / or I / O bridge 112 are capable of detecting a request to shut down computer system 100 (including requests for shutdown, hibernation or restart). The request can be received, for example, from the keyboard 116. In response, the Super I / O controller 114 and / or the I / O bridge 112 are able to capture the shutdown request and notify BIOS 130. BIOS 130 is then able to debug system memory 108 before the shutdown request is complete.

Disk drive 140 comprises an operating system (OS) 142 and applications 144, which are executable by processor 104. During the operating time of computer system 100 (or earlier), certain instructions or data related to OS 142 and / or applications 144 can be stored in system memory 108. These instructions or data can be stored in confidential area 110 or somewhere else in system memory 108. Secrets can also be stored in confidential area 110 as mentioned earlier.

As shown, disk driver 140 can also comprise a protected area 146, which corresponds to part or all of disk driver 140. Protected area 146 is accessible through an authentication process that involves, for example, a password, pass phrase, an encryption key, a biometric reading or another secret. Although not required, some configurations rely on the TPM 150 to assist with the authentication process.

The TPM 150 is configured to provide cryptographic functions (eg, an asymmetric RSA algorithm for digital signature and for encryption), SHA1 combination, a Combination-based Message Authentication Code (HMAC) function, secure storage, generation of random number, or other functions. The TPM 150 is implemented using software, firmware [resident boot program] and / or hardware. TPM architectures and functions may possibly change over time as authorized by the TCG. Using TPM 150, a secret can be authenticated to allow a user to access protected area 146.

In at least some configurations, OS 142 comprises a secure OS that supports using the MOR bit as specified by the Trustworthy Computing Group (TCG). As an example, if a user requests access to protected area 146, OS 142 can activate the MOR bit and store a secret associated with the user's request in confidential area 110. After the user has finished accessing protected area 146, OS 142 can override the MOR bit and purge confidential area 110 to eliminate the secret. The particular timing with respect to when the MOR bit is activated and cleared may vary (eg, the MOR bit can be activated before or after the secret is stored in confidential area 110 and can be cleared before or after the secret has been deleted). If OS security is enabled, the MOR bit can remain active regardless of whether a secret has been stored in or overridden from confidential area 110. With the MOR bit active, all memory 108 (not only confidential area 110) would be cleared during a subsequent boot process.

BIOS 130 is stored on a medium read by the computer (eg, a flash [instant] ROM) and comprises several instructions executable by processor 104. In at least some configurations, BIOS 130 allows memory debugging to be selectively performed shutdown or a BIOS 130 process can MOR bit interface 132, instructions during a boot. As shown, the understanding of a memory 134, instructions for

Some have a 138 user interface.

BIOS components are part of

BIOS. These components accessed using a Debug Mode indicator 136 and or all of these from a block

BIOS too

Boot management can be System (SMM).

The MOR 132 bit interface allows BIOS 130 to access and update the MOR bit, which can be stored in a secure location in BIOS 130 memory or elsewhere. For example, during the boot process, BIOS 130 can check the status of a MOR flag. If the MOR bit is set for debugging, BIOS 130 performs a memory debug based on the memory debug instructions 134 as will be described later. If the MOR bit value is not set for debugging, BIOS 130 continues the boot process. Before or after memory debugging is performed, the MOR 132 bit interface can set the bit

MOR be canceled. The debug value of the MOR bit can be high or low in different configurations. As an example, if the debug value of the MOR bit is high, clearing the MOR bit corresponds to setting the MOR bit to a low value (eg, a logical 0). If the clearance value of the MOR bit is low, clearing the MOR bit corresponds to setting the MOR to a high value (eg, a logical 1).

In at least some configurations, BIOS 130 uses the MOR 132 bit interface to check the status of the MOR bit during a shutdown process. For example, the bridge

I / O 112 and / or the Super I / O 114 controller can detect and capture a request to shut down the system of computer 100. The request can be

identified by detecting when OS 142 attempts to write one or more records (eg, a sleep record or a restart record). In response, I / O bridge 112 and / or super I / O controller 114 switches computer system 100 to System Management Mode (SMM), which operates without involvement of OS 142.

During SMM, BIOS 130 is able to selectively override the MOR bit. For example, if the MOR bit has been set by OS 142 during run time, BIOS 130 can override the MOR bit even if OS security is enabled. Before or after BIOS 130 overrides the MOR bit, BIOS 130 can also debug system memory 108 using memory debug instructions 134. In at least some configurations, memory debug instructions 134 allow BIOS 130 to override all the contents of system memory 108. As an example, if system memory 108 has a capacity of 16 GB and the memory debug operation aborts memory at a rate of 1-2 GB / a, then the memory debug would last between 8-16 seconds. By clearing the MOR bit and performing memory debugging during shutdown, BIOS 130 10 does not have to perform memory debugging during the subsequent boot.

There are advantages to performing memory debugging during the shutdown process instead of the boot process. For example, a user logging out of computer system 100 usually does not care if the shutdown process takes time to debug memory. In contrast, a user who arrives and boots computer system 100 usually wants to reach the operating time as quickly as possible 20 and does not appreciate that the boot time is extended to perform memory debugging. In addition, audio / video cards and / or drivers may be available during the shutdown process, but not during the boot process. Thus, if the memory debug is performed during the shutdown process, a user can receive information regarding the status of the memory debug via the display 118.

Even if audio / video cards and / or drivers are not available at the time the memory debugging is performed, the

BIOS 130 implements control instructions 136 that allow BIOS 130 to control memory debugging 120.

the debug indicator does not

As discussed earlier, it can comprise an LED or LCD that video card and / or video drivers. Depending on the memory, the indicator control instructions 136 make the memory debug indicator 120 provide information for a

120 *

user in the form of LED light patterns or LCD text that indicate how much of a memory debug has been performed, time remaining for a memory debug and / or other information.

The user interface 138 of BIOS 130 allows a user to select various options related to memory debugging performed by BIOS 130. In at least some configurations, the user can access user interface 138 via an F10 setting option that presents a menu to the user. As an example, the menu may allow a user to select options such as when memory debugging is performed (eg, immediately during boot and / or during shutdown), activation / deactivation of the MOR 132 bit (eg, some OSs may not support MOR bit operations), MOR bit debugging (eg, BIOS 130 can perform memory debugging without depending on the MOR bit or can perform memory debugging even if the MOR bit is cleared), enable / disable memory debug indicator 120 or other options.

In summary, computer system 100 is capable of responding to restart attacks or power cycling attacks by performing a memory debug in advance in the subsequent boot process. Additionally, computer system 100 reinforces the usability of memory and MOR bit debugging by providing several options. For example, memory debugging can be performed during a shutdown process and the MOR bit can be selectively overridden by BIOS 130 to prevent a memory debugging from being performed during a subsequent boot process. As needed, BIOS 130 can control memory debug indicator 120 to improve user awareness of debug operations.

Figure 2 shows the access and use of a memory debugging bit (MOR) 206 according to configurations. As shown, an OS 202 and BIOS 204 selectively set and override the MOR 206 bit. The debug value of the MOR bit can be high or low in different configurations. As an example, if the debug value of the MOR bit is high, 5 setting the MOR bit corresponds to a high MOR bit value (eg, a logical 1) and canceling the MOR bit corresponds to a MOR bit value low (eg, a logical 0). Alternatively, if the debug value of the MOR bit is low, setting the MOR bit corresponds to a low MOR 10 bit value (eg, a logical 0) and canceling the MOR bit corresponds to a high MOR bit value ( eg a logical 1).

In at least some configurations, OS 202 sets the MOR bit if an A event occurs. For example, event A 15 may correspond to a secret being stored in confidential area 110 of memory 108 or in OS security being activated. In at least some configurations, OS 202 clears the MOR bit if an event B occurs. For example, event B may correspond to a secret being deleted from confidential area 110 of memory 108 or the security of the OS being disabled. In some configurations, the OS selectively performs a memory debugging of confidential area 110 of memory 108 to eliminate secrets, but does not clear all system memory 108.

In at least some configurations, BIOS 204 will override the MOR bit if a C event occurs. For example, event C may correspond to a secret being cleared from confidential area 110 of system memory 108 while OS security is enabled. In other words, with OS security enabled, some OS settings

202 do not clear the MOR bit even if confidential area 110 has been cleared. In such a case, BIOS 204 may selectively override the MOR bit. For example, BIOS 204 may override the MOR bit during a shutdown process such that a memory debug is not performed during a subsequent boot process. As shown, an SMM mode can be used selectively to allow BIOS 204 t

cancel the MOR bit. Alternatively, event C may correspond to BIOS 204 performing a memory debugging during a boot process. In such a case, BIOS 204 clears the MOR bit before or after the 5 memory debugging is complete.

In at least some configurations, BIOS 204 turns the MOR bit on if a D event occurs. For example, wind D may correspond to a user selecting a BIOS option to perform a memory debug and 10 depending on the MOR bit. The memory debugging can be performed when the user selects the option, during a boot process or during a shutdown process. If a user selects to perform a memory debug immediately, BIOS 204 performs debug and memory and the computer is rebooted.

In some configurations, BIOS 204 depends on the MOR bit being set as a prerequisite to perform memory debugging. Alternatively, BIOS 204 can perform memory debugging regardless of the MOR bit or 20 of the MOR bit value. For example, BIOS 204 can selectively perform a memory debug of all system memory 108 during shutdown without checking the MOR bit value, or it can perform memory debug even if the MOR bit is cleared. Even if a memory debugging of all system memory 108 occurs during shutdown, BIOS 204 can still perform another memory debugging during a subsequent boot if the MOR bit is active.

Figure 3 illustrates a method 300 according to 30 configurations. As shown, method 300 starts at block 302. At block 304, method 300 expects to receive a shutdown request. If a shutdown request is received (determination block 304), the shutdown request is captured (block 306) and the 35 bit MOR is canceled (block 308). For example, a BIOS operating on SMM can override the MOR bit. In at least some configurations, the MOR bit can be set (eg, because OS security is enabled) even if no secrets are stored in the memory to be cleared. If a memory debugging has been requested (determination block 310), the memory debugging is performed (block 312). For example, a BIOS operating on SMM can perform memory debugging. If a memory clearance has not been requested (determination block 310) or if memory clearance in block 312 has already been performed, method 300 completes the shutdown process (block 314). The shutdown process can be part of a hibernation process or a restart process.

Figure 4 illustrates another method 400 according to configurations. As shown, method 400 starts at block 402. At block 404, method 400 waits until a memory debug is requested. If a memory debug is requested (determination block 404), method 400 determines whether a memory debug indicator is provided in block 406. If a memory debug indicator is provided (determination block 406), the duration of the memory debug is indicated by the memory debug indicator (block 408). For example, the memory debug indicator can be an LED or LCD that does not depend on a 25 video card and / or a video driver. If a memory debug indicator is not provided (determination block 406) or the duration of the memory debug has been indicated (block 408), method 400 performs memory debugging (block 410). In alternative configurations, the memory debugging indicator 30 may begin to display information after the memory debugging has started. Method 400 can be executed, for example, during a boot process or during a shutdown process.

Figure 5 illustrates yet another method 500 according to 35 configurations. As shown, method 500 starts at block 502. If a safe operation is to be performed (determination block 504), a MOR bit is set (block

506). As an example, secure operation comprises accessing a protected area from a disk trigger based on an authentication process. If the safe operation is finished (determination block 508), the 5 bit MOR is selectively canceled (block 512). For example, if OS security is disabled, a secret related to safe operation can be eliminated once the safe operation is finished and the MOR bit can be cleared. If OS security is enabled, the 10 bit MOR remains set regardless of whether a secret related to secure operation has been overridden. Since the MOR bit is selectively overridden, method 500 determines whether a BIOS is capable of performing a memory debug during shutdown in block 514.

Returning to block 508, if the safe operation has not ended (determination block 508) and an abnormal shutdown occurs (determination block 510), method 500 performs a memory debugging during a subsequent boot process if the MOR bit is defined (block 20 516). If the safe operation has not ended (determination block 508) and an abnormal shutdown does not occur (determination block 510), method 500 branches to block 514. Method 500 also branches to block 514 if a safe operation does not have to be carried out (determination block 504). If a BIOS is prepared to perform a memory debugging during connection (determination block 514), a memory debugging is performed during the shutdown regardless of the MOR bit value and the MOR bit is cleared 30 (block 518). If the BIOS is not able to perform a memory debug during shutdown (determination block 514), method 500 performs a memory debug during a subsequent boot process if the MOR bit is active (block 516).

The above discussion is intended to be illustrative of the principles and the various configurations of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, in some configurations, memory debugging performed by BIOS 130 does not need to erase all system memory 108. The following claims are intended to be interpreted to cover all such variations and modifications.

Claims (6)

1. Computer system (100), characterized by the fact that it comprises: a processor (104); system memory (108) coupled to the processor (104); and a Basic Input / Output System (BIOS) (130) in communication with the processor (104); an input / output (I / O) bridge (112) coupled to the processor (104); and an operating system (OS) (142) in communication with the processor (104), the I / O bridge (112) being arranged to capture a shutdown request and cause the system (100) to enter a System Management Mode (SMM) based on a selection, the BIOS (130) being operative to debug system memory (108) in that System Management Mode during the shutdown process and debug system memory (108 ) before the shutdown request is complete, the selection comprising the OS (142) setting a memory debug (MOR) bit that causes the BIOS (130) to debug the system memory (108) during a boot process of the computer system (100), the OS (142) canceling the MOR bit (206) if at least one of the following occurs: a secret is cleared from a confidential area of memory (108), and OS security is disabled. 2. Computer system (100) according to claim 1, characterized by the fact that the BIOS (130) is arranged to cancel the MOR bit (206) during the shutdown process. 3. Computer system (100) according to claim 1, characterized in that it additionally comprises a memory debugging indicator (120) in communication with the BIOS (130), the memory debugging indicator (120) is independent of a video card from the computer system and is arranged to display Petition 870180158017, of 12/03/2018, p. 10/11 information regarding a memory debug. 4. Method for debugging a system memory, characterized by the fact that it comprises: receiving a shutdown request for a computer system (100); capture the shutdown request; perform a memory debug in an operation in BIOS System Management Mode (130) before the shutdown request is allowed to proceed; by an OS (142) of the computer system (100), set a memory debug (MOR) bit (206) that makes the BIOS (130) debug the system memory (108) during a system boot process computer (100); by OS (142), clear the MOR bit (206) if at least one of the following occurs: a secret is deleted from a confidential area of memory (108), and OS security is disabled. 5. Method, according to claim 4, characterized in that it additionally comprises clearing the memory debugging bit (MOR) (206) before the shutdown request is allowed to proceed. 6. Method, according to claim 4, characterized in that it additionally comprises allowing a user to select at least one of multiple options with respect to when memory debugging is performed, options comprising performing a memory debugging during a boot process and perform a memory debugging during a shutdown process.