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BR9911733A - System to generate an accurate low-noise periodic signal - Google Patents

System to generate an accurate low-noise periodic signal

Info

Publication number
BR9911733A
BR9911733A BR9911733-9A BR9911733A BR9911733A BR 9911733 A BR9911733 A BR 9911733A BR 9911733 A BR9911733 A BR 9911733A BR 9911733 A BR9911733 A BR 9911733A
Authority
BR
Brazil
Prior art keywords
signal
noise
generate
accurate
digital
Prior art date
Application number
BR9911733-9A
Other languages
Portuguese (pt)
Inventor
Daniel Keyes Butterfield
Robert P Gilmore
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR9911733A publication Critical patent/BR9911733A/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/1806—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the frequency divider comprising a phase accumulator generating the frequency divided signal

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

Patente de Invenção: SISTEMA PARA GERAR UM SINAL PERIóDICO ACURADO DE BAIXO RUìDO. Na modalidade ilustrativa, o sistema da invenção inclui um conversor digital-para-analógico (68) de poucos bits para converter um primeiro sinal em uma freq³ência de referência para um sinal digital. Um conversor delta-sigma é incluído para a supressão de ruídos no sinal digital dentro da faixa predeterminada da freq³ência de referência e prover um sinal em forma de ruído em resposta ao mesmo. Um filtro passa-banda (72) filtra o ruído fora de banda e provê um sinal periódico acurado que não apresenta ruído de pequeno defeito. Em uma modalidade específica, o sistema da invenção inclui também um sintetizador digital direto (42) para prover o primeiro sinal na primeira freq³ência e o sinal periódico acurado de referência é suprido na forma de um sinal de referência para um loop de fase travada ou "phase locked loop" (50).Invention Patent: SYSTEM TO GENERATE AN ACCURATE LOW NOISE PERIODIC SIGN. In the illustrative embodiment, the system of the invention includes a few-bit digital-to-analog converter (68) for converting a first signal into a reference frequency for a digital signal. A delta-sigma converter is included to suppress noise in the digital signal within the predetermined range of the reference frequency and to provide a signal in the form of noise in response to it. A bandpass filter (72) filters out-of-band noise and provides an accurate periodic signal that does not show minor defect noise. In a specific embodiment, the system of the invention also includes a direct digital synthesizer (42) to provide the first signal at the first frequency and the accurate periodic reference signal is supplied in the form of a reference signal for a locked phase loop or " phase locked loop "(50).

BR9911733-9A 1998-06-30 1999-06-29 System to generate an accurate low-noise periodic signal BR9911733A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10786898A 1998-06-30 1998-06-30
PCT/US1999/014655 WO2000001072A1 (en) 1998-06-30 1999-06-29 System for generating an accurate low-noise periodic signal

Publications (1)

Publication Number Publication Date
BR9911733A true BR9911733A (en) 2001-04-03

Family

ID=22318894

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9911733-9A BR9911733A (en) 1998-06-30 1999-06-29 System to generate an accurate low-noise periodic signal

Country Status (7)

Country Link
EP (1) EP1095458A1 (en)
JP (1) JP2002519924A (en)
CN (1) CN1308789A (en)
AU (1) AU4726099A (en)
BR (1) BR9911733A (en)
CA (1) CA2336383A1 (en)
WO (1) WO2000001072A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10019487A1 (en) 2000-04-19 2001-11-08 Siemens Ag Frequency synthesizer
US7130327B2 (en) 2003-06-27 2006-10-31 Northrop Grumman Corporation Digital frequency synthesis
US7482885B2 (en) * 2005-12-29 2009-01-27 Orca Systems, Inc. Method of frequency synthesis for fast switching
US7782017B2 (en) * 2006-02-28 2010-08-24 Linear Technology Corporation Apparatus and method for producing signal conveying circuit status information
JP2010219756A (en) * 2009-03-16 2010-09-30 Canon Inc Signal processor
JP2015128220A (en) 2013-12-27 2015-07-09 セイコーエプソン株式会社 Oscillation circuit, oscillator, electronic device, moving object, and frequency adjustment method for oscillator
US9397675B1 (en) * 2015-07-31 2016-07-19 Shure Acquisition Holdings, Inc. Hybrid frequency synthesizer and method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965533A (en) * 1989-08-31 1990-10-23 Qualcomm, Inc. Direct digital synthesizer driven phase lock loop frequency synthesizer

Also Published As

Publication number Publication date
AU4726099A (en) 2000-01-17
WO2000001072A1 (en) 2000-01-06
CN1308789A (en) 2001-08-15
CA2336383A1 (en) 2000-01-06
EP1095458A1 (en) 2001-05-02
JP2002519924A (en) 2002-07-02

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Legal Events

Date Code Title Description
FA10 Dismissal: dismissal - article 33 of industrial property law
B11Y Definitive dismissal acc. article 33 of ipl - extension of time limit for request of examination expired