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BR9907844A - Dispositivo e método de entrelaçamento e desentrelaçamento para sistema de comunicação - Google Patents

Dispositivo e método de entrelaçamento e desentrelaçamento para sistema de comunicação

Info

Publication number
BR9907844A
BR9907844A BR9907844A BR9907844A BR9907844A BR 9907844 A BR9907844 A BR 9907844A BR 9907844 A BR9907844 A BR 9907844A BR 9907844 A BR9907844 A BR 9907844A BR 9907844 A BR9907844 A BR 9907844A
Authority
BR
Brazil
Prior art keywords
input data
interlacing
communication system
size
deinterlacing
Prior art date
Application number
BR9907844A
Other languages
English (en)
Other versions
BR9907844B1 (pt
Inventor
Min-Goo Kim
Beong-Jo Kim
Young-Hwan Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of BR9907844A publication Critical patent/BR9907844A/pt
Publication of BR9907844B1 publication Critical patent/BR9907844B1/pt

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation
    • H03M13/2764—Circuits therefore
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2771—Internal interleaver for turbo codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2782—Interleaver implementations, which reduce the amount of required interleaving memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

<B>DISPOSITIVO E MéTODO DE ENTRELAçAMENTO E DESENTRELAçAMENTO PARA SISTEMA DE COMUNICAçãO<D> Um método para entrelaçar dados de entrada tendo um tamanho diferente de um múltiplo de 2^ m^ (m>1) é revelado. O método compreende o armazenamento seq³êncial de dados de entrada em uma memória; acrescentar um valor de deslocamento ao tamanho dos dados de entrada para fornecer um endereço virtual com tamanho 2^ m^ em que (m>1), e gerar endereços aleatórios nas áreas de geração de endereço e ler os dados de entrada da memória utilizando os endereços aleatórios gerados das áreas de geração de endereço.
BR9907844A 1998-12-21 1999-12-21 dispositivo e mÉtodo de entrelaÇamento e desentrelaÇamento para sistema de comunicaÇço. BR9907844B1 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019980057959A KR100346170B1 (ko) 1998-12-21 1998-12-21 통신시스템의인터리빙/디인터리빙장치및방법
PCT/KR1999/000795 WO2000038333A1 (en) 1998-12-21 1999-12-21 Interleaving/deinterleaving device and method for communication system

Publications (2)

Publication Number Publication Date
BR9907844A true BR9907844A (pt) 2000-10-24
BR9907844B1 BR9907844B1 (pt) 2013-03-05

Family

ID=19565176

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9907844A BR9907844B1 (pt) 1998-12-21 1999-12-21 dispositivo e mÉtodo de entrelaÇamento e desentrelaÇamento para sistema de comunicaÇço.

Country Status (10)

Country Link
US (1) US6668343B1 (pt)
EP (1) EP1060564B1 (pt)
JP (1) JP3961770B2 (pt)
KR (1) KR100346170B1 (pt)
CN (2) CN1121095C (pt)
AU (1) AU738762B2 (pt)
BR (1) BR9907844B1 (pt)
CA (1) CA2319726C (pt)
RU (1) RU2217864C2 (pt)
WO (1) WO2000038333A1 (pt)

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US7543197B2 (en) 2004-12-22 2009-06-02 Qualcomm Incorporated Pruned bit-reversal interleaver
US7437650B2 (en) * 2005-04-12 2008-10-14 Agere Systems Inc. Pre-emptive interleaver address generator for turbo decoders
US8082479B2 (en) * 2006-02-02 2011-12-20 Qualcomm Incorporated Methods and apparatus for generating permutations
US7925956B2 (en) * 2006-10-03 2011-04-12 Motorola Mobility, Inc. Method and apparatus for encoding and decoding data
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US7949926B2 (en) * 2006-11-30 2011-05-24 Motorola Mobility, Inc. Method and apparatus for encoding and decoding data
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US8200733B1 (en) 2008-04-15 2012-06-12 Freescale Semiconductor, Inc. Device having interleaving capabilities and a method for applying an interleaving function
KR101585936B1 (ko) * 2011-11-22 2016-01-18 한국전자통신연구원 가상 사설 망 관리 시스템 및 그 방법
US10203881B2 (en) * 2011-12-19 2019-02-12 Apple Inc. Optimized execution of interleaved write operations in solid state drives
US11799564B2 (en) * 2019-02-15 2023-10-24 Apple Inc. Method for initialization seed generation for PN sequences in remote interference management

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Also Published As

Publication number Publication date
BR9907844B1 (pt) 2013-03-05
KR20000041934A (ko) 2000-07-15
WO2000038333A1 (en) 2000-06-29
KR100346170B1 (ko) 2002-11-30
JP2002533976A (ja) 2002-10-08
EP1060564B1 (en) 2017-10-18
EP1060564A4 (en) 2006-06-28
EP1060564A1 (en) 2000-12-20
CN1496023A (zh) 2004-05-12
RU2217864C2 (ru) 2003-11-27
CA2319726C (en) 2005-05-10
AU738762B2 (en) 2001-09-27
CN1121095C (zh) 2003-09-10
US6668343B1 (en) 2003-12-23
CN1291379A (zh) 2001-04-11
CN100345390C (zh) 2007-10-24
CA2319726A1 (en) 2000-06-29
JP3961770B2 (ja) 2007-08-22
AU1695600A (en) 2000-07-12

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Legal Events

Date Code Title Description
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 05/03/2013, OBSERVADAS AS CONDICOES LEGAIS.

B21F Lapse acc. art. 78, item iv - on non-payment of the annual fees in time

Free format text: REFERENTE A 22A ANUIDADE.

B24J Lapse because of non-payment of annual fees (definitively: art 78 iv lpi, resolution 113/2013 art. 12)

Free format text: EM VIRTUDE DA EXTINCAO PUBLICADA NA RPI 2649 DE 13-10-2021 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDA A EXTINCAO DA PATENTE E SEUS CERTIFICADOS, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.