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BR9808716A - Aparelho, sistema e processo para transportar dados de emulação de circuito - Google Patents

Aparelho, sistema e processo para transportar dados de emulação de circuito

Info

Publication number
BR9808716A
BR9808716A BR9808716-9A BR9808716A BR9808716A BR 9808716 A BR9808716 A BR 9808716A BR 9808716 A BR9808716 A BR 9808716A BR 9808716 A BR9808716 A BR 9808716A
Authority
BR
Brazil
Prior art keywords
circuit emulation
emulation data
clock
atm
connection
Prior art date
Application number
BR9808716-9A
Other languages
English (en)
Inventor
Lars Westberg
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR9808716A publication Critical patent/BR9808716A/pt

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
    • H04L2012/5656—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL] using the AAL2
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

"APARELHO, SISTEMA E PROCESSO PARA TRANSPORTAR DADOS DE EMULAçãO DE CIRCUITO Transporte de dados de emulação de circuito de baixa taxa de tranferência de bit atavés de uma conexão de modo de transferência assíncrono (ATM) é aperfeiçoado compactando os dados de emulação de circuito em pacotes curtos de acordo com um relógio de compactação. O relógio de compactação é derivado em função do relógio de modelar célula ATM. Os pacotes curtos são então multiplexados conjuntamente em uma única conexão ATM e transportados para uma unidade de recepção de acordo com o relógio de modelagem de célula ATM. Os dados de emulação de circuito são então extraídos da unidade receptora e encaminhados para a conexão de emulação de circuito correspondente à taxa de serviço apropriada, que é recuperada baseada sobre as características de conexão ATM.
BR9808716-9A 1997-05-06 1998-04-24 Aparelho, sistema e processo para transportar dados de emulação de circuito BR9808716A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/851,714 US6195353B1 (en) 1997-05-06 1997-05-06 Short packet circuit emulation
PCT/SE1998/000750 WO1998051114A1 (en) 1997-05-06 1998-04-24 Short packet circuit emulation

Publications (1)

Publication Number Publication Date
BR9808716A true BR9808716A (pt) 2000-07-11

Family

ID=25311475

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9808716-9A BR9808716A (pt) 1997-05-06 1998-04-24 Aparelho, sistema e processo para transportar dados de emulação de circuito

Country Status (10)

Country Link
US (1) US6195353B1 (pt)
EP (1) EP0980637A1 (pt)
JP (1) JP3988894B2 (pt)
KR (1) KR20010012306A (pt)
CN (1) CN1132491C (pt)
AU (1) AU740680B2 (pt)
BR (1) BR9808716A (pt)
CA (1) CA2288873A1 (pt)
RU (1) RU2211548C2 (pt)
WO (1) WO1998051114A1 (pt)

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KR100332960B1 (ko) * 2000-05-02 2002-04-20 고동범 비동기 전송 모드망에서 회로망 정보와 비동기 전송모드망 정보 간의 맵핑을 위한 연동 장치 및 연동 방법
US7657887B2 (en) * 2000-05-17 2010-02-02 Interwoven, Inc. System for transactionally deploying content across multiple machines
US6731649B1 (en) * 2000-07-26 2004-05-04 Rad Data Communication Ltd. TDM over IP (IP circuit emulation service)
US6847623B1 (en) 2000-11-15 2005-01-25 Qualcomm Incorporated Method and apparatus for allocating data streams onto a single channel
FR2818066B1 (fr) 2000-12-12 2003-10-10 Eads Airbus Sa Procede et dispositif de transmission deterministe de donnees asynchrones mises en paquet
US20050160088A1 (en) * 2001-05-17 2005-07-21 Todd Scallan System and method for metadata-based distribution of content
GB0205350D0 (en) * 2002-03-07 2002-04-24 Zarlink Semiconductor Inc Clock synchronisation over a packet network using SRTS without a common network clock
US7181544B2 (en) * 2002-09-03 2007-02-20 Intel Corporation Network protocol engine
US20040044796A1 (en) * 2002-09-03 2004-03-04 Vangal Sriram R. Tracking out-of-order packets
US7016354B2 (en) * 2002-09-03 2006-03-21 Intel Corporation Packet-based clock signal
US7324540B2 (en) 2002-12-31 2008-01-29 Intel Corporation Network protocol off-load engines
US7805629B2 (en) * 2005-03-04 2010-09-28 Netapp, Inc. Protecting data transactions on an integrated circuit bus
US7899680B2 (en) * 2005-03-04 2011-03-01 Netapp, Inc. Storage of administrative data on a remote management device
US8090810B1 (en) 2005-03-04 2012-01-03 Netapp, Inc. Configuring a remote management module in a processing system
US8291063B2 (en) * 2005-03-04 2012-10-16 Netapp, Inc. Method and apparatus for communicating between an agent and a remote management module in a processing system
EP1814278B1 (de) * 2006-01-27 2009-04-08 Siemens Aktiengesellschaft Verfahren zur Zuordnung von zumindest einer Nutzdatenverbindung zu zumindest einer Multiplexverbindung
US7924885B2 (en) * 2006-11-20 2011-04-12 Siverge Networks Ltd Methods and apparatuses for circuit emulation multi-channel clock recovery
EP2132911A4 (en) * 2007-01-10 2011-03-23 Smart Technologies Ulc PARTICIPANT ANSWER SYSTEM WITH ENHANCED COMMUNICATION BANDWIDTH
KR101646610B1 (ko) 2015-05-28 2016-08-09 (주)바이오니아 생체 물질 정제용 고활성 실리카 자성나노입자 및 이의 제조 방법
CN107592110B (zh) * 2017-10-27 2023-10-20 长鑫存储技术有限公司 延迟锁相环时钟线路及半导体存储器

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Also Published As

Publication number Publication date
US6195353B1 (en) 2001-02-27
AU740680B2 (en) 2001-11-08
CN1262022A (zh) 2000-08-02
JP2001523424A (ja) 2001-11-20
KR20010012306A (ko) 2001-02-15
CN1132491C (zh) 2003-12-24
RU2211548C2 (ru) 2003-08-27
WO1998051114A1 (en) 1998-11-12
CA2288873A1 (en) 1998-11-12
JP3988894B2 (ja) 2007-10-10
EP0980637A1 (en) 2000-02-23
AU7458698A (en) 1998-11-27

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 12A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2077 DE 26/10/2010.