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BR9808782A - Controlador de memória passìvel de ajuste na escala - Google Patents

Controlador de memória passìvel de ajuste na escala

Info

Publication number
BR9808782A
BR9808782A BR9808782-7A BR9808782A BR9808782A BR 9808782 A BR9808782 A BR 9808782A BR 9808782 A BR9808782 A BR 9808782A BR 9808782 A BR9808782 A BR 9808782A
Authority
BR
Brazil
Prior art keywords
asic
memory controller
controller
scale
memory
Prior art date
Application number
BR9808782-7A
Other languages
English (en)
Inventor
Anthony P Gold
Michael K Benton
Philip C Bolyn
Eric D Aho
Mark D Luba
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Publication of BR9808782A publication Critical patent/BR9808782A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)

Abstract

''CONTROLADOR DE MEMóRIA PASSìVEL DE AJUSTE NA ESCALA" Trata-se de um controlador de memória de ASIC único tem plena interligação entre diversos modos no ASIC: controlador de entrada, controlador de memória e controlador de saída. O ASIC único inclui uma seção de controlador de entrada, uma seção de controlador de memória e uma seção de controlador de saída. A arquitetura de ASIC é projetada de modo a permitir que qualquer uma das seções sejam contornadas. Com o emprego do mecanismo de contornamento, o ASIC pode ser combinado com outros ASICs semelhantes para melhorar o desempenho e aumentar as capacidades do sistema sem necessidade de redesenho de ASIC. O desenho de ASIC pode ser empregado em subsistemas de memória que são passíveis de ajuste na escala, dependendo das necessidades do usuário.
BR9808782-7A 1997-05-16 1998-05-15 Controlador de memória passìvel de ajuste na escala BR9808782A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/857,494 US6006296A (en) 1997-05-16 1997-05-16 Scalable memory controller
PCT/US1998/010068 WO1998052126A1 (en) 1997-05-16 1998-05-15 Scalable memory controller

Publications (1)

Publication Number Publication Date
BR9808782A true BR9808782A (pt) 2000-08-01

Family

ID=25326114

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9808782-7A BR9808782A (pt) 1997-05-16 1998-05-15 Controlador de memória passìvel de ajuste na escala

Country Status (5)

Country Link
US (1) US6006296A (pt)
EP (1) EP1010088B1 (pt)
BR (1) BR9808782A (pt)
DE (1) DE69828890T2 (pt)
WO (1) WO1998052126A1 (pt)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1094386A4 (en) * 1998-05-18 2007-05-23 Hitachi Ltd DISK ARRAY CONTROL DEVICE
US6137994A (en) * 1998-05-29 2000-10-24 Motorola, Inc. Radio communication system and method for setting an output power of a base site therein
US6553446B1 (en) * 1999-09-29 2003-04-22 Silicon Graphics Inc. Modular input/output controller capable of routing packets over busses operating at different speeds
EP1226503A2 (de) * 1999-11-02 2002-07-31 Siemens Aktiengesellschaft Bus-system zur simultanen bearbeitung verschiedener speicherzugriffe bei system-on-chip-lösungen
JP2001256003A (ja) 2000-03-10 2001-09-21 Hitachi Ltd ディスクアレイ制御装置、そのディスクアレイ制御ユニットおよびその増設方法
US6745308B2 (en) * 2002-02-19 2004-06-01 Ati Technologies, Inc. Method and system for bypassing memory controller components
US7231478B2 (en) * 2002-05-24 2007-06-12 Koninklijke Philips Electronics N.V. Programmed access latency in mock multiport memory
US7308540B2 (en) * 2002-05-24 2007-12-11 Koninklijke Philips Electronics N.V. Pseudo multiport data memory has stall facility
JP2005196331A (ja) 2004-01-05 2005-07-21 Hitachi Ltd ディスクアレイ装置及びディスクアレイ装置の構成変更方法
US8356127B2 (en) * 2004-12-09 2013-01-15 Rambus Inc. Memory interface with workload adaptive encode/decode
US7281093B1 (en) 2004-12-21 2007-10-09 Xilinx, Inc. Memory apparatus for a message processing system and method of providing same
US8122421B2 (en) * 2008-08-14 2012-02-21 Omnivision Technologies, Inc. System, and method, and computer readable medium for designing a scalable clustered storage integrated circuit for multi-media processing
US20140068220A1 (en) * 2012-09-06 2014-03-06 Advanced Micro Devices, Inc. Hardware based memory allocation system with directly connected memory

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4682284A (en) * 1984-12-06 1987-07-21 American Telephone & Telegraph Co., At&T Bell Lab. Queue administration method and apparatus
US4991084A (en) * 1988-02-05 1991-02-05 International Business Machines Corporation N×M round robin order arbitrating switching matrix system
US5255239A (en) * 1991-08-13 1993-10-19 Cypress Semiconductor Corporation Bidirectional first-in-first-out memory device with transparent and user-testable capabilities
DE69327504T2 (de) * 1992-10-19 2000-08-10 Koninklijke Philips Electronics N.V., Eindhoven Datenprozessor mit Operationseinheiten, die gemeinsam Gruppen von Registerspeichern benutzen
JP3010947B2 (ja) * 1992-11-26 2000-02-21 日本電気株式会社 メモリアクセス制御装置
WO1996007139A1 (en) * 1994-09-01 1996-03-07 Mcalpine Gary L A multi-port memory system including read and write buffer interfaces
US5841775A (en) * 1996-07-16 1998-11-24 Huang; Alan Scalable switching network

Also Published As

Publication number Publication date
DE69828890T2 (de) 2006-03-30
WO1998052126A1 (en) 1998-11-19
EP1010088B1 (en) 2005-02-02
EP1010088A1 (en) 2000-06-21
DE69828890D1 (de) 2005-03-10
US6006296A (en) 1999-12-21

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Legal Events

Date Code Title Description
B08F Application fees: application dismissed [chapter 8.6 patent gazette]

Free format text: REFERENTE A 8A,9A E 10A ANUIDADES

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO PUBLICADO 1976 DE 18/11/2008.