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BR9504270A - Circuitos que incluem células com requisitos de elevada abertura em leque com retardo rc reduzido - Google Patents

Circuitos que incluem células com requisitos de elevada abertura em leque com retardo rc reduzido

Info

Publication number
BR9504270A
BR9504270A BR9504270A BR9504270A BR9504270A BR 9504270 A BR9504270 A BR 9504270A BR 9504270 A BR9504270 A BR 9504270A BR 9504270 A BR9504270 A BR 9504270A BR 9504270 A BR9504270 A BR 9504270A
Authority
BR
Brazil
Prior art keywords
delay
circuits
reduced
include cells
fan opening
Prior art date
Application number
BR9504270A
Other languages
English (en)
Inventor
Steven Craig Bartling
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR9504270A publication Critical patent/BR9504270A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/506—Indexing scheme relating to groups G06F7/506 - G06F7/508
    • G06F2207/5063—2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Apparatus Associated With Microorganisms And Enzymes (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
BR9504270A 1994-10-14 1995-10-04 Circuitos que incluem células com requisitos de elevada abertura em leque com retardo rc reduzido BR9504270A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US32314994A 1994-10-14 1994-10-14

Publications (1)

Publication Number Publication Date
BR9504270A true BR9504270A (pt) 1998-12-22

Family

ID=23257917

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9504270A BR9504270A (pt) 1994-10-14 1995-10-04 Circuitos que incluem células com requisitos de elevada abertura em leque com retardo rc reduzido

Country Status (7)

Country Link
EP (1) EP0707262A1 (pt)
JP (1) JP3238052B2 (pt)
KR (1) KR960015198A (pt)
CN (1) CN1126859A (pt)
BR (1) BR9504270A (pt)
CA (1) CA2155379A1 (pt)
TW (1) TW269074B (pt)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2775531B1 (fr) * 1998-02-27 2001-10-12 Sgs Thomson Microelectronics Additionneur numerique rapide
GB9817899D0 (en) 1998-08-17 1998-10-14 Sgs Thomson Microelectronics Designing addition circuits
US20030069914A1 (en) * 1998-09-03 2003-04-10 Agilent Technologies Carry lookahead adder having a reduced fanout architecture
TWI361306B (en) 2008-07-11 2012-04-01 Au Optronics Corp Multidomain-vertical-alignment transreflective lcd

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU3289889A (en) * 1988-02-29 1989-09-22 Chopp Computer Corporation Carry generation method and apparatus
IT1249833B (it) * 1990-11-13 1995-03-28 Tong Lung Metal Ind Co Ltd Serratura a codice meccanico
US5278783A (en) * 1992-10-30 1994-01-11 Digital Equipment Corporation Fast area-efficient multi-bit binary adder with low fan-out signals
US5396435A (en) * 1993-02-10 1995-03-07 Vlsi Technology, Inc. Automated circuit design system and method for reducing critical path delay times

Also Published As

Publication number Publication date
JPH08123666A (ja) 1996-05-17
JP3238052B2 (ja) 2001-12-10
KR960015198A (ko) 1996-05-22
CN1126859A (zh) 1996-07-17
CA2155379A1 (en) 1996-04-15
TW269074B (en) 1996-01-21
EP0707262A1 (en) 1996-04-17

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Legal Events

Date Code Title Description
FB34 Technical and formal requirements: requirement - article 34 of industrial property law
HP Claimed priority lost
B07A Technical examination (opinion): publication of technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]

Free format text: INDEFERIDO COM BASE NO ARTIGO 8O COMBINADO COM O ARTIGO 13 DA LPI.