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BR8802944A - Pastilha de circuito integrado e processo para a disposicao de uma camada condutora - Google Patents

Pastilha de circuito integrado e processo para a disposicao de uma camada condutora

Info

Publication number
BR8802944A
BR8802944A BR8802944A BR8802944A BR8802944A BR 8802944 A BR8802944 A BR 8802944A BR 8802944 A BR8802944 A BR 8802944A BR 8802944 A BR8802944 A BR 8802944A BR 8802944 A BR8802944 A BR 8802944A
Authority
BR
Brazil
Prior art keywords
provision
integrated circuit
conductive layer
circuit insert
insert
Prior art date
Application number
BR8802944A
Other languages
English (en)
Inventor
Joseph John Gajda
Kris Vekatraman Srikrishnan
Paul Anthonyh Totta
Francis George Trudeau
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR8802944A publication Critical patent/BR8802944A/pt

Links

Classifications

    • H10W20/069—
    • H10W20/40—
BR8802944A 1987-08-20 1988-06-16 Pastilha de circuito integrado e processo para a disposicao de uma camada condutora BR8802944A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/087,478 US4839715A (en) 1987-08-20 1987-08-20 Chip contacts without oxide discontinuities

Publications (1)

Publication Number Publication Date
BR8802944A true BR8802944A (pt) 1990-01-23

Family

ID=22205430

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8802944A BR8802944A (pt) 1987-08-20 1988-06-16 Pastilha de circuito integrado e processo para a disposicao de uma camada condutora

Country Status (6)

Country Link
US (1) US4839715A (pt)
EP (1) EP0303812A1 (pt)
JP (1) JPS6461933A (pt)
AU (1) AU608042B2 (pt)
BR (1) BR8802944A (pt)
CA (1) CA1277435C (pt)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6365489B1 (en) 1999-06-15 2002-04-02 Micron Technology, Inc. Creation of subresolution features via flow characteristics
US8435873B2 (en) 2006-06-08 2013-05-07 Texas Instruments Incorporated Unguarded Schottky barrier diodes with dielectric underetch at silicide interface

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1910736C3 (de) * 1969-03-03 1978-05-11 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Herstellen von gegeneinander elektrisch isolierten, aus Aluminium bestehenden Leiterbahnen und Anwendung des Verfahrens
US4017890A (en) * 1975-10-24 1977-04-12 International Business Machines Corporation Intermetallic compound layer in thin films for improved electromigration resistance
US4028206A (en) * 1976-03-10 1977-06-07 William James King Method for cool deposition of layers of materials onto a substrate
US4307132A (en) * 1977-12-27 1981-12-22 International Business Machines Corp. Method for fabricating a contact on a semiconductor substrate by depositing an aluminum oxide diffusion barrier layer
GB1595659A (en) * 1978-05-25 1981-08-12 Standard Telephones Cables Ltd Providing conductive tracks on semiconductor devices
US4214018A (en) * 1978-08-14 1980-07-22 Rca Corporation Method for making adherent pinhole free aluminum films on pyroelectric and/or piezoelectric substrates
US4495221A (en) * 1982-10-26 1985-01-22 Signetics Corporation Variable rate semiconductor deposition process
US4525221A (en) * 1984-05-16 1985-06-25 Rca Corporation Alloying of aluminum metallization

Also Published As

Publication number Publication date
JPH0577338B2 (pt) 1993-10-26
CA1277435C (en) 1990-12-04
US4839715A (en) 1989-06-13
AU608042B2 (en) 1991-03-21
JPS6461933A (en) 1989-03-08
AU2096288A (en) 1989-02-23
EP0303812A1 (en) 1989-02-22

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Legal Events

Date Code Title Description
FD3 Appl. lapsed due to non-payment of renewal fee