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BR8605799A - Circuito de trava mestre-escravo - Google Patents

Circuito de trava mestre-escravo

Info

Publication number
BR8605799A
BR8605799A BR8605799A BR8605799A BR8605799A BR 8605799 A BR8605799 A BR 8605799A BR 8605799 A BR8605799 A BR 8605799A BR 8605799 A BR8605799 A BR 8605799A BR 8605799 A BR8605799 A BR 8605799A
Authority
BR
Brazil
Prior art keywords
master
lock circuit
slave lock
slave
circuit
Prior art date
Application number
BR8605799A
Other languages
English (en)
Inventor
Katuhisa Kubota
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP61062914A external-priority patent/JPS62202612A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of BR8605799A publication Critical patent/BR8605799A/pt

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/289Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable of the primary-secondary type
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037Bistable circuits
    • H03K3/0372Bistable circuits of the primary-secondary type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
BR8605799A 1985-11-26 1986-11-26 Circuito de trava mestre-escravo BR8605799A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP26646285 1985-11-26
JP61062914A JPS62202612A (ja) 1985-11-26 1986-03-20 マスタスレ−ブラツチ回路

Publications (1)

Publication Number Publication Date
BR8605799A true BR8605799A (pt) 1987-08-25

Family

ID=26403973

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8605799A BR8605799A (pt) 1985-11-26 1986-11-26 Circuito de trava mestre-escravo

Country Status (6)

Country Link
US (1) US4841168A (pt)
EP (1) EP0225075B1 (pt)
AU (1) AU574591B2 (pt)
BR (1) BR8605799A (pt)
CA (1) CA1275310C (pt)
DE (1) DE3673961D1 (pt)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4873456A (en) * 1988-06-06 1989-10-10 Tektronix, Inc. High speed state machine
DE3835116A1 (de) * 1988-10-14 1990-04-19 Siemens Ag Adressverstaerkerschaltung mit selbstverriegelung und sicherung gegen mehrfachadressierung zur verwendung in statischen gaas-rams
JP2569790B2 (ja) * 1989-03-13 1997-01-08 三菱電機株式会社 アービタ回路
US5072132A (en) * 1989-06-09 1991-12-10 Digital Equipment Corporation Vsli latch system and sliver pulse generator with high correlation factor
JP2990791B2 (ja) * 1990-11-20 1999-12-13 ソニー株式会社 コレクタドットアンド回路
US5248905A (en) * 1990-12-28 1993-09-28 National Semiconductor Corporation High speed, master/slave latch transceiver having a directly-driven slave stage
US5220212A (en) * 1991-10-10 1993-06-15 National Semiconductor Corp. Single level bipolar ECL flip flop
FR2732152B1 (fr) * 1995-03-21 1997-04-30 Suisse Electronique Microtech Element de memoire du type bascule maitre-esclave, realise en technologie cmos
AU1913500A (en) 1998-11-25 2000-06-13 Nanopower, Inc. Improved flip-flops and other logic circuits and techniques for improving layouts of integrated circuits
US6621302B2 (en) 2001-03-21 2003-09-16 Bae Systems Information And Electronic Systems Integration, Inc Efficient sequential circuits using critical race control
US20090013874A1 (en) * 2004-02-05 2009-01-15 Koninklijke Philips Electronics N.V. Beverage Making Device
JP5875996B2 (ja) 2013-02-13 2016-03-02 株式会社東芝 フリップフロップ回路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588545A (en) * 1969-11-12 1971-06-28 Rca Corp J-k' flip-flop using direct coupled gates
JPS56149114A (en) * 1980-04-21 1981-11-18 Nec Corp Flip-flop circuit
JPS59121697A (ja) * 1982-12-27 1984-07-13 Toshiba Corp シフトレジスタ
US4675553A (en) * 1984-03-12 1987-06-23 Amdahl Corporation Sequential logic circuits implemented with inverter function logic

Also Published As

Publication number Publication date
AU574591B2 (en) 1988-07-07
CA1275310C (en) 1990-10-16
EP0225075B1 (en) 1990-09-05
EP0225075A2 (en) 1987-06-10
AU6494286A (en) 1987-06-11
DE3673961D1 (de) 1990-10-11
EP0225075A3 (en) 1988-06-22
US4841168A (en) 1989-06-20

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Legal Events

Date Code Title Description
MM Lapse due to non-payment of fees (art. 50)