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BR8503021A - Circuito de controle de sinalizador em um aparelho de controle de acesso de memoria em um sistema computador digital - Google Patents

Circuito de controle de sinalizador em um aparelho de controle de acesso de memoria em um sistema computador digital

Info

Publication number
BR8503021A
BR8503021A BR8503021A BR8503021A BR8503021A BR 8503021 A BR8503021 A BR 8503021A BR 8503021 A BR8503021 A BR 8503021A BR 8503021 A BR8503021 A BR 8503021A BR 8503021 A BR8503021 A BR 8503021A
Authority
BR
Brazil
Prior art keywords
computer system
memory access
digital computer
signaler
control device
Prior art date
Application number
BR8503021A
Other languages
English (en)
Inventor
Miyuki Ishida
Takashi Chiba
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59128617A external-priority patent/JPS617959A/ja
Priority claimed from JP59128621A external-priority patent/JPS617960A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of BR8503021A publication Critical patent/BR8503021A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
BR8503021A 1984-06-22 1985-06-24 Circuito de controle de sinalizador em um aparelho de controle de acesso de memoria em um sistema computador digital BR8503021A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59128617A JPS617959A (ja) 1984-06-22 1984-06-22 タグ記憶装置制御方式
JP59128621A JPS617960A (ja) 1984-06-22 1984-06-22 バツフア無効化制御方式

Publications (1)

Publication Number Publication Date
BR8503021A true BR8503021A (pt) 1986-03-11

Family

ID=26464222

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8503021A BR8503021A (pt) 1984-06-22 1985-06-24 Circuito de controle de sinalizador em um aparelho de controle de acesso de memoria em um sistema computador digital

Country Status (8)

Country Link
US (1) US4760546A (pt)
EP (1) EP0165823B1 (pt)
KR (1) KR910001735B1 (pt)
AU (1) AU552199B2 (pt)
BR (1) BR8503021A (pt)
CA (1) CA1241768A (pt)
DE (1) DE3584476D1 (pt)
ES (1) ES8609771A1 (pt)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4768148A (en) * 1986-06-27 1988-08-30 Honeywell Bull Inc. Read in process memory apparatus
JP2965987B2 (ja) * 1988-02-22 1999-10-18 株式会社日立製作所 データ処理システム
DE68924306T2 (de) * 1988-06-27 1996-05-09 Digital Equipment Corp Mehrprozessorrechneranordnungen mit gemeinsamem Speicher und privaten Cache-Speichern.
US5025365A (en) * 1988-11-14 1991-06-18 Unisys Corporation Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors
US5222224A (en) * 1989-02-03 1993-06-22 Digital Equipment Corporation Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system
JPH035851A (ja) * 1989-06-01 1991-01-11 Fujitsu Ltd バッファ記憶装置
US5404482A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills
US5404483A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills
TW268967B (pt) * 1992-11-28 1996-01-21 Hoechst Ag
JP3304577B2 (ja) * 1993-12-24 2002-07-22 三菱電機株式会社 半導体記憶装置とその動作方法
EP1990728A4 (en) * 2006-02-27 2009-08-05 Fujitsu Ltd DEGENERATION CONTROL AND DEGENERATION CONTROL PROGRAM
WO2007097026A1 (ja) * 2006-02-27 2007-08-30 Fujitsu Limited キャッシュ制御装置およびキャッシュ制御プログラム
JP4327238B2 (ja) * 2006-02-28 2009-09-09 富士通株式会社 システムコントローラおよびキャッシュ制御方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3848234A (en) * 1973-04-04 1974-11-12 Sperry Rand Corp Multi-processor system with multiple cache memories
US4136386A (en) * 1977-10-06 1979-01-23 International Business Machines Corporation Backing store access coordination in a multi-processor system
JPS5849945B2 (ja) * 1977-12-29 1983-11-08 富士通株式会社 バツフア合せ方式
US4370710A (en) * 1980-08-26 1983-01-25 Control Data Corporation Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses
US4637024A (en) * 1984-11-02 1987-01-13 International Business Machines Corporation Redundant page identification for a catalogued memory

Also Published As

Publication number Publication date
EP0165823A2 (en) 1985-12-27
KR860000594A (ko) 1986-01-29
EP0165823B1 (en) 1991-10-23
DE3584476D1 (de) 1991-11-28
ES8609771A1 (es) 1986-07-16
KR910001735B1 (ko) 1991-03-22
ES544431A0 (es) 1986-07-16
CA1241768A (en) 1988-09-06
EP0165823A3 (en) 1988-10-26
US4760546A (en) 1988-07-26
AU4393485A (en) 1986-01-02
AU552199B2 (en) 1986-05-22

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Legal Events

Date Code Title Description
B21A Patent or certificate of addition expired [chapter 21.1 patent gazette]

Free format text: PATENTE EXTINTA EM 24/06/2000