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BR8104670A - Disposicao de circuito - Google Patents

Disposicao de circuito

Info

Publication number
BR8104670A
BR8104670A BR8104670A BR8104670A BR8104670A BR 8104670 A BR8104670 A BR 8104670A BR 8104670 A BR8104670 A BR 8104670A BR 8104670 A BR8104670 A BR 8104670A BR 8104670 A BR8104670 A BR 8104670A
Authority
BR
Brazil
Prior art keywords
circuit arrangement
arrangement
circuit
Prior art date
Application number
BR8104670A
Other languages
English (en)
Inventor
Maria G Corti
Mario Landi
Original Assignee
Italtel Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Italtel Spa filed Critical Italtel Spa
Publication of BR8104670A publication Critical patent/BR8104670A/pt

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2097Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/17Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0407Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023Failover techniques
    • G06F11/2025Failover techniques using centralised failover control functionality

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
BR8104670A 1980-08-26 1981-07-21 Disposicao de circuito BR8104670A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8024284A IT1209258B (it) 1980-08-26 1980-08-26 Disposizione circuitale atta a gestire lo scambio di dati tra una coppia di elaboratori, operanti secondo il principio master-slave, ed un elaboratore di supporto.

Publications (1)

Publication Number Publication Date
BR8104670A true BR8104670A (pt) 1982-04-06

Family

ID=11212939

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8104670A BR8104670A (pt) 1980-08-26 1981-07-21 Disposicao de circuito

Country Status (5)

Country Link
BR (1) BR8104670A (pt)
DE (1) DE3133715A1 (pt)
FR (1) FR2489556A1 (pt)
GB (1) GB2084770A (pt)
IT (1) IT1209258B (pt)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1255618B (it) * 1992-09-30 1995-11-09 Sits Soc It Telecom Siemens Unita' di controllo e di elaborazione duplicata per apparati di telecomunicazioni
DE4241319A1 (de) * 1992-12-09 1994-06-16 Ant Nachrichtentech Rechnersystem
JPH07152788A (ja) * 1993-06-28 1995-06-16 At & T Global Inf Solutions Internatl Inc 並列検索方法及びその方法を用いた並列演算処理コンピューターシステム

Also Published As

Publication number Publication date
DE3133715A1 (de) 1982-04-08
IT1209258B (it) 1989-07-16
FR2489556A1 (fr) 1982-03-05
IT8024284A0 (it) 1980-08-26
GB2084770A (en) 1982-04-15

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