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BR8003880A - Sistema de registradores de encadeamento - Google Patents

Sistema de registradores de encadeamento

Info

Publication number
BR8003880A
BR8003880A BR8003880A BR8003880A BR8003880A BR 8003880 A BR8003880 A BR 8003880A BR 8003880 A BR8003880 A BR 8003880A BR 8003880 A BR8003880 A BR 8003880A BR 8003880 A BR8003880 A BR 8003880A
Authority
BR
Brazil
Prior art keywords
recorders
chain
recorders system
chain recorders
Prior art date
Application number
BR8003880A
Other languages
English (en)
Inventor
P Fairchild
J Leininger
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR8003880A publication Critical patent/BR8003880A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
BR8003880A 1979-06-21 1980-06-20 Sistema de registradores de encadeamento BR8003880A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/050,570 US4296470A (en) 1979-06-21 1979-06-21 Link register storage and restore system for use in an instruction pre-fetch micro-processor interrupt system

Publications (1)

Publication Number Publication Date
BR8003880A true BR8003880A (pt) 1981-01-13

Family

ID=21966018

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8003880A BR8003880A (pt) 1979-06-21 1980-06-20 Sistema de registradores de encadeamento

Country Status (4)

Country Link
US (1) US4296470A (pt)
JP (1) JPS589457B2 (pt)
BR (1) BR8003880A (pt)
IT (1) IT1209221B (pt)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57196357A (en) * 1981-05-29 1982-12-02 Toshiba Corp Data processor
US4530049A (en) * 1982-02-11 1985-07-16 At&T Bell Laboratories Stack cache with fixed size stack frames
JPS5994045A (ja) * 1982-11-22 1984-05-30 Toshiba Corp 画像入力装置
US5596761A (en) * 1989-07-06 1997-01-21 Ricoh Company, Ltd. Central processing unit with internal register initializing means
JPH04346127A (ja) 1991-05-23 1992-12-02 Sony Corp 電子装置
EP0945787A3 (en) * 1991-07-08 2008-12-31 Seiko Epson Corporation Risc microprocessor architecture implementing fast trap and exception state
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
EP1526446A3 (en) 1991-07-08 2007-04-04 Seiko Epson Corporation Extensible RISC microprocessor architecture
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
JPH0546407A (ja) * 1991-08-12 1993-02-26 Toshiba Corp スタツク管理システム
FR2680591B1 (fr) * 1991-08-22 1996-01-26 Telemecanique Controleur d'interruption programmable, systeme interruptif et procede de controle d'interruption.
US5623665A (en) * 1992-01-13 1997-04-22 Sony Corporation Electronic apparatus for patching a read-only memory
JP3230262B2 (ja) * 1992-01-24 2001-11-19 ソニー株式会社 電子装置及びその固定情報修正方法
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
DE69311330T2 (de) 1992-03-31 1997-09-25 Seiko Epson Corp., Tokio/Tokyo Befehlsablauffolgeplanung von einem risc-superskalarprozessor
WO1993022722A1 (en) 1992-05-01 1993-11-11 Seiko Epson Corporation A system and method for retiring instructions in a superscalar microprocessor
JP3810805B2 (ja) * 1992-09-19 2006-08-16 ソニー株式会社 情報修正システム
JP3284614B2 (ja) * 1992-09-19 2002-05-20 ソニー株式会社 電子装置
DE69329778T2 (de) * 1992-09-29 2001-04-26 Seiko Epson Corp., Tokio/Tokyo System und verfahren zur handhabung von laden und/oder speichern in einem superskalar mikroprozessor
US6735685B1 (en) * 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
EP0849665B1 (en) 1992-12-31 2001-10-04 Seiko Epson Corporation System and method for register renaming
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5995996A (en) * 1993-06-15 1999-11-30 Xerox Corporation Pipelined image processing system for a single application environment
US5701479A (en) * 1993-06-15 1997-12-23 Xerox Corporation Pipelined image processing system for a single application environment
US5396616A (en) * 1993-06-15 1995-03-07 Xerox Corporation System for emulating multi-tasking pipelines in a single tasking environment
US5778221A (en) * 1997-03-17 1998-07-07 International Business Machines Corporation System for executing asynchronous branch and link in parallel processor
JP2001256062A (ja) * 2000-03-09 2001-09-21 Omron Corp 割込処理方法およびその方法を用いた演算処理装置
US7552261B2 (en) * 2001-10-12 2009-06-23 Mips Technologies, Inc. Configurable prioritization of core generated interrupts
US7487339B2 (en) * 2001-10-12 2009-02-03 Mips Technologies, Inc. Method and apparatus for binding shadow registers to vectored interrupts
US7313797B2 (en) * 2002-09-18 2007-12-25 Wind River Systems, Inc. Uniprocessor operating system design facilitating fast context switching
US7237216B2 (en) * 2003-02-21 2007-06-26 Infineon Technologies Ag Clock gating approach to accommodate infrequent additional processing latencies
US7900027B2 (en) * 2008-01-31 2011-03-01 International Business Machines Corporation Scalable link stack control method with full support for speculative operations

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3293610A (en) * 1963-01-03 1966-12-20 Bunker Ramo Interrupt logic system for computers
FR1477814A (pt) * 1965-04-05 1967-07-07
US3453600A (en) * 1966-08-18 1969-07-01 Ibm Program suspension system
US3440619A (en) * 1967-07-14 1969-04-22 Ibm Control system for maintaining register contents during interrupt and branch conditions in a digital computer
US3811114A (en) * 1973-01-11 1974-05-14 Honeywell Inf Systems Data processing system having an improved overlap instruction fetch and instruction execution feature
FR2216883A5 (pt) * 1973-02-01 1974-08-30 Etudes Realis Electronique
GB1426749A (en) * 1973-06-05 1976-03-03 Burroughs Corp Micro programme data processor having parallel instruction flow streams for plural level of subinstruction sets
JPS5412174B2 (pt) * 1973-07-02 1979-05-21
US3909797A (en) * 1973-12-13 1975-09-30 Honeywell Inf Systems Data processing system utilizing control store unit and push down stack for nested subroutines
US4050058A (en) * 1973-12-26 1977-09-20 Xerox Corporation Microprocessor with parallel operation
US4062058A (en) * 1976-02-13 1977-12-06 The United States Of America As Represented By The Secretary Of The Navy Next address subprocessor
JPS52129252A (en) * 1976-04-21 1977-10-29 Hitachi Ltd Program processing unit
US4041462A (en) * 1976-04-30 1977-08-09 International Business Machines Corporation Data processing system featuring subroutine linkage operations using hardware controlled stacks
US4097920A (en) * 1976-12-13 1978-06-27 Rca Corporation Hardware control for repeating program loops in electronic computers
US4079455A (en) * 1976-12-13 1978-03-14 Rca Corporation Microprocessor architecture
US4173782A (en) * 1978-01-03 1979-11-06 International Business Machines Corporation Return and link mechanism

Also Published As

Publication number Publication date
JPS589457B2 (ja) 1983-02-21
US4296470A (en) 1981-10-20
IT1209221B (it) 1989-07-16
JPS564847A (en) 1981-01-19
IT8021993A0 (it) 1980-05-13

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