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BE832915A - BUFFER MEMORY - Google Patents

BUFFER MEMORY

Info

Publication number
BE832915A
BE832915A BE159609A BE159609A BE832915A BE 832915 A BE832915 A BE 832915A BE 159609 A BE159609 A BE 159609A BE 159609 A BE159609 A BE 159609A BE 832915 A BE832915 A BE 832915A
Authority
BE
Belgium
Prior art keywords
buffer memory
buffer
memory
Prior art date
Application number
BE159609A
Other languages
French (fr)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of BE832915A publication Critical patent/BE832915A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G06F5/085—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register in which the data is recirculated

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Communication Control (AREA)
BE159609A 1974-08-30 1975-08-29 BUFFER MEMORY BE832915A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19742441584 DE2441584A1 (en) 1974-08-30 1974-08-30 BUFFER STORAGE

Publications (1)

Publication Number Publication Date
BE832915A true BE832915A (en) 1976-03-01

Family

ID=5924477

Family Applications (1)

Application Number Title Priority Date Filing Date
BE159609A BE832915A (en) 1974-08-30 1975-08-29 BUFFER MEMORY

Country Status (5)

Country Link
BE (1) BE832915A (en)
DE (1) DE2441584A1 (en)
FR (1) FR2283511A1 (en)
IT (1) IT1042058B (en)
NL (1) NL7509269A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7713708A (en) * 1977-12-12 1979-06-14 Philips Nv INFORMATION BUFFER MEMORY OF THE "FIRST-IN, FIRST-OUT" TYPE WITH FIXED INPUT AND VARIABLE OUTPUT.
NL7713706A (en) * 1977-12-12 1979-06-14 Philips Nv INFORMATION BUFFER MEMORY OF THE "FIRST-IN, FIRST-OUT" TYPE WITH A VARIABLE INPUT AND A VARIABLE OUTPUT.

Also Published As

Publication number Publication date
IT1042058B (en) 1980-01-30
FR2283511A1 (en) 1976-03-26
NL7509269A (en) 1976-03-02
DE2441584A1 (en) 1976-03-11

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