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AU7575398A - Shared, reconfigurable cache memory execution subsystem - Google Patents

Shared, reconfigurable cache memory execution subsystem

Info

Publication number
AU7575398A
AU7575398A AU75753/98A AU7575398A AU7575398A AU 7575398 A AU7575398 A AU 7575398A AU 75753/98 A AU75753/98 A AU 75753/98A AU 7575398 A AU7575398 A AU 7575398A AU 7575398 A AU7575398 A AU 7575398A
Authority
AU
Australia
Prior art keywords
shared
cache memory
memory execution
execution subsystem
reconfigurable cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU75753/98A
Inventor
Richard Rubinstein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of AU7575398A publication Critical patent/AU7575398A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU75753/98A 1998-05-15 1998-05-15 Shared, reconfigurable cache memory execution subsystem Abandoned AU7575398A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1998/010065 WO1999060480A1 (en) 1998-05-15 1998-05-15 Shared, reconfigurable cache memory execution subsystem

Publications (1)

Publication Number Publication Date
AU7575398A true AU7575398A (en) 1999-12-06

Family

ID=22267077

Family Applications (1)

Application Number Title Priority Date Filing Date
AU75753/98A Abandoned AU7575398A (en) 1998-05-15 1998-05-15 Shared, reconfigurable cache memory execution subsystem

Country Status (2)

Country Link
AU (1) AU7575398A (en)
WO (1) WO1999060480A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7653785B2 (en) 2005-06-22 2010-01-26 Lexmark International, Inc. Reconfigurable cache controller utilizing multiple ASIC SRAMS
US7734873B2 (en) 2007-05-29 2010-06-08 Advanced Micro Devices, Inc. Caching of microcode emulation memory

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1515376A (en) * 1975-07-09 1978-06-21 Int Computers Ltd Data storage systems
WO1994012929A1 (en) * 1992-11-23 1994-06-09 Seiko Epson Corporation A microcode cache system and method
EP0741356A1 (en) * 1995-05-05 1996-11-06 Rockwell International Corporation Cache architecture and method of operation
US5761720A (en) * 1996-03-15 1998-06-02 Rendition, Inc. Pixel engine pipeline processor data caching mechanism
KR100280285B1 (en) * 1996-08-19 2001-02-01 윤종용 Multimedia processor suitable for multimedia signals
DE19713178A1 (en) * 1997-03-27 1998-10-01 Siemens Ag Circuit arrangement with a processor and a data memory

Also Published As

Publication number Publication date
WO1999060480A1 (en) 1999-11-25

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase