AU717222B2 - Optical image authenticator - Google Patents

Description

WO 97/06502 PCT/AU96/00498 1 OPTICAL IMAGE AUTHENTICATOR Field of the Invention This invention generally relates to optical memory technology, and applications of such technology to the authentication of cards (such as credit cards, debit cards, access cards and the like), documents and products of various types. The invention particularly relates to methods and apparatus for detecting or reading data from a diffraction surface an optical memory), and further to authenticating that data in order to authenticate the diffraction surface.

Background of the Invention The fraudulent copying and counterfeiting of cards, documents and products is a substantial and growing problem due to the ease with which many of the existing anticounterfeiting devices (such as holograms) can themselves be copied or counterfeited.

Other related problems, including repackaging and parallel importation, are also resulting in substantial revenue losses to brand owners and manufacturers.

Various security devices are currently employed to protect against counterfeiting and the abovementioned related problems. These existing devices include optical devices such as holograms, pixelgrams, kinegrams, gyrograms and optically refractive surfaces based on the inclusion of patterns of glass microspheres.

Reference is made to the document having International Publication No.

WO 94/06097 (PCT/AU93/00455) in the name of the present applicant. This document summarises a large number of prior art documents relevant to the holographic patterns and kinegrams.

International Publication No. WO 94/06097 also describes an optical memory medium formed as a diffraction surface, and illustrates in Fig. 2b thereof an intensity pattern obtainable by illumination of the diffraction surface by a single collimated monochromatic incident optical beam. Furthermore, in Figs. 3a and 3b thereof, a system for reading and authenticating the diffraction surface is disclosed.

Summary of the Invention s The present invention is directed to overcoming or at least substantially ameliorating one or more of the disadvantages of the first mentioned prior art documents.

Furthermore, the present invention is directed to improvements in data detection and authentication over the arrangements disclosed in noted International Publication No.

WO 94/06097.

Therefore, in one aspect, the invention discloses apparatus for authenticating a light intensity pattern, the apparatus comprising: optical means for directing a pulsed light source at a diffractio surface in a manner to produce a diffracted image pattern at frame rate intervals and to detect said diffracted image pattern; I 15 memory means for storing an authentic pattern in the format of a pixel array; and data processing means for receiving a said detected pattern and for assigning, on a pixel-by-pixel basis, one of a number of digital values to each pixel in the detected pattern, and further for comparing each detected pixel with the corresponding pixel of said stored authentic pattern to determine whether the pixel is good or bad, and yet further 20 for authenticating said detected pattern or rejecting said detected pattern on the basis of the number of good pixels and/or the number of bad pixels.

Preferably, said pixels have assigned the binary value of 0 or 1, and said data processing means discriminates on a pixel-by-pixel basis which pixels of said detected pattern are light and which are dark on the basis of the binary value, and further determines whether a pixel is good if it is light or dark as expected from the corresponding authentic pixel, otherwise it is determined to be bad.

In a preferred form the data processing means can authenticate a detected pattern on the basis of the ratio of good to bad pixels.

Advantageously, the data processing means further provides for comparing a said detected pattern with one of a number of threshold values, the threshold values discriminating the detected pixels into said binary values.

Preferably, the invention further comprises optical reading means for reading a diffraction pattern to detect a said light intensity pattern. The optical reading means can comprise a light source for illuminating said diffraction pattern to cause generation of a [R:\LIBK]OI 789.doc:mxl -3return light pattern, said return light pattern being detected as light intensity by charge coupled device (CCD) or CMOS sensor means, for example.

Further preferably, said optical reading means reads a diffraction pattern periodically to detect said light intensity pattern in frames. The light source can be a laser beam source that is pulsed once within a frame. The CCD sensors respond to a said return light pattern over time, said response time being less than the period of a frame.

Yet further, said memory means can store said authentic pattern in a plurality of forms, each form being angularly rotated with respect to any other, and further wherein one or more of said forms of the authentic pattern are compared with the detected pattern so that the detected pattern can be authenticated against any one said forms of the authentic pattern.

The invention further discloses a method for authenticating a light intensity a. ,pattern, the method comprising the steps of: storing an authentic pattern in the format of a pixel array; 15 directing a pulsed light source at a diffraction surface at frame rate intervals in a manner to produce a diffracted image pattern; optically detecting said diffracted pattern; assigning, on a pixel-by-pixel basis, one of a number of digital values to each pixel in the detected pattern; 4 comparing each detected pixel with the corresponding pixel of said stored 4 authentic pattern to determine whether the pixel is good or bad; and *oo 4 °authenticating said detected pattern or rejecting said detected pattern on the basis of the number of good pixels and/or the number of bad pixels.

o o Preferably, the pixels have assigned the binary value of 0 or 1, and said step of assigning discriminates, on a pixel-by-pixel basis, which pixels of said detected pattern are light and which are dark on the basis of the binary value, and the step of comparing [R:\LIBK]O 1789 doc:mlI WO 97/06502 PCT/AU96/00498 4 determines whether a pixel is good if it is light or dark as expected from the corresponding authentic pixel, otherwise it is determined to be bad.

Brief Description of the Drawings An embodiment of the invention now will be described with reference to the accompanying drawings, in which: Fig. 1 is a top view of a diffraction surface; Fig. 2 shows a diffracted beam intensity pattern produced by the surface of Fig. 1; Fig. 3 shows, as a cross-sectional view, a diffraction surface reader; Fig. 4 is a schematic block diagram of the CCD sensor of the reader; Fig. 5 is a schematic block diagram of the reader and authentication apparatus; Fig. 6 is a schematic block diagram summarising the authentication process; and Figs. 7 and 8 are schematic block diagrams showing the authentication process in detail.

Description of Preferred Embodiments Fig. 1 is an illustration of a diffraction surface 10 as viewed from above the surface. The surface 10 includes a mesh pattern of etched regions 15 enclosed by ridges 11 and 13, with the mesh pattern varying across the surface 10. The diffraction surface 10 is arranged to produce a number of return diffracted beams when illuminated by monochromatic coherent light, each of which return beams produces a specified intensity pattern that can be machine-recognised in order to authenticate the diffraction surface Fig. 2 illustrates a type of diffracted beam intensity pattern which may be produced by a surface of the type shown in Fig. 1 when illuminated by a single, collimated, approximately monochromatic incident optical beam. In Fig. 2, white WO 97/06502 PCT/AU96/00498 indicates the maximum diffracted optical intensity, black indicates zero optical intensity, and different degrees of shading represent different intermediate levels of optical intensity in the diffracted beam intensity pattern projected onto an intercepting surface. The central spot of Fig. 2 represents specular reflection of the incident optical beam, illustrating that in this example the diffracted beam forms a pair of symmetrical images around the specular reflection beam. It should be appreciated that the diffraction surface 10 can be designed to produce a specified combination of angular size and angular position of the diffracted images in order to suit machine reading of the diffracted images. It should also be appreciated that part or all of the diffracted beam optical intensity pattern may be utilised to be machine read for the purposes of authentication of a device bearing the diffraction surface 10. The diffraction surface thus constitutes an optical memory.

Fig. 3 shows, as a cross-sectional view, a reading device 20 suitable for reading a diffraction surface of the type shown in Fig. 1. The reader has a light shield 22, the ends of which butt against a medium 16 carrying on one side thereof a diffraction surface 10 generally of the type shown in Fig. 1. The diffraction surface can occupy only a part or the whole of the substrate medium 16.

The reader 20 further has a source of near monochromatic light, in the form of a laser diode 24 carried by a focusing sleeve 26, in turn set in and secured to an outer shell 28 by set screws 30. The laser light output from the device 24 passes through a lens system 32, following which it is in the form of a beam of approximately coherent light. The beam then is incident on the diffraction surface 10 in a direction normal to the surface. The incident light source results in the production of a conjugate pair of return diffracted beams 34, 34'. Within the outer shell 28 are arranged sites for optical detector arrays 36, 38 coincident with the path of the diffracted beams.

The lens system is preferably adjusted so as to produce the sharpest diffracted images at the sites 36 and 38. This will result in the output beam from the lens system 32 being slightly converging. In the embodiment shown in Fig. 3, only the single WO 97/06502 PCT/AU96/00498 6 sensor array 38 is provided. The sensor array 38 is constituted by a charge coupled device (CCD) array positioned so that the diffracted beam 34 is incident upon approximately 60% of the total active pixel area of the CCD array.

Hence in this embodiment the CCD sensor array 38 detects only part of the total diffracted intensity pattern produced by the diffraction surface 10. The diffraction surface 10 and CCD array 38 will usually be configured so as to enable the CCD array 38 to detect one complete component of the zeroth order diffracted image produced by the surface 10 (with the remaining components of the zeroth order image being mirror images of the detected component).

In operation of the reading head, the laser diode light source 24 is pulsed once per frame with an 'on-time' which produces return signals at approximately 50% of the CCD sensor full well capacity. CCD devices function by accumulating charge over time in response to incident light. Thus the incident light must be pulsed for a discrete and uniform instant of time, and the sensor output appropriately 'framed' in consideration of the minimum time taken for the sensors to accumulate the charge due to the light pulse duration.

In one embodiment, the CCD sensor 38 is a 192 by 165 pixel format sensor.

The pixels typically are of a size 8.5 un by 10.0 gm. The CCD sensor in this embodiment utilises only 4 wires for complete operation, and the clock input signal to the sensor may preferably be TTL compatible.

The relative orientation of the collimating lens 32 and the diffraction surface is important so that the return beams 34, 34' occur at the location of the detector arrays 36, 38. Correct focusing can be obtained by placing adjusting the location of the collimating lens 32 to produce the optimum diffracted image at the detector array 38.

The diffractive surface 10 can be made up of a repetitive pattern of basic cell units, so that each cell unit produces a unique diffracted intensity image. In some instances the optical properties of the laser diode 24 and collimating lens 32 will result in an elliptical light pattern incident upon the diffractive surface 10. Configuring of the WO 97/06502 PCT/AU96/00498 7 optical components in some cases will need to take into account the lengths and orientations of the major and minor axes of said elliptical pattern, in particular to ensure that one or other of said axes coincides with a particular direction on the optical surface 10 and that the length of one or other of said axes is comparable with the characteristic dimension of the individual cell units of the diffraction surface 10. Most usually, this involves configuring the optical components to ensure that the minor axis of said ellipse is parallel to a specified direction in the optical surface 10 and that the length of said minor axis is comparable with said characteristic dimension, thereby ensuring that cells from no more than one row or column of the basic cell structure of said diffractive surface 10 are fully illuminated at any one time. Configuring said optical components to meet such requirements may in some instances involve placing an aperture in the path of the optical beam incident on the optical surface Fig. 4 shows a schematic diagram of the CCD sensor 38, that includes an array driver section 42 driving the pixel array 40. Further, there is a serial driver section 44 driving a multiplexing stage 46. The output from the multiplexer 46 is provided to an output amplifying section 48 and in turn to the output terminal 50. Input power supply terminal 52 receives a power supply for the clocking and drive electronics, together with providing power for the CCD array 40 and output amplifier section 48. A clock input line 54 controls integration time, parallel array shifting and serial register pixel readout. A ground reference connection point 56 also is provided.

Thus the output from terminal 50 represents an amplified form of serial register pixel data updated at the frame rate. For each frame, the output data for each pixel represents the received light intensity.

Fig. 5 shows a schematic block diagram of reading and authentication apparatus in accordance with a preferred embodiment. A low voltage (6 V) supply and high voltage supply are provided. The 6 V supply is regulated by the low voltage regulator 60 to a 5 V level. This voltage level supports all logic type devices and the pulsed laser driver circuit 62. The 18 V supply is regulated by the high voltage WO 97/06502 PCT/AU96/00498 8 regulator 64 to a 15.5 V supply, that provides power for all analogue circuits, including the CCD array 40 and the output amplifier 48, and is regulated down once again to 10 V DC for the video comparator 74.

Overall timing is derived from the master clock 66, which in an embodiment is a 10.0 MHz TTL oscillator, fed to a timing generator circuit 68, such as an Altera EPS-448 timing generator chip. The timing generator circuit 68 thus has responsibility for frame timing, which is chosen to be twice the mains frequency 120 Hz in the United States) to reduce the effects of line noise and stray light from sources such as fluorescent sources. In countries where the mains frequency is 50 Hz, the frame rate would be set at 100 Hz. The pixel readout from the CCD sensor 40 is at one half of the master oscillator frequency, i.e. at 5 MHz. The laser diode 24 is fired once per frame with an 'on time' in one embodiment of approximately 2 pts. The laser source remains idle for the remainder of the frame time, and such a low duty cycle is possible due to the sensitivity of the CCD sensors 40 and high reflectance of the diffraction surface 10. For diffraction surfaces 10 with lower diffractive efficiencies for example, "clear" diffractive surfaces 10 the laser diode 24 may need to have a longer on-time.

The laser drive circuit 62 consists of a charging circuit, a firing circuit, and preferably may also include a failsafe circuit feature to prevent damage to the laser diode 24 in the event of a circuit failure. The drive circuit is logic 1 to fire the laser diode 24 and logic zero in the off state.

A frame timing of 120 Hz gives a period of 8.333 ms. For a 2 ps on-time, this represents a duty cycle of 0.024%. Thus there is very little power dissipation by the laser diode, virtually eliminating the need for laser diode heat sinking.

The noise filter 70 filters the regulated supply from high frequency noise that otherwise would affect the output noise floor of the CCD array The amplified output from the CCD sensor 40 passes to a video buffer offset amplifier 72 to provide a DC offset so that the output signal is suitable for passing to WO 97/06502 PCT/AU96/00498 9 the video comparator 74. Also provided to the video comparator 74 is a DC input voltage that sets the threshold between black (dark) and white (light) pixels. The threshold level is previously determined by minimising false white pixels due to noise within the circuit and matching the number of illuminated pixels to a pre-stored digital image located in the pattern read-only memory 78. The video comparator 74 digitises the thresholded return pattern to a 1-bit digital data stream at the pixel rate. Thus the video comparator 74 determines, for each frame, definitively which pixels of the return diffraction intensity pattern are black or white. The thresholded return pattern then is passed to the first one of two LSI devices 80, 82 where the authentication processing 1o takes place.

Fig. 6 shows a typical pictorial representation of analogue output image from the CCD sensor 40 and subsequent thresholded analogue image as performed by the video comparator 74. The frame comparator 100 and the pixel accumulators 102, 104 represent a number of the components shown in Fig. 5, and particularly the LSI devices 80, 82 and the pixel scalers 86, 88.

From the pre-stored image stored in the pattern memory 78, each pixel is classified as "expected light" or "expected dark". There then follows a comparison with the thresholded return pattern, and pixels which are light where dark backgrounds are expected are classed as "bad"; pixels which are light where expected light are classed as "good". The converse comparison can in some preferred embodiments also be performed, with pixels which are dark where dark is expected being classed as "good", and which are dark where light is expected being classed as "bad". This testing is performed by the pixel accumulator 102. The total number of "good" and "bad" pixels are stored in two counters in the second pixel accumulator 104. At the end of each frame, the total pixel counts in each of the good and bad groups are subtracted, and further by the application of minimum difference rules, the determination of an authentic or non-authentic return intensity image per frame is determined.

WO 97/06502 PCT/AU96/00498 Fig. 7 is a schematic block diagram further detailing the authentication process. The thresholded data (VID) from the video comparator 74 is input to a twocycle delay latch 110 to be latched and delayed by two pixel cycles. The pattern ROM 78 is addressed by a 16 bit generator 112, being incremented at the pixel rate via the CLK input. The address generator 112 is cleared once per frame by the CLR* signal from the timing generator 68 and delay line 84.

Thus the digital data from the pattern ROM 78 is input to the three-cycle delay latch 114, thereby being latched and delayed by three pixel cycles to match the difference in propagation times from the CCD sensor 40 and the pattern ROM 78. The latched delay signal then is provided to a processing unit 116, that determines the good/bad pixel count and contains the steering logic. Each pixel from the pattern ROM 78 therefore is matched in time with the corresponding pixel from the CCD sensor to steer the detected pixels in terms of those pixels which are light and expected to be light and those pixels which are light but expected to be dark.

Pixels that are expected to be light and are determined to be so are fed to a rate multiplier (scaler) 118 as "good" pixels. The scaler 118 can be programmed via ADIV bits 0-3 of the selector 86 to feed through one clock cycle for each pixel received in this category down to one clock cycle for each 15 pixels received. The scaling of expected good pixels relative to bad pixels provides user selectivity in the authentication process.

In that case, for minimal security applications where low to moderate ratios of good to bad pixels would be allowable for the purposes of authentication, a direct count of good and bad pixels can be made without the use of the scaler circuits. Conversely, for high security applications, only one-of-eight good pixels might, for example, be passed for the purposes of authentication, thus requiring a ratio of at least eight good to every one bad pixel counted.

Fig. 7 also shows a "bad pixel" scaler 120. In that case, there is scaling of both good and bad pixel paths. The scaling of pixels which are light when expected to be dark, via BDIV bits 0-3 of the selector 88, could be necessary under conditions of WO 97/06502 PCT/AU96/00498 11 low security or where ambient lighting or high speed reader applications may require a reduction in bad pixel count sensitivity. Thus flexibility is included by the inclusion of both scalers, since this allows a wide range of good to bad pixel ratio count in the authentication process.

The outputs CKA and CKB from the LSI device 80 thus are classified as good and bad pixel count respectively, and either or both categories have been scaled depending on the level of security desired. Both the good pixel count and bad pixel count thus are passed to the second LSI device 82, as shown in particular detail in Fig.

8. Two diagnostic LED indicators 90, 92 also are provided by way of indication of good pixel count and bad pixel count.

The good pixel count and bad pixel count are separately passed to 16-bit counters 130, 132. Each counter's 12 lower significant bits are routed to a 12-bit subtracter circuit 134 that maintains a difference count at the pixel rate. In the simplest form, total counts in the good pixel counter which equal or exceed the bad pixel total count will result in a non-borrow condition in the subtracter 134. The 12-bit subtracted values and borrow bit are passed to a logic unit 136, where the minimum difference between good and bad pixel counts are combined with the subtracter borrow output to set a minimum difference requirement. Further logic can be incorporated to limit the absolute number of bad pixels in the bad pixel (CKB) count, ensuring that non-authentic diffraction patterns having a random return pattern outside the expected count ranges are rejected. Additional levels of logic can be added to accommodate unique good to bad pixel count situations.

The output from the logic circuit 136 is a valid signal (AGEB) that is passed to the LED indicator 94 shown in Fig. It should be noted that authentication of a number of different return patterns can be achieved by electronically selecting different EPROM chips, each storing a different valid pattern, and comparing the return pattern with each stored pattern to determine whether the return pattern matches any of the stored patterns.

WO 97/06502 PCT/AU96/00498 12 The embodiments described above exemplify the case where a diffraction surface is at a known and repeatable position with respect to the optical reading system, for example such as is the case where a "swipe-slot" credit card configuration is used.

In other instances the reader might be hand-held, and thus can have a varying positional distance from the diffraction surface, and furthermore, a differing rotational orientation. Two methods of compensating for such a situation are described as follows.

Rotation of the reading apparatus relative to the diffractive surface will result in rotation of the return diffracted images about the axis of specular reflection of the incident light beam. For such rotated images reaching the CCD sensor 38, the return pattern will have more pixels light which are expected to be dark than in the nonrotated situation. Thus there could be rejection of an otherwise valid diffraction surface.

As has been described, a one-bit serial string of data is stored in the pattern ROM 78, which is usually an EPROM device, and is used for comparison against the return beam pattern. Most common EPROM devices are structured for 8-bit bytes, hence there are effectively seven unused channels which are output along the single pattern channel being sampled at the pixel rate. By using six of the remaining seven channels in the EPROM, it is possible to provide for three images rotated on either side of the "central" pattern also to be loaded into the same EPROM. Thus a total of seven images can be stored, each one being a relative rotation with respect to the others. The degree of rotation for each step can be determined by considering the field of view of the CCD sensor and the largest rotational angle at which the pattern would still strike the CCD sensor, with the total rotational angle being divided into three segments on either side of the original image. Thus a comparison can be made with each one of the stored image patterns in sequence against a detected image pattern for the process of authentication, having the property of greater rotational freedom. The process basically is one of electronic de-rotation of the return images.

WO 97/06502 PCT/AU96/00498 13 The effective sample rate of the pattern data can be maintained by adding circuitry to allow the parallel simultaneous) processing of the seven channels.

Alternatively, a shift register could be clocked once per frame to select the next data bit pattern from the pattern EPROM for comparison with the detected return pattern (the serial technique). Using the (serial) shift register 1-of-7 technique would result in the authentication process increasing in time from a minimum of 8.333 ms up to a maximum 58.3 ms if the last pattern in the authentication loop was the match for the actual return image. One the other hand, the parallel reading and comparison of the 7 data streams would not suffer any such time penalty, but would involve considerable additional circuitry and a commensurate increase in power consumption. The use of "wider" EPROM devices (with more bits per word, such as 16 bit devices), with more unused channels, could further improve the ability to authenticate rotated return images using either the serial or parallel technique referred to above. Thus in general the serial comparison of the actual return images against electronically rotated pattern data results in a time penalty, while the parallel comparison of the return image with electronically rotated pattern data does not result in a time penalty but does involve increased electronic complexity and increased power consumption.

As follows, the use of EPROM devices having higher number of bit bytes could further improve the ability to authenticate rotated images.

The above technique deals with the electronic de-rotation of images. As noted, a similar situation arises where the return patterns are likely to shift linearly in a particular direction (which will here be arbitrarily termed the vertical direction) for example due to a relative motion between the diffraction surface and machine reading apparatus. A technique similar to the rotationally displaced authentic images can be employed. Again, a plurality of authentic images are stored, each having a differing relative linear translation (in one or two directions).

Return patterns generally can include dots, lines and even circles. Thus, in a second technique, by selecting patterns which have a singular region of return signal at WO 97/06502 PCT/AU96/00498 14 the top vertical extreme one horizontal tangent point) of the image, then by implementing a "floating point" pattern start location, the absolute vertical position of the return image can be easily detected, and thus the degree of vertical offset resolved.

The first illuminated pixel would reset the pattern EPROM address generator, hence the stored pattern would begin with the first pixel of the first line in which the pattern information was present for comparison with the return image.

In this way, less EPROM pattern data would be required in the authentication process, since only illuminated lines would be mapped. Restarting of the address generator (by a thresholded reset of the address generator) would start the comparison of the stored pattern data to the digitised return pattern. There would be no time penalty associated with this process, and data matching of the return data and the EPROM pattern would be handled in the same manner as the full frame authentication process.

The technique for compensating for linear movement of the return image can be extended to two dimensions, thereby allowing a "floating point" location of the return image, and hence the start point for the image authentication, in both the horizontal and vertical directions the X and Y directions in a Cartesian coordinate system).

The return pattern data described above utilises only one threshold in advance of a comparison with the stored pattern i.e. each pixel in the return pattern is converted into a simple binary "light/dark" signal. High security methods can incorporate grey scale comparison between stored patterns and the return patterns in which each pixel in the stored and return patterns is assigned one of a number of digital values rather than a simple binary 1 (light) or 0 (dark) value. Moving from one-bit to multi-bit data may be achieved through the addition of either more comparators to detect each of the values (levels), or a flash type analogue to digital converter. Data stored in the EPROM pattern array would be matched to the various digitised levels for WO 97/06502 PCT/AU96/00498 comparison with the multi-bit digitised return patterns using a technique similar to that described herein for single bit comparison.

In the reading head illustrated in Fig. 3 the output beam from the laser diode 24 and lens 32 is perpendicular to the diffraction surface 10. It is to be appreciated that the output beam may instead be incident on the diffraction surface 10 at a different angle, with the CCD sensor 38 positioned appropriately to accept the return diffracted beam 34.

In the embodiment described herein the output of the authenticator is used to activate an LED to indicate whether or not the return pattern from the diffraction surface is authentic. It should also be appreciated that the output of the authenticator could instead be used to activate or trigger another device or process, thereby acting as an optoelectronic security "key" for said device or process.

Numerous alterations and modifications, apparent to one skilled in the art, can be made without departing from the basic inventive concept. All such alterations and modifications are to be considered within the scope of the present invention.

Claims (14)

1. Apparatus for authenticating a light intensity pattern, the apparatus comprising: optical means for directing a pulsed light source at a diffraction surface in a manner to produce a diffracted image pattern at frame rate intervals and to detect said diffracted image pattern; memory means for storing an authentic pattern in the format of a pixel array; and data processing means for receiving a said detected pattern and for assigning, on io a pixel-by-pixel basis, one of a number of digital values to each pixel in the detected pattern, and further for comparing each detected pixel with the corresponding pixel of said stored authentic pattern to determine whether the pixel is good or bad, and yet further for authenticating said detected pattern or rejecting said detected pattern on the basis of the number of good pixels and/or the number of bad pixels. asin 2. Apparatus as claimed in claim 1, wherein said digital values are i assigned in a grey scale representation.

3. Apparatus as claimed in claim 1, wherein said pixels of said detected 20 pattern are assigned a binary value, and said data processing means discriminates, on a 5*4505 pixel-by-pixel basis, which pixels are light and which are dark on the basis of the binary value, and further determines whether a pixel is good if it is light or dark as expected from the corresponding authentic pixel, otherwise it is determined to be bad.

4. Apparatus as claimed in claim 3, wherein the data processing means authenticates a detected pattern on the basis of the ratio of good to bad pixels. [R:\LIBK]01789.doc:xl -17- Apparatus as claimed in claim 4, wherein the data processing means further provides for comparing a said detected pattern with one of a number of threshold values, the threshold values discriminating the detected pixels into said binary values.

6. Apparatus as claimed in any one of the preceding claims, wherein the optical means includes a charge coupled device (CCD) sensor that detects said detected pattern light intensity at least once per frame rate interval.

7. Apparatus as claimed in claim 6, wherein the CCD sensors respond to a said detected pattern over time, said response time being less than the frame'rate interval.

8. Apparatus as claimed in any one of the preceding claims, wherein said data processing means is further operable to detect the position of a first detected pixel in a detected pattern and match that pixel position with the respective position in said authentic pattern as an assigned starting point.

9. Apparatus as claimed in claims 1 to 7, wherein said memory means stores said authentic pattern in a plurality of forms, all of which forms being uniquely rotated or linearly translated with respect to any other, and further wherein said processor compares one or more of said forms of the authentic pattern with the detected pattern so that the detected pattern is simultaneously authenticated against any one said forms of the "authentic pattern. A method for authenticating a light intensity pattern, the method comprising the steps of: storing an authentic pattern in the format of a pixel array; directing a pulsed light source at a diffraction surface at frame rate intervals in a manner to produce a diffracted image pattern; optically detecting said diffracted pattern; [R:\LIBK]01789.doc:mxl -18- assigning, on a pixel-by-pixel basis, one of a number of digital values to each pixel in the detected pattern; comparing each detected pixel with the corresponding pixel of said stored authentic pattern to determine whether the pixel is good or bad; and authenticating said detected pattern or rejecting said detected pattern on the basis of the number of good pixels and/or the number of bad pixels.

11. A method as claimed in claim 10, whereby said digital values of said assigning step are in a grey scale representation.

12. A method as claimed in claim 10, whereby the pixels of said detected pattern are assigned a binary value, and said assigning step discriminates, on a pixel-by- pixel basis, which pixels are light and which are dark on the basis of the binary value, and the step of comparing determines whether a pixel is good if it is light or dark as expected Is from the corresponding authentic pixel, otherwise it is determined to be bad. oooo 0 13. A method as claimed in claim 12, whereby said authenticating step 0 comprises the steps of forming a ratio of good pixels and bad pixels; and comparing said ooo° ratio against a predetermined number which delineates authentic from unauthentic. S A method as claimed in claim 13, whereby the assigning step comprises 0ooo the steps of comparing a detected pattern with one of a number of threshold values; and discriminating each detected pixel into said binary values on the basis of the comparison.

15. A method as claimed in any one of the preceding claims, whereby said optical detection occurs at least one per frame rate interval.

16. A method as claimed in any one of claims 10 to 15, comprising the 'S 4 urther steps of: [R:\LIBKO]1I 789.doc:mnxl 'VL -19- detecting a first detected pixel in a detected pattern; and matching that pixel position with the respective position in said authentic pattern as a starting point for the pixel-by-pixel step of assigning.

17. A method as claimed in any one of claims 10 to 15, whereby the step of storing stores said authentic pattern in a plurality of unique forms, all of which being rotated or linearly translated with respect to any other, and said step of comparing compares one or more of said forms of the authentic pattern with the detected pattern so that the detected pattern is simultaneously authenticated against any one of said forms of the authentic pattern.

18. Apparatus for authenticating a light intensity pattern, said apparatus °being substantially as described herein with reference to any one of the embodiments, as that embodiment is described in the accompanying drawings.

19. A method for authenticating a light intensity pattern, said method being substantially as described herein with reference to any one of the embodiments, as that embodiment is described in the accompanying drawings. DATED this Thirty-first Day of December, 1999 i. ~Mikoh Technology Limited •Patent Attorneys for the Applicant SPRUSON FERGUSON [R:\LIBK]01789 doc mx