AU637460B2

AU637460B2 - Flexible-multiplexing process and device

Info

Publication number: AU637460B2
Application number: AU72474/91A
Authority: AU
Inventors: Claus Ehricke
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1990-04-06
Filing date: 1991-02-28
Publication date: 1993-05-27
Anticipated expiration: 2011-02-28
Also published as: JPH05502354A; CA2079793A1; JPH088553B2; DE4011264A1; BR9106317A; WO1991015905A1; EP0523059A1; AU7247491A

Description

I FLEXIBLE-MULTIPLEXING PROCESS AND DEVICE SThe invention relates to a method and an arrangement for flexible multiplexing.

A flexible multiplexer permits a liberal grouping and distribution of time slots of digital multiplex signals. It can establish connections between subscriberside interface units and perform grouping and division of multiplex signals between subscriber-side and^ line-side interface units as well as channel distribution between line-side interface units.

A multiplexing device of this type is known from the publication "PDMX-programmierbarer Digitalmultiplexer fir die 2-Mbit/s-Netzebene" (PDMX-programmable digital multiplexer for the 2-Mbit/s network level), published by Siemens AG, Bereich tbertragungssysteme, Postfach 700073, order no. A42020-S154-A1-2-29 and from the US Patent Specification US-A-4 725 835.

When a relatively large number of interface units, which are to be completely contactable among one another, are connected, the accommodation of correspondingly numerous speech/data and signaling multiplex signal lines presents problems. According to a prior proposal (EP-A-0 395 780, 07/11/90), a reduction of the multiplex signal lines is obtained if all subscriber-side and line-side interface units are no longer connected to each multiplex signal line, but rather if groups of subscriber-side interface units and the line-side interface units are connected in each case to a speech/data switching matrix via two speech/data multiplex signal lines for the two transmission directions, and to a signaling switching matrix via two signaling multiplex signal lines, likewise for the two transmission dtrections.

For example, 64-kbit/s signals or signals having a multiple bit rate thereof can be subjected to a time REPLACEMENT PAGE W, I ras;aarar~ 2 different frames, then according to the Application Note "Memory Time Switch Large", PEB 2047, Siemens AG, 12/89, a time compensation can be achieved if at least one byte, actually ending up in the first frame, is instead fed S 5 back from a second output of the switching matrix to a further input via a loop. As a result, this byte is delayed in the switching matrix by the duration of one frame, and subsequently all bytes at the first output of the switching matrix end up temporally in the same following frame. However, in effect this reduces the crosspoints that can be used since each looped byte must pass through a further crosspoint.

A flexible multiplexer is conceived for a specific number of interface units with a specific number of channel units contained therein. An interface unit of this type may contain a differing number of channel units however, so that a more or less large number of interface units also results for the multiplexer. However, the switching network array must always be designed here in such a way that it can serve the maximum number of Schannel units.

The object of the invention is, without substantially changing a basic device, to ensure the byte integrity in the first case mentioned and increase the number of interface units when required in the second case mentioned.

This object is achieved according to th invention by the features of Claim 1. Developments of the method and arrangements for carrying out the method emerge from the subclaims.

With this method, when the number of interface units is increased, smaller switching matrixes are not replaced by larger ones, but rather the smaller switching matrixes are supplemented by further switching matrixes.

This method accordingly makes it possible to accommodate add-on switching matrixes separately from the main switching matrixes and use them as required. In addition, channels 'can be switched through without and 'I 0, with delay as desired. The former is pursued in

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P 1 197 DE -3 particular for signals that have only one byte per frame and ara to be switched through with as little delay as possible. The latter can be used for ensuring byte integrity in the case of n x 64-kbit/s signals. In this case, the number of interface units is small and the unused additional possible connections or the additional crosspoints available can be used for loop circuits.

The basic device is a rack which, in addition to the main switching matrixes, is filled with interface units connected to these. In the case of an extension, the add-on switching matrixes are additionally accommodated therein, while the additional interface units are inserted into a second rack for reasons of space, from where they are connected to the add-on switching matrixes. Loops are only installed in the add-on switching matrixes so that the capacity of the main switching matrixes, that is to say the number of crosspoints available for switching through directly, is retained. If it were necessary to provide crosspoints for loops in the main switching matrixes, it would only be possible to serve a smaller number of interface units and the first rack would remain partly empty.

Only four symmetrical buses between the two racks for :he speech/data and signaling multiplex signal lines and only four asymmetrical buses between the neighboring main and add-on switching matrixes are required for carrying out the method. The latter is advantageous since the plug connections need have only half as many contacts as for symmetrical buses.

The invention will be explained in greater detail below with reference to exemplary embodiments: Fig. 1 shows a block circuit diagram of a flexible multiplexer according to a prior proposal, Fig. 2 shows a subscriber-side interface unit according to said prior proposal, Fig. 3 shows a line-side interface unit according to said prior proposal, Fig. 4 shows a block circuit diagram of a flexible multiplexer according to the invention, ~AiT U F j 4 Fig. 5 shows a block circuit diagram of a main and addon switching matrix, and Fig. 6 shows said main and add-on switching matrix with commercially available integrated circuits.

Figure 1 shows the block circuit diagram of the flexible multiplexer according to the prior proposal.

Said multiplexer contains subscriber-side interface units T 7a, 8a, 9, 10 and 11, line-side interface units L 12, 13 and 14, a control device 15, a speech/data main switching matrix 16a, a signaling main switching matrix 17a, speech/data buses 18a and 19a, signaling buses and 21a, speech/data multiplex signal lines 22a, 22d, 23a and 23d, signaling multiplex signal lines 24a, 24d, and 25d, and a control bus 26 which is connected to all subscriber-side interface units 7a, 8a, 9, 10 and 11 and to all main switching matrixes 1Ga and 17a. The designation S/D signifies that either speech or data signals can be transmitted in a time slot. The designation Kz stands for signaling information signals.

Before the functioning of the arrangement according to Figure 1 is discussed, a subscriber-side interface unit T is presented in Figure 2 and a line-side interface unit L is presented in Figure 3.

Figure 2 shows the subscriber-side interface unit T with eight channel units K, time/space switches 27 and 28, and space/time switches 29 and 30. The channel units K and the time/space switches 27 and 28 on the one hand and the space/time switches 29 and 30 on the other hand are connected to one another, in that connections denoted by the same three-digit numbers are interconnected. The time/space switches 27 and 28 and space/time switches 29 and 30 are set via the control bus 26. Input signals with a bit rate of n x 64 kbit/s are converted into n bytes per frame.

Figure 3 shows a line-side interface unit L with a frame multiplexer 31 and a frame demultiplexer 32. M denotes multiplex signals. These may be, for example, 2048-kbit/s signals, in the 16th frame of which 4-bit signaling words for two channels are transmitted in each T 0 -QLU i T N

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5 case. The latter are converted into byte-long signaling words.

In Figure 1 the subscriber-side interface units T are connected in groups. Thus, for example, the subscriber-side interface units 7a and 8a and further non-illustratad subscriber-side interface units T form a group, which are connected in each case via four multiplex signal lines 22a to 25a to the buses 18a to 21a proceeding in the form of a star from the main switching matrixes 16a and 17a. Also connected to said buses are the line-side interface units L; the line-side interface unit 12, for example, via the multiplex signal lines 22d to 25d. The main switching matrixes 16a and 17a and the buses 18a to 21a are parts of a controller CTR. There are external inputs 1 and external outputs 2 for speech/data signals S/D, there are external inputs 3 and external outputs 4 for signaling information signals Kz, and there are external inputs 5 and external outputs 6 for multiplex signals M, The main switching matrixes 16a and 17a are realized by integrated circuits PEB 2040 or PEB 2047, and the interface units T and L are equipped, for example, with integrated circuits FEB 2055.

Figure 4 shows a flexible multiplexer according to the invention. Said multiplexer contains in a rack I the controller CTR known from Figure 1, the subscriberside interface units 7a and 8a, the line-side interface units 12 and 13, the control device 15 and also a switching network extension SNE according to the invention, and in a rack II groups of subscriber-side interface units 7b and 8b as well as 7c and 8c.

The switching network extension SNE contains in each case one speech/data add-on switching matrix 16b and one signaling add-on switching matrix 17b in optionally different sizes. The buses 18a to 21a already known from Figure 1 are lead further asymmetrically to the add-on switching matrixes 16b to 17b via the switching matrix interfaces 45-48. In addition, buses 18b to 21b are lead to said add-on switching matrixes via symmetrical frame interfaces 35 to 38, out from which multiplex signal

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I c i 6 lines 22b to 25b and 22c to 25c are lead to the subscriber-side interface units 7b and 8b as well as 7c and 8c. Bus loops 33 and 34 are furthermore connected for the purpose of delay.

5 Figure 5 shows a block circuit diagram of a speech/data main switching matrix 16a with a speech/data add-on switching matrix 16b. This block circuit diagram applies analogously to a signaling main switching matrix 17a with signaling add-on switching matrix 17b. The reference symbols of the latter are shown in brackets.

Time slots in the speech/data multiplex input signals S/D-EM1 and in the signaling multiplex input signals Kz-EM1 can be cross-connected either via the speech/data main switching matrix 16a and the signaling main switching matrix 17a respectively into speech/data multiplex output signals S/D-AM1 and signaling multiplex output signals Kz-AM1 respectively, or via the speech/data add-on switching matrix 16b and the signaling add-on switching matrix 17b into speech/data multiplex output signals S/D-AM2 or S/D-AM3 and signaling multiplex -output signals Kz-AM2 or Kz-AM3 respectively. Speech/data multiplex input signals S/D-EM2 and signaling multiplex input signals Kz-EM2 can be cross-connected over via the speech/data add-on switching matrix 16b and the signaling add-on switching matrix 17b respectively either into speech/data multiplex output signals S/D-AM1 and signaling multiplex output signals Kz-AM1 respectively, or speech/data multiplex output signals S/D-AM2 or S/D-AM3 and signaling multiplex output signals Kz-AM2 or Kz-AM3 respectively. Time slots of the multiplex output signals S/D-AM3 and Kz-AM3 can be delayed via the bus loops 33 and 34 respectively, which may be formed by one or more lines, for the duration of one frame as multiplex input signals S/D-EM3 and Kz-EM3 respectively. A multiple loop may also be formed along the arrow with a broken line.

Figure 6 shows the realization of the block circuit diagram according to Figure 5 with integrated circuits PEB 2047 under the reference symbols 16a, 39, and 41 for speech/data and 17a, 42, 43 and 44 for

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r k i i, LS 7 signaling information. The numbers with an asterisk indicate how many S/D or Kz multiplex signal lines run in parallel in each case, and the numbers 512 and 1024 associated values in brackets indicate the number of possible channels on the buses 18a to 21a and 18b to 21b for 64-kbit/s signals in this case. The buses 18a to 21a of the controller CTR are connected to the switching network extension SNE via the asymmetrical switching matrix interfaces 45 to 48.

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Claims

1. Method for flexible multiplexing, in which first speech/data input signals (S/D-ES1) and first signaling input signals (Kz-ES1) of an n-fold first bit rate (n 1, 2, 3, are combined in a time slot first assignment to form first speech/data multiplex input signals (S/D-EM1) and to form first signaling multiplex input signals (Kz-EM1) of a second bit rate, in which these and further speech/data (S/D-EM1) and signaling (Kz-EM1) multiplex input signals resulting from mixed speech/data and signaling multiplex signals are cross-connected over in a time slot second assignment into first speech/data (S/D-AM1) and first signaling (Kz-AM1) multiplex output signals, and in which the first speech/data (S/D-AM1) and signaling (Kz-AM1) multiplex output signals are divided into first speech/data (S/D-AS1) and signaling (Kz-AS1) output signals of the n-fold first bit rate or combined to form mixed speech/data and signaling multiplex signals wherein second speech/data input signals (S/D-ES2) and second signaling input signals (Kz-ES2) of the n-fold first bit rate are combined in an add-on time slot first assignment to form second speech/data multiplex input signals (S/D-EM2) and to form second signaling multiplex input signals (Kz-EM2) of the second bit rate, wherein the first speech/data (S/D-EM1) and signaling (Kz-EM1) multiplex input signals are cross-connected over in an add-on time slot second assignment into second (S/D-AM2) and third (S/D-AM3) speech/data multiplex output signals respectively, and second (Kz-AM2) and third (Kz-AM3) signaling multiplex output signals respec- tively, wherein the second speech/data (S/D-EM2) and signaling (Kz-EM2) multiplex input signals are cross-connected over in the add-on time slot second assignment into first speech/data (S/D-AM1) and signaling (Kz-AMI) multiplex output signals and/or second (S/D-AM2) or third (S/D-AM3) speech/data multiplex output signals respectively, and NT w i i II I 9 second (Kz-AM2) or third (Kz-AM3) signaling multiplex output signals respectively, wherein the second speech/data (S/D-AM2) and signaling (Kz-AM2) multiplex output signals are divided into second speech/data (S/D-AS2) and signaling (Kz-AS2) output signals of the n-fold first bit rate, and wherein the third speech/data (S/D-AM3) and also the third signaling (Kz-AM3) multiplex output signals in the add-on time slot second assignment are now delayed by the duration of one frame time slot by time slot as third speech/data (S/D-EM3) and signaling (Kz-EM3) multiplex input signals via a loop pass.

2. Method as claimed in claim 1, wherein the first bit rate is less than or equal to 64 kbit/s and the second bit rate is selected to be 2048, 4096 or 8192 and 1544, 3088 or 6176 kbit/s.

3. Flexible multiplexer for carrying out the method as claimed in claim 1 or 2, having first subscriber-side interface units (7a, 8a, 9- 11), the channel units with an external speech/data input with an external speech/data output with an external signaling input and with an external signaling output having line-side interface units (12-14) which contain an external multiplex signal input and an external multiplex signal output having a controller (CTR) which contains a speech/data main switching matrix (16a), which is connected via first buses (18a, 19a) from first speech/data multiplex signal lines (22a, 23a; 22d, 23d) to the interface units (7a, 8a, 12, 13), and a signaling main switching matrix (17a), which is connected via second buses (20a, 21a) from first signaling multiplex signal lines (24a, 25a; 24d, 25d) to the interface units (7a, 8a, 12, 13), and having a control device (15) which is connected via a i control bus (26) to all subscriber-side interface units (7a, 8a, 9-11) and main switching matrixes (16a, 17a), wherein second subscriber-side interface units (7b, 8b; 7c, 8c) are provided which have channel units with an i e 11 I-I external speech/data input with an external speech/data output with an external signaling input and with an external signaling output wherein a speech/data add-on switching matrix (16b) is provided which is connected via third buses (18b, 19b), consisting of third speech/data multiplex signal lines (22b, 23b; 22c, 23c), to the second subscriber-side interface units (7b, 8b; 7c, 8c) and via the first buses (18a, 19a) to the first speech/data multiplex signal lines (22a, 23a; 22d, 23d), wherein a signaling add-on switching matrix (17b) is provided which is connected via fourth buses (20b, 21b), consisting of fourth signaling multiplex signal lines (24b, 25b; 24c, 25c), to the second subscriber-side interface units (7b, 8b; 7c, 8c) and via the second buses 21a) to the first signaling multiplex signal lines (24a, 25a; 24d, wherein speech/data (33) and signaling (34) delay loops are provided between outputs and inputs in tLe speech/data add-on switching matrix (16b) and in the signaling add-on switching matrix (17b), and wherein the second subscriber-side interface units (7b, 8b 7c, 8c), the speech/data add-on switching matrix (16b) and the signaling add-on switching matrix (17b) are connected to the control device (15) via the control bus (26).

4. Flexible multiplexer as claimed in claim 3, wherein the first subscriber-side interface units (7a, 8a, 9-11) and also line-side interface units (12-14), the speech/data main switching matrix (16a), the signaling main switching matrix (17a), the speech/data add-on switching matrix (16b) and the signaling add-on switching matrix (17b) are arranged in a first rack and the second subscriber-side interface units (7b, 8b; 7c, 8c) are arranged in a second rack (II). Flexible multiplexer as claimed in claim 4, wherein one or two plug-in slots are provided in the first rack in which either the speech/data add-on SI* switching matrix (16b) and the signaling add-on switching A *A 1 1 t IRN: 167390 INSTR CODE: 61890 1 KRS/665P 11 matrix (17b) or first subscriber-side interface units (7a, 8a, 9-11) or line-side interface units (12-14) are accommodated as desired.

6. Flexible multiplexer as claimed in claim 3, wherein the subscriber-side interface units (7a-7c, 8a- 8c, 9-11) contain a first time/space switch which connects time slots of the speech/data multiplex output signals (S/D-AM1, S/D-AM2) to selected external speech/data outputs a second time/space switch which connects time slots of the signaling multiplex output signals (Kz-AM1, Kz-AM2) to selected signaling outputs a first space/time switch which connects external speech/data inputs to selecte. time slots of the speech/data multiplex input signal; (S/D-EM1, S/D-EM2), and a second space/time switch which connects external signaling inputs to selcted time slots of the signaling multiplex input signals (Kz-EM1, Kz-EM2).

7. Flexible multiplexer as claimed in claim 3, wherein the line-side interface units (12-14) contain a frame multiplexer which converts and nests speech/data multiplex output signals (S/D-AM1) and signaling multiplex output signals (Kz-AM1) and outputs them to an exte,'nal multiplex signal output and a frame demultiplexer which separates mixed speech/data and signaling multiplex signals and outputs speech/data (S/D-EM1) and signaling (Kz-EM1) multiplex input signals.

8. Flexible multiplexer as claimed in claim 4, wherein the speech/data (16a) and the signaling (17a) main switchJing matrixes are connected respectively to the speech/data (16b) and the signaling (17b) add-on switch- ing matrix via two asymmetrical switching matrix inter- faces (45, 46 and 47, 48 respectively) in each case at the input and at the output of the speech/data (16a) and the signaling (17a) main switching matrix respectively.

9. Flexible multiplexer as claimed in claim 4, wherein the speech/data (16b) and the signaling (17 wn mixed speech/data and signaling multiplex signals wherein second speech/data input signals (S/D-ES2) and second signaling input signals (Kz-ES2) of the n-fold first bit rate are combined in an add-on time slot first 1* i /2 12 add-on switching matrixes are connected respectively to the second subscriber-side interface units (7b, 8b; 7c, 8c) via two symmetrical rack interfaces (35, 36 and 37, 38 respectively) in each case. P 1197 DE -13- Abstract A flexible multiplexer for speech, data and signaling information signals having an individual n-fold bit rate (n 1, 2, 3, at the external inputs and outputs is to be assigned further interface units (7b, 7c, 8b, 8c) without changes to the basic device This is made possible by add-on switching matrixes (16b, 17b) in which speech/data and signaling information signals (S/D-ES1, Kz-ES1) combined in interface units (7a, 8a, 12, 13) of the basic device to form multiplex signals (S/D-EM1, Kz-EMI), and speech/data and signaling informa- tion signals (S/D-ES2, Kz-ES2) combined in the further interface units (7b, 7c, 8b, 8c) to form multiplex signals (S/D-EM2, Kz-EM2) are cross-connected and are output as new multiplex signals (S/D-AM1, S/D-AM2, Kz-AM1, Kz-AM2) both at interface units (7a, 8a, 12, 13) of the basic device and at the further interface units (7b, 7c, 8b, 8c). If a plurality of bytes originat- ing from one frame were to end up temporally in two 20 different frames during cross-connection, then time compensation can be accomplished with a delay of the duration of one frame via bus loops (33, 34) between outputs and inputs of the add-on switching matrixes (16b, 17b). Flexible multiplexers permit a liberal grouping and distribution of time slots of digital multiplex signals. Figure 4 iT N T l