AU606815B2 - Apparatus for encoding/transmitting images - Google Patents

Description

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AUSTRALIA

PATENTS ACT 1952 COMPLETE SPECIFICATION Form

(ORIGINAL)

FOR OFFICE USE60 6 Short Title: Int. Cl: Application Number: Lodged: This document contains the amendments made under Section 49 and is correct for printing.

Complete Specification-Lodgeds Accepted: Lapsed: Published: Priority: Related Art: 441 8844 TO BE COMPLETED BY APPLICANT Name of Applicant: Address of Applicant:

MITSUBISHI

KAISHA

DENKI KABUSHIKI 8 4 Ia e i Actual Inventor: 2-3 MARUNOUCHI 2 CHOME

CHIYODA-KU

TOKYO 100

JAPAN

GRIFFITH HACK CO., 601 St. Kilda Road, Melbourne, Victoria 3004, Australia.

Address for Service: 8 8 4 Complete Specification for the invention entitled: APPARATUS FOR ENCODING/TRANSMITTING IMAGES The following statement is a full description of this invention including the best method of performing it known to me:- 1 form for" guidance in completing this part DECLARED at Tokyo, Japan this _6Lthday of lo__embe_ 19 APPARATUS FOR ENCODING/TRANSMITTING IMAGES BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a technology for transmitting image signals obtained by encoding image information which utilizes the so-called vector quantization technique and which is applicable to the fields such as the television (TV) conference system and R the TV telephone system.

4o aThis application is a divisional of Australian 10 Patent Application No. 73379/87, the contents of which are I 0. 0 o incorporated herein by reference. There are also other o a divisional applications of the noted parent application.

Description of the Prior Art As a result of the remarkable advance of the o 5, image processing technology in recent years, there have 0 been made various attempts to put, for example, the TV OMU conference system and the TV telephone system to the practical use by mutually and bidirectionally transmitting the image information. In such a technological field, the 020. quantization technique has been used in which the image signals as the analog quantity are classified into a finite number of levels changing in a discrete fashion within a fixed width and a unique value is assigned to each of these levels. Particularly, there has been a considerable advance in the vector quantization technique in which a plurality of samples of the image signals are grouped in blocks and each block thereof is mapped onto a pattern most similar thereto in a 1Amultidimensional signal space; thereby accomplishing the quantization.

The study of the vector quantization technology has been described in the following reference materials, for example.

"An Algorithm for Vector Quantizer.iDesign" by Y. Linde, A. Buzo, and R. M. Gray (IEEE TRANSACTION ON o. .o COMMUNICATIONS, Vol. COM.28, No. 1, January 1980, pp.

0o o 84 o 0O 10 "On the Structure of Vector Quantizers" by A. Gersho (IEEE TRANSACTION ON INFORMATION THEORY, Vol. IT28, No. 2, 0o00 March 1982, pp. 157 166) "Speech Coding Based Upon Vector Quantization" by A. Buzo, A. H. Gray Jr., R. M. Gray and J. D. Markel 0000 0 00 1°5 (IEEE TRANSACTION ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, Vol. ASSP28, No. 5, October 1980, pp. 562 0 0 574) Moreover, the following U.S. Patents have been 0o0 o obtained by the assignee of the present invention.

0. 0 a o U.S.P.N. 4,558,350 "VECTOR QUANTIZER", Murakami U.S.P.N. 4,560,977 "VECTOR QUANTIZER", Murakami et al.

2 Referring now to FIGS. 1 -3B3, the prior art technology of the present invention will be described.

The conventional image encoding/transmitting apparatus, as shown in FIG. 1, includes a subtractor 1 for obtaining a difference between an input signal S 1 such as an image signal and an estimation signal S 9 and for output-ting an estimated error signal S 2 a movement dete&ting circuit 0 0 0 a0CI 2 for comparing a threshold value T with the estimated 0 0 0 a0 error signal S2 to detect a movement or a change and for o 00 0 0 0090 0Q generating and outputting a movement or change detect signal S3 and a differential signal S 4 a quantization 0000 circuit 3 for quantizing the movement or change detect signal S 3 and the differential signal S 4 to output a quantization signal S 5 a variable length encoder 4 for 0 0 4 5 04 1~5 generating from the quantization signal S -an encoded o to 5 001 0 signal S 6 with a variable length and for outputting the 00encoded signal S 6 a transmission data buffer circuit for temporarily storing the encoded signal S 6 and for 00 1 20 a local decoding circuit 6 for generating a reproduced differential signal S 7 from the quantization signal delivered from the quantization circuit 3 and outputting the reproduced or regenerated differential signal S 7 an adder 7 for achieving an addition on the reproduced differential signal S 7 and the estimation signal S 9and for outputting a reproduced input signal S 8 an estimating circuit 8 for outputting an estimation signal S 9 based on -3- I' 11- 7 0 0o Do 0o 0 0 0 00 o 0 0a the reproduced input signal S8, and a threshold generating circuit 9 for monitoring the amount of the encoded signal S 6 accumulated in the transmission data buffer circuit 5 and for generating an approprite threshold value T.

The movement detecting circuit 2 comprises, as shown in FIG. 2, an absolute value circuit 10 for -calculating the absolute value IS 2 1 of the estimated error signal S 2 a comparing circuit 11 for effecting a comparison between 0 the absolute value IS21 of the estimated error signal S 2 0 and the threshold value T and for outputting the movement or change detect signal S3, and a zero allocator 12 for allotting 0 and outputting 0 as the differential signal

S

4 when the movement or change is not detected as a 0 15 result of the comparison in the comparing circuit 11.

The movement detect signal S 3 is converted into a running record R by use of the running length encode table 4a to generate serial data. In addition, only when the movement 0 detect signal S 3 is indicating the validness, the 020 quantization signal S5 is converted into a variable-length record through the variable-length encode table 4b to generate serial data (FIGS. 2B 2C). Reference numeral 4C indicates a multiplex operation control section.

In contrast to the configuration on the transmission side of FIGS. 1 2B, the configuration on the reception side is shown in FIGS. 3A'- 3B. In FIG. 3A, the equipment on the reception side includes a receiving data 0 0 0 0 0 0 0 0 o 0 0 0.

0 000 0 0 0 l 4) 4 1.

buffer circuit 13 for receiving and for temporarily storing the encoded signal S 6 delivered from the transmission data buffer circuit 5 on the transmission side, a variable length decoder 14 for decoding the encoded signal S 6 stored in the receiving data buffer 13 to output a reproduced quantization signal Sl 1 a local decoding circuit 15 for outputting a reproduced 0o, differential signal S12 based on the reproduced quantization signal Sll, an adder circuit 16 for obtaining 10 the difference between the reproduced differential signal alp, S 1 2 and the reproduced estimation signal S 1 3 and for reproducing the input signal S 14 which corresponds to the reproduced input signal S 8 on the transmission side, and an estimating circuit 17 for outputting the reproduced 15 estimation signal S13.

After the encoded signal S 6 undergone the 0o 0 mit tiplexing in the variable-length encode circuit 4 is received by the receive buffer circuit 13, the data is oooo0 distributed to the respective decode tables of variable 0000oooo o-o 20 codes under control of the multiplex separation control o 00 circuit 14a. As a result of the decoding, the movement detect signal and the quantization signal are attained.

Moreover, when the decoded movement detect signal indicates the invalidness the quantization signal is reset to by the flip-flop 14c, thereby outputting the output Sll (FIG. 3B).

J

A

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i

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I i t!j Next, the operation on the transmission side will be described with reference to FIGS. 1 2.

Assuming first the non-effective error in the movement detecting circuit 2 to be d, the estimation coefficient to be applied to the reproduced input signal

S

8 in the estimating circuit 8 to be A, and the delay of the time t to be Z the following relationships are satisfied.

S

2 S1 S9

S

4

S

2 d

S

7

S

4

Q

S

8 7 S59 S1 Q d Sg Sg S9 8A S 8 Z t The subtractor 1 calculates the estimated error signal S2 representing the difference between the input signal S 1 and the estimated signal S 9 whereas the movement detecting circuit 2 outputs the movement or change detection signal S3 and the differential signal S 4 based on the estimated error signal S 2 calculated by the subtractor i.

A detailed description will be given of the operation of the movement detecting circuit 2 by referring to FIG. 2. The allotting absolute value circuit 10 obtains the absolute value of the estimated error signal S2 and then the comparison circuit 11 achieves a comparison between the absolute value Is21 of the estimated error signal S 2 and the threshold value T generated by the threshold value generating circuit 9.

6 1 The movement detection signal S, is output in 3 conformity with the following conditions.

S

3 0 (invalid) IS 2 1

T

S

3 1 (valid) Is 2 1 T When the movement or change is not detected, namely, for "S3 zero allocator 12 outputs for the differential signal S 4 t On the other hand, the quantization circuit 3 converts the inputted differential signal S 4 according to an arbitrary characteristic. The variable encoding circuit 4 receives the quantization signal S 5 only when the movement detection signal S 3 is valid, namely, for

"S

3 1" and, for example, conducts a run-length encoding on the movement detection signal S 3 For the quantization 4 1 ''15 signal S 5 a code having a smaller code length is assigned S a to a value in the neighborhood of for which the generation frequency is high and then the code is stored in the transmission data buffer circuit 5. The transmission data buffer circuit 5 outputs the 0 accumulated datum as the encoded signal S6 to a transmission line. The threshold generating circuit 9 monitors the accumulated amount of the transmission data buffer circuit 5 and further controls the generation amount of the encoded data by generating an appropriate threshold value.

Next, the operation on the reception side will be described with reference to FIG. 3. The receiving data 7- 1 buffer circuit 13 first receives the encoded signal S 6 undergone the variable length encoding on the transmission signal and outputs the signal S 6 to the variable length decoder 14. Only when the movement detection signal S 3 undergone the decoding operation indicates the validness, the variable length decoder 14 outputs the reproduced quantization signal',S 11 If the movement detection signal S3 indicates the invalidness, the variable length decoder 14 outputs Next, the local decoding circuit 15 decodes the reproduced quantization signal Sl11 and outputs the reproduced diffrenialsignal S 1 to the adder 16. The adder 16 adds the reproduced differential signal S 1 to the reproduced estimation signal S 13 from the estimation circuit 17 thereby to reproduce the input signal S 1 4 The operation to effect the data compression and transmission by use of the differential signal is a~ 4 referred to as the differential pulse code modulation (to be abbreviated as DPCM herebelow) system.

However, in the image encoding/transmitting apparatus using the DPCM system, the variable length encoding is achieved on the datum~ which is judged to be effective at the step of the variable length encoding; consequently, as the threshold. value increases, the code having a short code length to be assigned in the neighborhood of "0" cannot be generated and hence the efficiency of the encoding is deteriorated; moreover, there has been a 8 -ft problem that as the threshold value becomes greater, the precision of the quantization is not improved for the quantization characteristic of the quantization circuit in the circuitry on the transmission side even when the dynamic range of the effective datum is narrowed.

SUMMARY OF THE INVENTION i It is an object of the present invention to provide an image encoding/transmitting apparatus and a method thereof in which input vectors of a plurality of pixel (pixel means a picture element.) signals can be simultaneously subjected to a quantization processing by a single circuit which achieves a function equivalent to that of a plurality of stages of circuits for the same input vector, thereby miniaturising the circuit.

15 According to one aspect of the invention, there is provided an image encoding/transmitting apparatus 0 0 Sincluding a vector quantizer wherein said vector quantizer ''tC comprises: a quantization preprocessing circuit for 00 0 a 20 subsampling an image signal to thin out pixels from the image signal according to a pixel ratio, and for generating a minimized resultant n-dimensional input vector; a group of input buffers for respectively storing each said input vector in a sequence of a quantization processing and fcr repetitiously reading the input vector at an i.nterval of the processing period; 9a vector output circuit for beforehand preparing an output vector corresponding to a probability distribution of the input vector and for selecting and outputting the output vector based on an index input; a distortion computation circuit for computing a distance between the input vector and the output vector selected and output; 0 0 0 0 a plurality of encoding sections disposed to o O correspond to the buffers; 0 o0 1 0 index output generating means for generating an 00.00 0 0 oooo index for a period of a subsequent processing based on the mo calculated distance value outputted from said each encoding section and the input vector, and for sending the oo°°o index to each said vector output circuit; and oooo 0000 00 15 a quantized index output circuit for generating 00 0 an index of the vector quantizer from said generated index 0o0 oo000and for outputting the index.

BRIEF DESCRIPTION OF THE DRAWINGS 00 0 0000 In order that the invention can be more clearly 00 0 0 0 0 00 20 understood, a preferred embodiment will now be described with reference to the accompanying drawings, wherein: FIG. 1 is a block diagram showing the configuration on the transmission side of the prior art image encoding/transmitting apparatus utilizing the DPCM system; 10 FIG. 2A is a block diagram illustrating a detailed configuration of the movement detecting circ'mi.t of FIG. 1, FIG. 2B is a block diagram illustrating a detailed configuration of the variable-length encode circuit 4, FIG. 2C is a schematic diagram illustrating an example of the multiplexing of the circuit of FIG. 1; FIG. 3A is a block configuration diagram depicting the reception side of the prior art image encoding/transmitting apparatus, FIG. 3B is a block 10 diagram showing the details of the variable-length decode 0 0 circuit of FIG. 3A; FIG. 4 is a block configuration diagram depicting the prior art encoding section in each stage of a general vector quantizer; t FIG. 5 is a schematic block diagram depicting 15 the overall constitution of the vector quantizer of FIG.

0o 0 4; FIG. 6A is a schematic block diagram depicting the overall constitution of the vector quantizer in the 00 0 0 0 0 S0 20 image encoding/transmitting apparatus of the embodiment associated with the vector quantizer of FIGS. 4 according to the present invention, FIG. 6B is a block diagram illustrating in detail the history circuit 314 of FIG. 6A; FIG. 7 is an explanatory diagram showing blocks of the vector quantizer of FIG. 6A; 11 Sl 't^HT"

L

0.

000* 0 5 elq FIGS. 8(a) 8(g) are explanatory diagrams illustrating the indices in the embodiment; FIGS. 9(a) 9(d) are explanatory diagrams showing a state in which pixels are thinned out from the results of the subsampling on the image signals, FIGS.

9(a) 9(e) are explanatory diagrams showing a method for reading an input vector from each buffer, FIG. 9C is an explanatory diagram for explaining the details of the additional buffer; 10 FIG. 10 is a timing chart illustrating output waveforms of the respective sections of the history circuit.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Prior to describing an embodiment of the present 15 invention, a description will be given of the technology adopted as the basis of the embodiment and of the outline thereof.

The embodiment relates to a vector quantizer for encoding image signals with a high efficiency, and in .,ticular, to a miniturized vector quantizer.

I I 00 oe I 12 ii oa oq 0 O 0 0 FIG. 4 shows the technology as the basis of the embodiment. This diagram illustrates a block diagram of the n-th stage of th~ vector quantizer. As shown in FIG. 5 the vector quantizer includes a multi-stage connection of a plurality of stages.

In FIG. 4, reference numeral 31 is a vector output circuit, reference numeral 32 indicates an input index, .reference numerals 33a 33b are distortion operating S circuits, reference numeral 34 designates an input 010 vector, reference numeral 35 indicates a comparator, S reference numerals 36a 36b denote distortions, reference numeral 37 is an index output circuit, reference numeral 38 indicates a delay circuit, reference numeral 39 stands for an output vector, reference numeral *15 310 denotes an output index, and reference numeral 311 designates a quantizer output index. The encoding S section 320 comprises the respective circuits above.

Incidentally, reference numeral 321 in this diagram indicates the encoder at the final stage.

420 Next, the operation of this configuration will be described. When the input index 32 is received, the vector output circuits 31a 31b select output vectors from a group of output vectors beforehand prepared (code book) corresponding to the input index and then deliver the output vectors. The respective output vectors are supplied to the distortion computation circuits 33a 33b, which calculate the distortions (distances) with 00 0 0 4 4 4 o 0 0 0( '44~ 4 i 0 13

(I

respect to the input vector sent from the input buffer 312. The distortions 36a 36b outputted as a result of the computation from the respective distortion computation circuits 33a 33b are fed to the comparator 35, which effects a comparison therebetween. For the distortion 36a the distortion 36b, is output; 0° o whereas for the distortion 36a the distortion 36b, "1" 0n 00 o 0 0° is output. Next, the distortion compare value is output o 0 0o °o together with the index 32 from the index output circuit 0o 00 0 :010 37 to the encoding section 320 of the next stage so as to ooo0 0000 be used to generate a new input index. The input vector 34 to be subjected to the distortion computation at the next stage is sent via the delay circuit 38 to the 0000 0 0 0 00 0 encoding section 320 of the subsequent stage, so that o0 0 a 0 the distortion is computated with respect to the output 0, 0 vector selected and output by use of the new input index.

The distor' on computation is continuously repeated up to o° 0 the encoding section 321 of the final stage so as to o0a minimize the total of the distortion through a conversion, thereby generating the final quantizer output index 311.

In FIG. 5, the input vector and the input index to each encoding section 320 are respectively the output vector 39 and the output index 310 from an encoding section 320 of the previous stage. For the encoding section 321 at the final stage (the 10-th stage in this case), since there does not exist the encoding section 320 of the succeeding stage as compared with the encoding 14 in which a plurality of samples of the image signals are grouped in blocks and each block thereof is mapped onto a pattern most similar thereto in a 1A I I id ,4 Al;n~ Llly~ sections 320 of from the first to the ninth stages, the delay circuit 38 is not required. The output index from the final stage is delivered as the quantizer output index 311.

As shown in FIGS. 4 5 the prior art vector quantizer is configured such that the input vector (input datum) and the input index for selecting an output vector are sequentially transmitted to the next encoding section 320 while updating the input index in each encoding section 320 so as to generate the quantizer output index in the final encoding section 321, which consequently leads to problems that the size of the circuitry is increased and that the idle time or the wait tine occurs in the encoding sections and hence the overall circuitry cannot be effectively utilized.

According to the vector quantizer of the embodiment, there is provided a quantization index output circuit in which the input image signal is subsampled in the quantization preprocessing circuit to thin out pixels, the respective pixel signals are used to form an n-dimensional input vector, and each input vector is st6red in the input buffer corresponding to each pixel signal; furthermore, the input vector is supplied to the encoding section corresponding to the input buffer at an interval of the processing period, The encoding section calculates the distortion between the input vector and the output vector updated at an interval of the processing j

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15 *JoRur~~asa~-~~ liPI 0 0o 0 0 0 0 00 00 00 0 0 0 0 0 00 o0 0 009 0 00000 0 0 0000 0 0004 period. Based on the distortion, the input index generating means generates a new input index for selecting the output vector, and based on the input index, the quantizer output index is generated and is output from a quantization index output circuit.

Next, the embodiment of the present invention will be described with reference to the drawings.

FIG. 6 A is a schematic block diagram depicting the entire configuration of the embodiment in which 10 reference numeral 316 denotes an input image, reference numeral 317 is an quantization preprocessing circuit, reference numerals 311a 31b designate vector output circuits for outputting vectors corresponding to the input index 32, reference numerals 33a 33b indicate 15 distortion computation circuits for respectively calculating the distortion between the'input vector 34 and the vectors delivered from the vector output circuits 31a 31b, reference numeral 35 denotes a comparator, reference numeral 36a stands for a distortion outputted from a circuit equivalent to the distortion computation circuit 33a in the encoding section 313a and the distortion computation circuit 33a in the respective encoding sections 313b, 313c, and 313d, reference numeral 36b designates a distortion outputted from a circuit equivalent to the distortion computation circuit 33b in the encoding section 313a and the distortion computation circuit 33b in the respective encoding 0 0 0 00 0 0 0 0 0 00 0000 0 0 0 00 0 0 0 0 0 I 16

L~.

I*

-lp c ~e sections 313b, 313c, and 313d, reference numeral 37 indicates an index output circuit, reference numeral 311 represents a quantizer output index of the vector quantizer, reference numerals 312a, 312b, 312c, and 312d are input buffers for storing the blocks A, B, H obtained by dividing the input vector 34 as shown in FIG. 7 reference numerals 313a, 313b, 313c, and 313d denote encoding sections, reference numerals 314a, 314b, 314c, and 314d indicate history circuits for outputting indices for the blocks of A, B, H, and reference numeral 315 denotes a quantization index output circuit for outputting the index of the vector quantizer circuit associated with the input vector. As shown in FIG. 6&B, the history circuits 314a 314d each comprise a first 15 flip-flop circuit 601 for receiving an output from the output index circuit 37, a second flip-flop circuit 602 for the same purpose, an output control circuit 603, a third flip-flop circuit 604 for receiving the respective outputs from the first and second flip-flop circuits 601 602, and a pattern comparing circuit 605 for delivering a history signal to the encoder 313a based on the output from the third flip-flop circuit 604. The pattern comparing circuit 605 is constituted, for example, from a code book. FIG. 7 shows a block attained by dividing the image of the embodiment in which A H indicate subblocks. The input buffers 312a 312d respectively store subblocks A B, C D, E F, and 17 r G H. The embodiment has been described with reference to a vector quantizer including ten stages. FIGS.

8 8(g) show the indices and quantizer output index 311 to be output from the index output circuit 37 at each stage.

Next, the operation of the embodiment will be described. The image 316 supplied to the system is thinned out in the quantization preprocessing circuit 317. (Refer to FIG. 9 for details.) Before the input S 10 vector 34 is supplied to the vector quantizer, the blocks A B, C D, E F, and G H of FIG. 7 are respectively written in the buffers 312a 312d.

Thereafter, the image data is read as blocks of A B, C D, E F, and G H in parallel from the associated buffers 312a 312d, respectively, and the vector quantization is accomplished by executing the read operation ten times for each block. (Refer to FIG. for details.) However, prior to the operation above, the vectors read from the buffers 312a, 312b, 312c, and 312d are respectively supplied to the distortion computation circuits 33a and 33b. The buffers 312a 312d are added to effect a concurrent processing by separating the input serial data into four data groups.

The details of these buffers 312a 312d are shown in FIG. 9 C.

Furthermore, the vectors output from the vector output circuits 31a 31b according to the input index 18 i. i ii r i; ii-ii i i i Il-ilil_ l i _i 32 are also delivered to the distortion computation circuits 33a 33b. The distortion computation circuits 33a 33b calculate the distortions between the vectors input from the input buffers 312a 312d and the vectors output from +hc vector output circuits 31a 31b, respectively. In this operation, to prevent the distortions from being delivered from the encoding sections 313a 313d to the comparator 35 at the same time, the distortions are output therefrom in the i10 sequence of encoding sections as 313a, 313b, 313c, and 313d. Next, the distortions are input to the comparator and is output from the comparator if the distortion 36a is less than the distortion 36b; otherwise, is output. Based on the output from the comparator 35 and the index previously supplied, the index circuit 37 outputs a new index. 'From the history circuits 314a 314d, the indices of the vectors of the *r .respective blocks A B, C D, E F, and G H are output to the vector output circuit for the next 2' 20 distortion computation. In addition, the indices are also output to the index output circuit 37 to attain 'he next new index. This operation is repetitiously executed from the first stage to the tenth stage, and the index delivered from the last operation at the tenth stage is output as the vector quantizer index from the quantization index output circuit 315. The output waveforms at the respective sections described in 19 r-i 1 I ft rr. 0 *0 0 0 a 0 00a S 0 0 0 00 0 a 00 000 i 0 a I 0000 conjunction with FIG. 6 B of the history circuits 314a 314d are as shown in FIG. As described above, according to the embodiment, the input image is subsampled, the pixels are subjected to the thinning-out operation, and the n-dimensional input vector to be shaped is minimized.

Thereafter, for the input vectors of the same image, the distortion operation is repetitiously executed by the same distortion operation circuit to converge the total 10 of the distortions, thereby minimizing the resultant value of the total. For other vectors, the distortions are concurrently calculated by the respective distortion operation circuits, and based on the distortions, the quantizer index is generated for each pixel signal; 15 consequently, the size of the circuitry can be miniaturized and the entire circuitry can be efficiently operated without idle operations.

00*0 0 0 04 001 0 0 00 4I~ 4 0 i 4 0 20

Claims (2)

1. An image encoding/transmitting apparatus including a vector quantizer wherein said vector quantizer compri ,es: a quantization preprocessing circuit for subsampling an image signal to thin out pixels from the image signal according to a pixel ratio, and for 0 0 generating a minimized resultant n-dimensional input vector; [a group of input buffers for respectively storing each said input vector in a sequence of a quantization processing and for repetitiously reading the input vector at an interval of the processing period.; a vector output circuit for beforehand preparing S' an output vector corresponding to a probability distribution of the input vector and for selecting and outputting the output vector based on an index input; a distortion computation circuit for computing a distance between the input vector and the output vector *selected and output; a plurality of encoding sections disposed to correspond to the buffers; index output generating means for generating an index for a period of a subsequent processing based on the calculated distance value outputted from said each encoding section and the input vector, and for sending the index to each said vector output circuit; and a quantized index output circuit for generating 21 1 an index of the vector quantizer from said generated index and for outputting the index.

2. An image encoding/transmitting apparatus as claimed in claim 1, and substantially as herein described with reference to any one of the examples shown in Figures 6 to 10 of the accompanying drawings. DATED THIS 26TH DAY OF OCTOBER, 1990 MITSUBISHI DENKI KABUSHIKI KAISHA By Its Patent Attorneys GRIFFITH HACK CO. Fellows Institute of Patent Attorneys of Australia 22 -i jjb;. /k