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AU585546B2 - Circuit arrangement for regenerating and synchronizing a digital signal - Google Patents

Circuit arrangement for regenerating and synchronizing a digital signal

Info

Publication number
AU585546B2
AU585546B2 AU49285/85A AU4928585A AU585546B2 AU 585546 B2 AU585546 B2 AU 585546B2 AU 49285/85 A AU49285/85 A AU 49285/85A AU 4928585 A AU4928585 A AU 4928585A AU 585546 B2 AU585546 B2 AU 585546B2
Authority
AU
Australia
Prior art keywords
regenerating
synchronizing
digital signal
circuit arrangement
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU49285/85A
Other versions
AU4928585A (en
Inventor
Michael Klein
Joachim Wolk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent NV
Original Assignee
Alcatel NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel NV filed Critical Alcatel NV
Publication of AU4928585A publication Critical patent/AU4928585A/en
Application granted granted Critical
Publication of AU585546B2 publication Critical patent/AU585546B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/24—Systems for the transmission of television signals using pulse code modulation
    • H04N7/52—Systems for transmission of a pulse code modulated video signal with one or more other pulse code modulated signals, e.g. an audio signal or a synchronizing signal
    • H04N7/54—Systems for transmission of a pulse code modulated video signal with one or more other pulse code modulated signals, e.g. an audio signal or a synchronizing signal the signals being synchronous
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Multimedia (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Pulse Circuits (AREA)
AU49285/85A 1984-11-14 1985-11-01 Circuit arrangement for regenerating and synchronizing a digital signal Ceased AU585546B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19843441501 DE3441501A1 (en) 1984-11-14 1984-11-14 Circuit arrangement for regenerating and synchronising a digital signal
DE3441501 1984-11-14

Publications (2)

Publication Number Publication Date
AU4928585A AU4928585A (en) 1986-05-22
AU585546B2 true AU585546B2 (en) 1989-06-22

Family

ID=6250211

Family Applications (1)

Application Number Title Priority Date Filing Date
AU49285/85A Ceased AU585546B2 (en) 1984-11-14 1985-11-01 Circuit arrangement for regenerating and synchronizing a digital signal

Country Status (2)

Country Link
AU (1) AU585546B2 (en)
DE (1) DE3441501A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU617312B2 (en) * 1988-03-26 1991-11-28 Alcatel N.V. Synchronizing circuit

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3510566A1 (en) * 1985-03-23 1986-10-02 Standard Elektrik Lorenz Ag, 7000 Stuttgart BROADBAND COUPLING BLOCK AND BROADBAND COUPLING
DE3543392A1 (en) * 1985-12-07 1987-06-25 Standard Elektrik Lorenz Ag CIRCUIT ARRANGEMENT FOR REGENERATING AND SYNCHRONIZING A DIGITAL SIGNAL
DE3702614A1 (en) * 1987-01-29 1988-08-11 Standard Elektrik Lorenz Ag DIGITAL COUPLING NETWORK FOR LINE AND PACKAGE SWITCHING AND COUPLING DEVICE TO THIS
EP0363513B1 (en) * 1988-10-13 1994-02-16 Siemens Aktiengesellschaft Method and apparatus for receiving a binary digital signal
US5146478A (en) * 1989-05-29 1992-09-08 Siemens Aktiengesellschaft Method and apparatus for receiving a binary digital signal
DE4037062C2 (en) * 1990-11-22 1996-05-23 Broadcast Television Syst Circuit arrangement for synchronizing an asynchronous data signal
DE69120244T2 (en) * 1991-03-05 1997-01-23 Alcatel Bell Nv Synchronization circuit
EP0562183A1 (en) * 1992-03-27 1993-09-29 ALCATEL BELL Naamloze Vennootschap Synchronization method and device realizing said method
DE4434803C1 (en) * 1994-09-29 1996-03-07 Ant Nachrichtentech Serial bit stream sampling method for high speed data transmission equipment
WO1996029794A1 (en) * 1995-03-23 1996-09-26 Siemens Aktiengesellschaft Digital phase-equalization circuit with delay device and identical transmission paths

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU525914B2 (en) * 1978-09-21 1982-12-09 Telefonaktiebolaget Lm Ericsson (Publ) Controlling phase of a signal

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2855724A1 (en) * 1978-12-22 1980-07-03 Ibm Deutschland METHOD AND DEVICE FOR ADJUSTING THE DIFFERENT SIGNAL DELAY TIMES OF SEMICONDUCTOR CHIPS
US4234850A (en) * 1979-01-08 1980-11-18 Optimizer Control Corporation Firing time control circuit
US4330862A (en) * 1980-07-09 1982-05-18 Bell Telephone Laboratories, Incorporated Signal characteristic state detector using interval-count processing method
JPS57152855U (en) * 1981-03-20 1982-09-25
DE3217050A1 (en) * 1982-05-06 1983-11-10 Siemens AG, 1000 Berlin und 8000 München Delay circuit for digital signals

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU525914B2 (en) * 1978-09-21 1982-12-09 Telefonaktiebolaget Lm Ericsson (Publ) Controlling phase of a signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU617312B2 (en) * 1988-03-26 1991-11-28 Alcatel N.V. Synchronizing circuit

Also Published As

Publication number Publication date
DE3441501A1 (en) 1986-05-15
AU4928585A (en) 1986-05-22

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