AU4848100A - Method and apparatus for loose register encoding within a pipelined processor - Google Patents

Method and apparatus for loose register encoding within a pipelined processor

Info

Publication number: AU4848100A
Authority: AU; Australia
Prior art keywords: pipelined processor; register encoding; loose; loose register; encoding
Prior art date: 1999-05-13
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Abandoned

Application number

AU48481/00A

Inventor

Carl Graham

Peter Warnes

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Arc International Us Holdings Inc

Original Assignee

ARC INTERNAT U S HOLDINGS Inc

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1999-05-13

Filing date

2000-05-12

Publication date

2000-12-05

1999-10-14 Priority claimed from US09/418,663 external-priority patent/US6862563B1/en

2000-05-12 Application filed by ARC INTERNAT U S HOLDINGS Inc filed Critical ARC INTERNAT U S HOLDINGS Inc

2000-12-05 Publication of AU4848100A publication Critical patent/AU4848100A/en

Status Abandoned legal-status Critical Current

Classifications

- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30156—Special purpose encoding of instructions, e.g. Gray coding
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Software Systems (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Computer Hardware Design (AREA)
Evolutionary Computation (AREA)
Geometry (AREA)
Executing Machine-Instructions (AREA)

AU48481/00A 1999-05-13 2000-05-12 Method and apparatus for loose register encoding within a pipelined processor Abandoned AU4848100A (en)

Applications Claiming Priority (7)

Application Number	Priority Date	Filing Date	Title
US13425399P	1999-05-13	1999-05-13
US60134253		1999-05-13
US09418663		1999-10-14
US09/418,663 US6862563B1 (en)	1998-10-14	1999-10-14	Method and apparatus for managing the configuration and functionality of a semiconductor design
US52417800A	2000-03-13	2000-03-13
US09524178		2000-03-13
PCT/US2000/013198 WO2000070446A2 (en)	1999-05-13	2000-05-12	Method and apparatus for loose register encoding within a pipelined processor

Publications (1)

Publication Number	Publication Date
AU4848100A true AU4848100A (en)	2000-12-05

Family

ID=27384546

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
AU48481/00A Abandoned AU4848100A (en)	1999-05-13	2000-05-12	Method and apparatus for loose register encoding within a pipelined processor

Country Status (5)

Country	Link
EP (1)	EP1194835A2 (en)
CN (2)	CN1198208C (en)
AU (1)	AU4848100A (en)
TW (1)	TW482978B (en)
WO (1)	WO2000070446A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US6862563B1 (en)	1998-10-14	2005-03-01	Arc International	Method and apparatus for managing the configuration and functionality of a semiconductor design
US6988154B2 (en)	2000-03-10	2006-01-17	Arc International	Memory interface and method of interfacing between functional entities
US7734898B2 (en)	2004-09-17	2010-06-08	Freescale Semiconductor, Inc.	System and method for specifying an immediate value in an instruction
US8127117B2 (en) *	2006-05-10	2012-02-28	Qualcomm Incorporated	Method and system to combine corresponding half word units from multiple register units within a microprocessor
US8127113B1 (en)	2006-12-01	2012-02-28	Synopsys, Inc.	Generating hardware accelerators and processor offloads
GB2461849A (en) *	2008-07-10	2010-01-20	Cambridge Consultants	Push immediate instruction with several operands
US9836235B2 (en)	2014-05-07	2017-12-05	Marvell World Trade Ltd.	Low power distributed memory network
GB2569098B (en) *	2017-10-20	2020-01-08	Graphcore Ltd	Combining states of multiple threads in a multi-threaded processor
CN113656071B (en) *	2021-10-18	2022-02-08	深圳市智想科技有限公司	RISC architecture based CPU instruction set system and CPU system

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPH04172533A (en) *	1990-11-07	1992-06-19	Toshiba Corp	Electronic computer
EP0871108B1 (en) *	1991-03-11	2000-09-13	MIPS Technologies, Inc.	Backward-compatible computer architecture with extended word size and address space
AU5550194A (en) *	1993-09-27	1995-04-18	Giga Operations Corporation	Implementation of a selected instruction set cpu in programmable hardware
US5509129A (en) *	1993-11-30	1996-04-16	Guttag; Karl M.	Long instruction word controlling plural independent processor operations
JP3452989B2 (en) *	1994-09-26	2003-10-06	三菱電機株式会社	Central processing unit
CN1187255A (en) *	1995-06-07	1998-07-08	高级微型器件公司	Microprocessors that specify extended functionality using instruction fields
SE505783C2 (en) *	1995-10-03	1997-10-06	Ericsson Telefon Ab L M	Method of manufacturing a digital signal processor
GB2309803B (en) *	1996-02-01	2000-01-26	Advanced Risc Mach Ltd	Processing cycle control in a data processing apparatus
JP3706633B2 (en) *	1996-05-15	2005-10-12	トリメディアテクノロジーズインコーポレイテッド	Processor with instruction cache
GB2317464A (en) *	1996-09-23	1998-03-25	Advanced Risc Mach Ltd	Register addressing in a data processing apparatus
US5890008A (en) *	1997-06-25	1999-03-30	Sun Microsystems, Inc.	Method for dynamically reconfiguring a processor

2000
- 2000-05-12 CN CNB008084629A patent/CN1198208C/en not_active Expired - Fee Related
- 2000-05-12 CN CNB2005100535515A patent/CN100351782C/en not_active Expired - Lifetime
- 2000-05-12 AU AU48481/00A patent/AU4848100A/en not_active Abandoned
- 2000-05-12 WO PCT/US2000/013198 patent/WO2000070446A2/en not_active Ceased
- 2000-05-12 EP EP00930707A patent/EP1194835A2/en not_active Withdrawn
- 2000-07-05 TW TW089109199A patent/TW482978B/en not_active IP Right Cessation

Also Published As

Publication number	Publication date
CN1198208C (en)	2005-04-20
WO2000070446A2 (en)	2000-11-23
CN100351782C (en)	2007-11-28
CN1661547A (en)	2005-08-31
CN1384934A (en)	2002-12-11
TW482978B (en)	2002-04-11
WO2000070446A3 (en)	2002-02-07
EP1194835A2 (en)	2002-04-10

Publication	Publication Date	Title
AUPQ055999A0 (en)	1999-06-17	A method and apparatus (npage01)
AU2001238486A1 (en)	2001-08-27	Method and apparatus for conducting or facilitating a promotion
AU2001271847A1 (en)	2002-01-21	Method and apparatus for enhancing data resolution
AU3246700A (en)	2000-09-21	System and method for number portability
AU2001279208A1 (en)	2002-02-18	Methods and apparatus for enhancing digital signal processors
AU2387400A (en)	2000-07-24	A method and apparatus for improved predicate prediction
IL131800A (en)	2003-02-12	Apparatus for software initiated prefetch and method therefor
AU2002231358A1 (en)	2002-06-03	Method and apparatus for scheduling multiple micro-operations in a processor
AU4478600A (en)	2000-11-10	Method and apparatus for testing a well
AUPP248498A0 (en)	1998-04-23	A method and apparatus for encoding and decoding an image
AUPP868899A0 (en)	1999-03-11	A method and apparatus(IJ46P1C)
AU2636000A (en)	2000-08-18	Method and apparatus for digital printing
AUPP868799A0 (en)	1999-03-11	A method and apparatus(IJ46P1B)
GB2348585B (en)	2003-12-24	Method and apparatus for watermarking digital data
GB2374698B (en)	2003-12-24	Method and apparatus for constructing a pre-scheduled instruction cache
AU2001227007A1 (en)	2001-07-24	A processing method and apparatus
AU2001245511A1 (en)	2001-09-24	Method and apparatus for enhancing the performance of a pipelined data processor
AU4848100A (en)	2000-12-05	Method and apparatus for loose register encoding within a pipelined processor
AU2002357662A1 (en)	2003-04-28	A method and apparatus to improve an mri image
GB2360103B (en)	2002-08-21	System and method for providing a computer system with a detachable component
AU2001266231A1 (en)	2002-01-14	Apparatus and method for licensing digital data
AU2881000A (en)	2000-08-29	Method and apparatus for preprocessing for peripheral erroneous data
GB9903801D0 (en)	1999-04-14	Method and apparatus for encoding data
AUPP868999A0 (en)	1999-03-11	A method and apparatus(IJ46P1D)
GB9921261D0 (en)	1999-11-10	Method and apparatus for processing a digital bitstream

Legal Events

Date	Code	Title	Description
2002-03-21	MK6	Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase