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AU4279793A - Self-controlled write back cache memory apparatus - Google Patents

Self-controlled write back cache memory apparatus

Info

Publication number
AU4279793A
AU4279793A AU42797/93A AU4279793A AU4279793A AU 4279793 A AU4279793 A AU 4279793A AU 42797/93 A AU42797/93 A AU 42797/93A AU 4279793 A AU4279793 A AU 4279793A AU 4279793 A AU4279793 A AU 4279793A
Authority
AU
Australia
Prior art keywords
self
cache memory
memory apparatus
write back
back cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU42797/93A
Inventor
Tim Y. T Lau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
VTECH COMPUTERS Inc
Video Tech Computers Ltd
Original Assignee
VTECH COMPUTERS Inc
Video Tech Computers Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by VTECH COMPUTERS Inc, Video Tech Computers Ltd filed Critical VTECH COMPUTERS Inc
Publication of AU4279793A publication Critical patent/AU4279793A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU42797/93A 1992-04-07 1993-04-06 Self-controlled write back cache memory apparatus Abandoned AU4279793A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US86453592A 1992-04-07 1992-04-07
US864535 2001-05-24

Publications (1)

Publication Number Publication Date
AU4279793A true AU4279793A (en) 1993-11-08

Family

ID=25343486

Family Applications (1)

Application Number Title Priority Date Filing Date
AU42797/93A Abandoned AU4279793A (en) 1992-04-07 1993-04-06 Self-controlled write back cache memory apparatus

Country Status (2)

Country Link
AU (1) AU4279793A (en)
WO (1) WO1993020514A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220188228A1 (en) * 2021-12-22 2022-06-16 Intel Corporation Cache evictions management in a two level memory controller mode

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4942518A (en) * 1984-06-20 1990-07-17 Convex Computer Corporation Cache store bypass for computer
US4926317A (en) * 1987-07-24 1990-05-15 Convex Computer Corporation Hierarchical memory system with logical cache, physical cache, and address translation unit for generating a sequence of physical addresses
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US4995041A (en) * 1989-02-03 1991-02-19 Digital Equipment Corporation Write back buffer with error correcting capabilities
US5197144A (en) * 1990-02-26 1993-03-23 Motorola, Inc. Data processor for reloading deferred pushes in a copy-back data cache

Also Published As

Publication number Publication date
WO1993020514A1 (en) 1993-10-14

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