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AU4002095A - Simultaneous processing by multiple components - Google Patents

Simultaneous processing by multiple components

Info

Publication number
AU4002095A
AU4002095A AU40020/95A AU4002095A AU4002095A AU 4002095 A AU4002095 A AU 4002095A AU 40020/95 A AU40020/95 A AU 40020/95A AU 4002095 A AU4002095 A AU 4002095A AU 4002095 A AU4002095 A AU 4002095A
Authority
AU
Australia
Prior art keywords
multiple components
simultaneous processing
simultaneous
processing
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU40020/95A
Inventor
Hitoshi Yoshimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FLAMEPOINT Inc
Original Assignee
FLAMEPOINT Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by FLAMEPOINT Inc filed Critical FLAMEPOINT Inc
Publication of AU4002095A publication Critical patent/AU4002095A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
AU40020/95A 1994-10-26 1995-10-13 Simultaneous processing by multiple components Abandoned AU4002095A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US329707 1981-12-11
US32970794A 1994-10-26 1994-10-26
PCT/US1995/013309 WO1996013775A1 (en) 1994-10-26 1995-10-13 Simultaneous processing by multiple components

Publications (1)

Publication Number Publication Date
AU4002095A true AU4002095A (en) 1996-05-23

Family

ID=23286639

Family Applications (1)

Application Number Title Priority Date Filing Date
AU40020/95A Abandoned AU4002095A (en) 1994-10-26 1995-10-13 Simultaneous processing by multiple components

Country Status (3)

Country Link
AU (1) AU4002095A (en)
CA (1) CA2203378A1 (en)
WO (1) WO1996013775A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5941968A (en) * 1997-04-14 1999-08-24 Advanced Micro Devices, Inc. Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU and expansion bus device
US6057862A (en) * 1997-07-01 2000-05-02 Memtrax Llc Computer system having a common display memory and main memory
US6118462A (en) 1997-07-01 2000-09-12 Memtrax Llc Computer system controller having internal memory and external memory control
JP3524337B2 (en) 1997-07-25 2004-05-10 キヤノン株式会社 Bus management device and control device for multifunction device having the same
US6381247B1 (en) * 1998-12-17 2002-04-30 Nortel Networks Limited Service independent switch interface
DE19936080A1 (en) * 1999-07-30 2001-02-15 Siemens Ag Multiprocessor system for performing memory accesses to a shared memory and associated method
US6950893B2 (en) 2001-03-22 2005-09-27 I-Bus Corporation Hybrid switching architecture

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5067071A (en) * 1985-02-27 1991-11-19 Encore Computer Corporation Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus
US5339396A (en) * 1987-11-18 1994-08-16 Hitachi, Ltd. Interconnection network and crossbar switch for the same
US4979100A (en) * 1988-04-01 1990-12-18 Sprint International Communications Corp. Communication processor for a packet-switched network
US5163131A (en) * 1989-09-08 1992-11-10 Auspex Systems, Inc. Parallel i/o network file server architecture
US5226125A (en) * 1989-11-17 1993-07-06 Keith Balmer Switch matrix having integrated crosspoint logic and method of operation

Also Published As

Publication number Publication date
CA2203378A1 (en) 1996-05-09
WO1996013775A1 (en) 1996-05-09

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