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AU3869000A - Methods to produce robust multilayer circuitry for electronic packaging - Google Patents

Methods to produce robust multilayer circuitry for electronic packaging

Info

Publication number
AU3869000A
AU3869000A AU38690/00A AU3869000A AU3869000A AU 3869000 A AU3869000 A AU 3869000A AU 38690/00 A AU38690/00 A AU 38690/00A AU 3869000 A AU3869000 A AU 3869000A AU 3869000 A AU3869000 A AU 3869000A
Authority
AU
Australia
Prior art keywords
methods
electronic packaging
produce robust
multilayer circuitry
robust multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU38690/00A
Inventor
Daniel E. Baxter
Samuel Fu
Pradeep Gandhi
Gary E. Legerton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ormet Corp
Original Assignee
Ormet Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ormet Corp filed Critical Ormet Corp
Publication of AU3869000A publication Critical patent/AU3869000A/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0562Details of resist
    • H05K2203/0574Stacked resist layers used for different processes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703Plating
    • H05K2203/0733Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
AU38690/00A 1999-04-01 2000-03-06 Methods to produce robust multilayer circuitry for electronic packaging Abandoned AU3869000A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US28366099A 1999-04-01 1999-04-01
US09283660 1999-04-01
PCT/US2000/005821 WO2000059645A1 (en) 1999-04-01 2000-03-06 Methods to produce robust multilayer circuitry for electronic packaging

Publications (1)

Publication Number Publication Date
AU3869000A true AU3869000A (en) 2000-10-23

Family

ID=23087025

Family Applications (1)

Application Number Title Priority Date Filing Date
AU38690/00A Abandoned AU3869000A (en) 1999-04-01 2000-03-06 Methods to produce robust multilayer circuitry for electronic packaging

Country Status (2)

Country Link
AU (1) AU3869000A (en)
WO (1) WO2000059645A1 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7059948B2 (en) 2000-12-22 2006-06-13 Applied Materials Articles for polishing semiconductor substrates
US6887776B2 (en) 2003-04-11 2005-05-03 Applied Materials, Inc. Methods to form metal lines using selective electrochemical deposition
US8221518B2 (en) 2009-04-02 2012-07-17 Ormet Circuits, Inc. Conductive compositions containing blended alloy fillers
US8840700B2 (en) 2009-11-05 2014-09-23 Ormet Circuits, Inc. Preparation of metallurgic network compositions and methods of use thereof
US9583453B2 (en) 2012-05-30 2017-02-28 Ormet Circuits, Inc. Semiconductor packaging containing sintering die-attach material
US12053934B2 (en) 2012-06-18 2024-08-06 Ormet Circuits, Inc. Conductive film adhesive
US9005330B2 (en) 2012-08-09 2015-04-14 Ormet Circuits, Inc. Electrically conductive compositions comprising non-eutectic solder alloys
US11440142B2 (en) 2012-11-16 2022-09-13 Ormet Circuits, Inc. Alternative compositions for high temperature soldering applications
US10446412B2 (en) 2015-04-13 2019-10-15 Printcb Ltd. Printing of multi-layer circuits
CN112166653A (en) 2018-03-15 2021-01-01 以色列商普林特电路板有限公司 Two-component printable conductive composition
US11432402B2 (en) * 2018-10-11 2022-08-30 Microchip Technology Caldicot Limited Flipped-conductor-patch lamination for ultra fine-line substrate creation
JPWO2020179874A1 (en) * 2019-03-06 2020-09-10

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3433251A1 (en) * 1984-08-16 1986-02-27 Robert Bosch Gmbh, 7000 Stuttgart METHOD FOR PRODUCING GALVANIC SOLDER LAYERS ON INORGANIC SUBSTRATES
US5716663A (en) * 1990-02-09 1998-02-10 Toranaga Technologies Multilayer printed circuit
JP2665134B2 (en) * 1993-09-03 1997-10-22 日本黒鉛工業株式会社 Flexible circuit board and method of manufacturing the same
US5922397A (en) * 1997-03-03 1999-07-13 Ormet Corporation Metal-plating of cured and sintered transient liquid phase sintering pastes
US6068782A (en) * 1998-02-11 2000-05-30 Ormet Corporation Individual embedded capacitors for laminated printed circuit boards

Also Published As

Publication number Publication date
WO2000059645A1 (en) 2000-10-12

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase