AU2776602A - Delay profile measurement for a spread spectrum receiver - Google Patents

Description

P/00/011 Regulation 3.2

AUSTRALIA

Patents Act 1990

ORIGINAL

COMPLETE SPECIFICATION STANDARD PATENT Invention Title: Delay profile measurement for a spread spectrum receiver The following statement is a full description of this invention, including the best method of performing it known to us: rreeniiis liarter Smith ~eadIe Melbourne\004023105 Printed 27 March 2002 (14:57) Freehills Carter Smith Beadle Melbourne\004023105 Printed 27 March 2002 (14:57) DELAY PROFILE MEASUREMENT FOR A SPREAD SPECTRUM RECEIVER The present invention relates to wireless communications, and in particular to determining delay profiles for radio frequency signals in a spread spectrum receiver.

When a radio frequency (RF) signal is sent to a wideband code-division multipleaccess (W-CDMA) receiver in a W-CDMA telecommunications network, the receiver may receive multiple versions of the signal, each shifted in time relative to the others, due to reflections of the transmitted signal from objects (multipath signals), and/or reception of signals transmitted from a number of unsynchronised transmitters. The latter is important a mobile W-CDMA digital telephone moves from one cell to another, and a handover process is performed whereby the telephone switches from one transmitter to another. W-CDMA telephone systems include circuitry that enables them to detect a 15 number of versions of the signal, and to process them so that they may be combined. The circuitry includes a delay profile circuit to determine a profile of the correlation between the measured control channel signal and the signal scrambling code as a function of the time shift between signal and the scrambling code. This profile is then processed by a rake S•finger control circuit that searches the profile data for correlation peaks indicating likely time delays, and provides these to the fingers of a RAKE receiver, each of which performs a correlation on the data using the scrambling code time-aligned in accordance with the provided time delay. Thus each finger determines a despread signal, and these despread signals are then combined to improve the signal-to-noise ratio.

Current implementations of the delay profile circuit require a large number of logic gates and consume a significant amount of power, a precious commodity in mobile telephones. It is desired, therefore, to provide a method and system for determining signal delay profiles using a small number of logic gates and with low power consumption, or at least provide a useful alternative to current delay profile circuits.

It would also be desirable to provide a method and system of determining signal delay profiles for radio frequency signals in a spread spectrum receiver that ameliorates or overcomes one or more problems of the prior art.

Freehills Carter Smith Beadle Melbourne\004021426 Printed 25 March 2002 (16:39) In accordance with one aspect of the present invention there is provided a method for determining a plurality of signal delay profiles in a mobile telephone apparatus, including: storing sampled signal data in a region of memory, said signal data comprising signal data from a plurality of radio links or branches: determining timing data for each of said plurality of radio links or branches; sequentially determining correlation data for each of said plurality of radio links or branches, said correlation data determined for a plurality of delay values based on said timing data and said sampled signal data; and each of said plurality of radio links or branches, determining a signal delay profile based on said correlation data, and said delay values.

Preferably, said method includes determining, for each of said plurality of radio links or branches, an address within said region of memory based on said timing data, said address identifying the corresponding radio links or branches. Preferably, said method also includes concurrently determining scrambling codes for each of said radio links or branches, said scrambling codes synchronised with said timing data for the corresponding link or branch, and storing said address and the state of each scrambling code in response 20 to the timing data for the corresponding radio link or branch.

:eo••Q Preferably, said correlation data for all radio links or branches is determined by a single correlator bank, said correlation data for each radio link or branch based on said stored address and scrambling code state.

Preferably, said step of storing sampled signal data includes monitoring said signal data for frame boundaries and restarting said step if a frame boundary is detected.

Preferably, said correlation data for each radio link or branch is normalised by bit shifting said data and determining a single exponent value for said data.

Freehills Carter Smith Beadle Melbourne\004021426 Printed 25 March 2002 (16:39) 4 Preferably, said step of storing sampled signal data includes storing selected samples of said data, and said step of determining a delay profile includes compensating for unselected samples by interpolation.

Preferably, said method includes accumulation of in-phase symbols to reduce noise.

Preferably, said method includes weighting correlation values based on gain data to compensate for variations in signal strength.

In accordance with another aspect of the invention, there is provided a delay profile measurement device for use in a mobile telephone apparatus, the delay profile oooo measurement device including a processing unit and a memory device, operatively oo connected to the processing unit, for storing program instructions to cause the processing unit to carry out a method as described above.

A preferred embodiment of the present invention is hereinafter described, by way of example only, with reference to the accompanying drawings, wherein: Figure 1 is a block diagram of a preferred embodiment of a W-CDMA telephone receiver; Figure 2 is a schematic diagram illustrating 3GPP CPICH pilot patterns for two antennae and the two exceptions to the orthogonality between 4-symbol antenna pilot patterns; Figure 3 is a block diagram of a preferred embodiment of a delay profile device; Figure 4 is a schematic timing diagram illustrating branch signal processing by the delay profile device; Figure 5 is a schematic timing diagram illustrating frame boundary processing by the delay profile device; Figure 6 is a schematic timing diagram illustrating offset detection by the delay profile device; Figure 7 is a schematic timing diagram illustrating sample storage by the delay profile device; Figure 8 is a schematic timing diagram illustrating delay profile generation by the delay profile device; and Freehills Carter Smith Beadle Melboume\004021426 Printed 25 March 2002 (16:39) Figure 9 is a block diagram of a preferred embodiment of a replica code generator of the delay profile device.

The 'Third Generation Partnership Project', or 3GPP, is responsible for the global development of the third generation mobile telephone system. The 3GPP team has developed a set of 3GPP technical specifications, that define how the 3GPP system will operate. In particular, specifications that provide background information relevant to signal delay profile determination include 3GPP TS 25.211 and 25.213, which are incorporated herein by reference. A 3GPP mobile telephone receives downlink signals transmitted in ms radio frames divided into 15 slots. Each slot is divided into 2560 chips, representing from 10 to 1280 bits of information, depending upon the spreading factor. A common pilot "channel (CPICH) is used to transmit pilot symbols that provide control information. The CPICH uses a spreading factor of 256, and each slot therefore contains 20 bits of information. This is equivalent to 10 symbols, because the system uses quadrature phaseshift keying (QPSK), and each two-bit pair represents an I,Q pair for one symbol.

3GPP provides a space time transmit antenna diversity (STTD) mode, in which a transmission cell transmits different pilot patterns from two antennas, antenna 1 and antenna 2. The pilot symbols for antenna 1 are all the same, denoted by A, whereas antenna 2 transmits A and -A symbols, as shown in Figure 2. In STTD mode, any pilot pattern of 4 symbols from antenna 2 is orthogonal to the corresponding pattern of 4 symbols of antenna 1, with the exception of two cases crossing the frame boundary. STTD mode is used for transmit (Tx) diversity in order to improve downlink (cell to mobile link) performance.

A typical receiver circuit of a third-generation mobile telephone, referenced 101 in Figure 1, is comprised of an analog-to-digital converter (ADC) 102, a cell search device 105, an automatic gain control (AGC) device 104, a delay profile device 100, a finger control device 106, a rake/finger receiver 108, and a timing control device 110. Each of the devices 100, 105, 106, 108 and 110 are typically realised by a processing unit and associated memory device for storing program instructions to cause the processing unit to perform predetermined digital signal processing techniques.

Freehills Carter Smith Beadle Melboume\004021426 Printed 25 March 2002 (16:39) Incoming radio frequency (RF) signals are digitised by the ADC 102, and the resulting samples are sent to the cell search device 105, the rake/finger receiver 108, and the delay profile device 100. The cell search device 105 is a standard W-CDMA component that analyses the samples and identifies a number of cells. For each found cell the cell search device 105 provides scrambling code and scrambling code timing. The cell search device 105 performs signal power measurements for each found cell, and based on the results of measurements and under the instruction of mobile network the receiver circuitry 101 decides to receive and process signals from one to a number of cells, i.e. the mobile telephone may establish one to a number of radio links (RL) or branches (BH).

The multiple radio links are used for soft handover (SHO) or diversity handover (DHO), to combine signals from multiple cells and improve performance when the mobile *Vee terminal is on cell boundaries, and to provide a smooth handover. For each branch the cell search device 105 provides an initial scrambling code timing (equal to the frame boundary 15 for the CPICH) to the timing control device 110. The timing control device 110 generates timing signals for each detected branch and sends them to the delay profile device 100. The timing signal for each branch is a 10 ms-period clock pulse with the pulse position indicating the scrambling code boundary of first mutipath in time in search range. The *V delay profile device 100 uses this timing information as a starting point to generate a profile of the correlation between the signal and the scrambling code as a function of the delay between them. The timing for each branch is maintained by the timing control device 110, and timing correction is based on the timing adjustment information provided by the finger control device 106. The finger control device 106 identifies the time delays which produce the best correlations, and provides those delay values to the RAKE/Finger unit 108, which performs de-spreading of input data for each indicated (allocated) multipath and constructively combines multipath signals after the de-spreading to improve receiver performance. The AGC 104 is used to normalize the signal gain to compensate for variations in the received signal strength.

A block diagram of the delay profile device 100 is shown in Figure 3. A timing control device 304 receives three independent timing signals from the timing control device 110. Each timing signal provides a 10 ms-period strobe synchronised to the downlink scrambling code boundary of the radio signal with the minimum delay in the Freehills Carter Smith Beadle Melbourne\004021426 Printed 25 March 2002 (16:39) search range for the corresponding branch. The timing control device 304 generates chip/symbol and slot timing signals for each branch synchronised to the external timing strobe for that branch. These internal timing signals are used by other blocks in the delay profile device 100. The timing control device 304 also generates a master start pulse 402 synchronised to the beginning of the second symbol of the master branch BH1, one symbol period after the scrambling code strobe 500, as shown in Figure 5. Here, for the sake of simplicity of explanation the first branch is taken as a master, although any branch can be programmed to be the master. Only an enabled branch can be the master. In response to the master start pulse 402, a random access memory (RAM) controller 302 begins to store a sequence of incoming samples in sample RAM 303.

The length of the stored sequence is equivalent to six symbols, to allow in-phase o.o accumulation of four pilot symbols to reduce noise, and providing a fifth symbol for each branch to allow for time variations. A sixth symbol ensures that each of the three branches 15 has a width of five symbols available. The ADC 102 sampling rate is four times the chip rate, but the RAM controller 302 only stores every second sample. The total number of samples to be stored is 6 symbols x 256 chips x 2 samples per chip x 2 for I and Q 3072 x 2 6142 samples. Since an IQ pair of samples can be stored per 16 bit word (8 bits for 1, and 8 bits for the total RAM required for storing the samples is 3072 16-bit words, or 6 kbytes.

The delay profile device 100 includes three replica generators 306, 307, 308 each generating the serial in-phase and quadrature scrambling codes and STTD antenna 2 pattern for one of the three branches, and each synchronised with the scrambling code boundary strobe for that branch. At the beginning of RAM storage, the state the register values) of the first replica generator 306 is stored in a replica storage device 310 in response to a BH1 storage signal. The storage of the incoming samples in RAM 303 always starts from the top of memory, and this includes the restart case which is described below.

When the first symbol pulse of the second branch is identified by the timing signal 406, the current state of the second replica generator 307 is stored in the replica storage device 310, and the current value of the RAM address is stored in an address pointer store Freehills Carter Smith Beadle Melboume\004021426 Printed 25 March 2002 (16:39) 311, as shown in Figure 4. Similarly, when the first symbol pulse of the third branch is indicated by timing signal 408, the current state of the third replica generator 308 is stored in the replica storage device 310, and the current value of the RAM address is stored in an address pointer store 311. The replica generator state and address pointer are also stored when a restart signal is received. It is not necessary to enable all three branches, and only two or even one branch may be enabled for the calculation. The branch enable/disable control is provided by a control unit, not shown in Figure 1. The delay profile device 100 processes any combination of enabled branches, and dynamically can change from one combination to another.

Because STTD-mode antenna pilot patterns are not always orthogonal across frame boundaries, as discussed above, the stored signal must not contain frame boundaries for any of the three branches. This is assured for the master branch, because the data storage begins with the second symbol of this branch. For the second or third branches, a frame boundary detector 312 detects frame boundaries during data storage and initiates a re-start S• :of data storage, as shown in Figure 5. When a frame boundary 506, 508 is detected during the storage of the first 5 symbols of data, storage restart signals 510, 512 are generated to restart storage from the next symbol pulse of the master branch symbol clock 504. The maximum delay for a restart is 5 symbols, and there are a maximum of two restarts. Thus, the minimum available time for sample storage and processing in a single frame is 15 slots 2 5 symbols 14 slots, with 15 slots per frame, and 10 symbols per slot. 00° The delay profile device 100 calculates a variable number of delay profiles for each frame. Usually, two delay profiles are determined per frame per branch. The first sample storage starts at the second symbol of the master branch, or at the next symbol boundary of the master branch after a restart (maximum 2 restarts), and the second profile storage begins 7 slots after the previous successful start pulse, as shown in Figure 7. Similarly, if the delay profile device 100 is configured to determine three delay profiles, the storage of the second profile begins 14/3 slots 4 slots 6 symbols after the successful start of the first profile. The sample storage for the third profile in this case shall start 4 slots 6 symbols after the successful start of second profile. The timing for larger number of profiles is determined in the same manner. The sample storage for 2 nd, 3 rd Nth profile Freehills Carter Smith Beadle Melboume\004021426 Printed 25 March 2002 (16:39) in frame takes into account the required time for the restart, so an equal processing time is allocated for each profile.

When the storage of samples in RAM 303 is complete, the correlation values for each of the three branches are determined. For a given branch, the RAM address pointer for the branch is reloaded from the address pointer store 311. The stored address indicates the first data sample in memory to be used for determining the correlation values of the branch. The address pointer for the master branch does not need to be stored, however, because the starting address of the master branch is always the beginning of the sample RAM 303. The register values stored from the replica generator for the current branch are also retrieved and loaded into a local replica generator 314. For example, the replica state and address values for the second branch, BH2, are restored to the appropriate registers in response to the restore BH2 signal 410, as shown in Figure 4.

S*o* 15 As described above, the sample RAM 303 stores every second ADC sample for an interval of 6 symbols, and the missing samples are later approximated by interpolation.

°However, there are two possible sub-sets of samples to be stored. The appropriate choice for a given branch depends upon the time alignment of the symbol clock for that branch and the sample sub-set. For example, the sub-set 604 of the 1/ chip samples 602 chosen for storage is the subset time-aligned with the BH1 start pulse 402, and therefore the BH1 symbol clock 606, as shown in Figure 6. The BH2 symbol clock 608 may also be aligned with the subset 604, but the BH3 symbol clock 610 may differ by chip from the chosen subset, indicating that the alternate sub-set was the best choice for this branch. The timing control block 304 detects this offset for non-master branches, and sends a signal to an interpolator 332. The interpolator 332 corrects the timing during the process of interpolation by shifting the samples by one /-chip position. The interpolator 332 processes a region of profile samples containing alternating zero and non-zero values. Thus the interpolator 332 effectively shifts the sampled data by simply inserting a zero before the first sample of the profile.

The local replica generator block 314 is used for the correlation calculation. As seen in Figure 9, the local replica generator consists of a channelisation code generator 902, a scrambling code generator 904, and an antenna 2 CPICH pilot pattern generator Freehills Carter Smith Beadle Melbourne\004021426 Printed 25 March 2002 (16:39) 906. At the beginning of correlation, the registers of the local replica generator 314 are reloaded with the appropriate previously saved state of the continuously running replica generators 306 to 308, depending upon which branch is being processed. The local replica generator 314 only operates during a correlation calculation. The channelisation code, scrambling code and antenna 2 pilot pattern are generated according to 3GPP specifications. The antenna 2 pilot pattern is generated by periodic repetition of 4 symbols {P1,P2,P3,P4} and by starting from the first symbol P1 at the start of every frame. The pilot replica generator 906 provides a 2-bit pointer value which points to one of the four possible pilot symbols, P1 to P4, and is synchronised with the scrambling code strobe for that branch.

~A correlator bank 316 performs the actual correlation calculations. The correlator V bank 316 takes the stored data from the sample RAM 303 through the RAM controller 302, then the local replica generator 314 is initialised with the replica generator registers o 15 stored in the replica storage block 310. The correlator bank 316 then performs the despreading operation on the samples i.e. performs phase rotation of samples and accumulates the phase rotated samples over one symbol period. The operation is repeated for three more symbols.

The process of generating a delay profile is illustrated in Figure 8. For each o branch, five symbols of data (2560 I,Q sample pairs) are used for the correlation calculation. For non-master branches, the 2560 sample pairs are indicated by corresponding branch address pointer stored in the address pointer store 311, and for the master branch the data is always taken from the top of the sample RAM 303.

The correlator bank 316 is implemented as a single bank of correlators. The correlator bank 316 requires more hardware resources than any other element of the delay profile device 100. However, because the same bank 316 is used for all three branches regardless of mutual branch timing, it is practical to use the delay profile device 100 in mobile terminals of unsynchronised cellular networks.

A delay profile is generated by performing correlation calculations in a loop, shifting the starting point in the sample data by two samples at the end of each loop, and Freehills Carter Smith Beadle Melboume\004021426 Printed 25 March 2002 (16:39) 11 executing the loop 512 times for each of 4 symbols, with the result that a profile of 4x512 correlation results as a function of time delay are produced. An in-phase symbol accumulator 318 takes the output of the correlator bank 316 and performs in-phase symbol combining. For normal mode (non STTD mode), the four symbols are simply accumulated by complex addition. For STTD mode, the in-phase accumulator 318 sorts incoming symbols from the correlator bank 316 into two groups. The first group corresponds to pilots A and the second group corresponds to pilots For each 4 symbols, two of them are A pilots, and two of them are -A pilots. Because symbols from the frame boundary are excluded from the processing, orthogonality between two antenna patterns is preserved.

The symbols A and -A are determined by the antenna 2 CPICH pilot pattern generator 906 of the local replica generator 314. Before the start of each branch correlation calculation, the antenna 2 CPICH pilot pattern of the local replica generator 314 is loaded with the too* saved value of the synchronised replica counter. The in-phase symbol accumulation for sooo Sto, STTD mode is performed in two steps: in-phase accumulation for antenna 1, and in-phase accumulation for antenna 2. For clarity, let represent the -A symbol. First, the in-phase summation of two symbols is calculated: o *db AA A A (add two symbols corresponding to A symbols, A pair) SBB B B (add two symbols corresponding to -A symbols, -A pair) The four symbol in-phase accumulation for antenna 1 is calculated as follows: AABB AA BB For antenna 1, the four symbols are accumulated without any rotation, and in the same way as for normal (non STTD) mode.

The four symbol in-phase accumulation for antenna 2 is calculated in following way: AACC AA BB In this case, the -A symbols are rotated by 180 degrees before the accumulation.

Freehills Carter Smith Beadle Melbourne\004021426 Printed 25 March 2002 (16:39) The symbols are combined in pairs (A symbols, or -A symbols), then the pairs are combined to accumulate 4 symbols in total. The combining of symbols in pairs can be used for all modes.

The partial symbol in-phase accumulations are performed in the process of correlation by allowing the correlator to continue processing over the symbol boundary. In this case, the partial accumulation of two symbols is performed during the correlation phase, i.e. pairs of A or -A symbols are summed. The symbol pairs for partial accumulation are determined based on the antenna 2 replica pattern generator. There are four possible combinations of the 4 pilot symbol pattern: {A A -A -A A {A -A -A and A A For the first two combinations, the correlator simply accumulates the first and second symbol, and also accumulates the third and fourth symbol. For the last two combinations, a local storage is required to store the first symbols, 15 and then restore the first symbol values to the correlator registers before the 4 t h symbol despreading starts. The required storage size is related to the number of correlators in the correlation bank and is not significant compared with the profile length.

The accumulated value(s) is/are forwarded to a power calculator block 320. The power calculator 320 calculates an amplitude approximation to be used instead of power.

The calculation is given by the following formula: Powapp MAX(III,IQI) 0.5 MIN(III,IQI) where MAX(x,y) bigger of x and y MIN(x,y) smaller of x and y for C>=0 ICI=C, for C<0 CI=-C I,Q are the in-phase and quadrature components of 4 accumulated symbols The 0.5 multiplication is performed by a right bit shift by 1 bit.

The amplitude approximation provides a decrease in required dynamic range of profile values, thus the required hardware resources are reduced.

Freehills Carter Smith Beadle Melboume\004021426 Printed 25 March 2002 (16:39) 13 For STTD mode, the power calculation is performed in the following three steps: Calculate the amplitude approximation for antenna 1 (as above) Calculate the amplitude approximation for antenna 2 (as above) Combine the amplitude approximations from two antennas For normal mode, the amplitude approximation is calculated only for antenna 1.

An AGC weighting block 322 multiplies the amplitude approximation result from the power calculator block 320 with the AGC gain from the RF AGC unit 104.

S. A normalisation block 324 normalises the binary sample values in each profile according to the maximum value in the profile. Each value in the profile is bit-shifted left until the maximum value has one leading zero. The number of bit shifts is accounted for 15 by an exponent, used for all values in the profile. The normaliser 324 provides better utilisation of the available bit widths for profile averaging.

The averaging block 326 accumulates up to 32 profiles to further reduce noise. The actual number of frames used for profile accumulation is programmable. The accumulated profiles are stored in a profile RAM 330. The required RAM for profile storage is 3x512 words. The common exponent determined by the normalisation block 324 is assigned to each branch profile. The required division in the process of averaging is performed by an exponent correction approximation. The exponent correction is for 0,1,2, and it is dependent on number of accumulated profiles. The common exponent allows the number of bits per profile to be reduced, thereby decreasing the memory required for profile storage.

As discussed above, the interpolator block 332 performs interpolation to increase the resolution of the delay profiles from V2 chip to 4 chip, increasing the number of profile samples from 512 to 1024. The interpolation is performed in two steps: first, the profile samples and 512 zeros are interleaved, then the filtering is performed. A Finite Impulse Response (FIR) poly-phase filter is used for interpolation, where 512 samples of the 1024 sample profile are unchanged from their original values, i.e. only the missing the Freehills Carter Smith Beadle Melboume\004021426 Printed 25 March 2002 (16:39) 14 zero-valued) samples are calculated. As discussed above, the interpolator compensates 1 sample shift for non-master branches, if required.

The average value block 334 calculates an average value for each completed profile. The average profile value and the delay profile itself are provided to the finger control device 106.

The delay profile device 100 achieves a high level of parallel processing. While the correlation calculations are being performed, the power calculation, normalisation, and profile accumulation are performed in parallel. The profile average block 326 performs the profile accumulation of the last branch in parallel with the sample data storage for the next S.profile calculation.

Many modifications will be apparent to those skilled in the art without departing 15 from the scope of the present invention as hereinbefore described with reference to the accompanying drawings.

Freehills Carter Smith Beadle Melbourne\004021426 Printed 25 March 2002 (16:39)

Claims (12)

1. A method for determining a plurality of signal delay profiles in a mobile telephone apparatus, including: storing sampled signal data in a region or memory, said signal data comprising signal data from a plurality of radio links or branches; determining timing data for each of said plurality of radio links or branches; sequentially determining correlation data for each of said plurality of radio links or branches, said correlation data determined for a plurality of delay values based on said timing data and said sampled signal data; and for each of said plurality of radio links or branches, determining a signal delay profile based on said correlation data, and said delay values.

2. A method according to claim 1, and further including: 15 determining, for each of said plurality of radio links or branches, an address within said region of memory based on said timing data, said address identifying the corresponding radio link or branch.

3. A method according to claim 2, and further including: concurrently determining scrambling codes for each of said radio links or branches, said scrambling codes synchronised with said timing data for the corresponding radio link or branch, and storing said address and the state of each scrambling code in response to the timing data for the corresponding radio link or branch.

4. A method according to any one of the preceding claims, wherein said correlation data for all radio links or branches is determined by a single correlator bank, said correlation data for each radio link or branch based on said stored address and scrambling code state.

5. A method according to any one of the preceding claims, wherein said step of storing sampled signal data includes monitoring said signal data for frame boundaries and restarting said step if a frame boundary is detected. 16

6. A method according to any one of the preceding claims, wherein said correlation data for each radio link or branch is normalised by bit shifting said data and determining a single exponent value for said data.

7. A method according to any one of the preceding claims, wherein said step of storing sampled signal data includes storing selected samples of said data, and said step of determining a delay profile includes compensating for unselected samples by interpolation.

8. A method according to any one of the preceding claims, wherein said method includes accumulation of in-phase symbols to reduce noise.

9. A method according to any one of the preceding claims, wherein said method includes weighting correlation values based on gain data to compensate for variations in signal strength. *o

10. A delay profile measurement device for use in a mobile telephone apparatus, the delay profile measurement device including a processing unit and a memory device, operatively connected to the processing unit, for storing program instructions to cause the processing unit to carry out a method according to any one of the preceding claims.

11. A method for determining a plurality of signal delay profiles including steps substantially as hereinbefore described.

12. A delay profile measurement device substantially as hereinbefore described with reference to the accompanying drawings. Dated: 27 March 2002 FREEHILLS CARTER SMITH BEADLE Patent Attorneys for the Applicant NEC AUSTRALIA PTY LTD