AU2017204549B2 - System and method for controlling a thermal array - Google Patents

Abstract

A system and method is provided. The system and method calculate target setpoints for each thermal element and index through each thermal element to provide power to the thermal element, sense an electrical characteristic of the thermal element, and determine if the thermal element exceeds a target setpoint for the thermal element based on the sensed electrical characteristic. WO 2013/033332 PCT/US2012/053049 10/17 600 Control 61 Calculate -/-612 Setpoints Calculate Time Windows 614 For Each Thermal Element 616 620 622 Is End Of Yes Time w Increment To Window Next Thermal 624 624 Element 62 No A Power and Measure Thermal Element Characteristics 626 Post thermalYe Element Setpoint Based on Measured Characteristics 628 630 No FIG. 6a

Description

Control 61

Calculate -/-612 Setpoints

Calculate Time Windows 614 For Each Thermal Element

616 620 622 Is End Of Yes Time w Increment To Window Next Thermal 624 Element 624 62 No A

Power and Measure Thermal Element Characteristics

626

Post thermalYe Element Setpoint Based on Measured Characteristics 628

630 No

FIG. 6a

SYSTEM AND METHOD FOR CONTROLLING A THERMAL ARRAY CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of provisional application serial nos.

61/528,939 filed on August 30, 2011 and 61/635,310 filed on April 19, 2012, the

contents of which are incorporated herein by reference in their entirety. This

application is also related to co-pending applications titled "High Definition Heater

and Method of Operation," "High Definition Parallel Control Systems for Heaters,"

"Thermal Array System," "Thermal Array System," "Thermal Array System," and

"System and Method for Controlling A Thermal Array," concurrently filed herewith

and commonly assigned with the present application, the contents of which are

incorporated herein by reference in their entirety.

BACKGROUND

[0002] The present application generally relates to a system and method for

controlling a thermal array.

[0003] Throughout this specification the word "comprise", or variations such

as "comprises" or "comprising", will be understood to imply the inclusion of a stated

element, integer or step, or group of elements, integers or steps, but not the

exclusion of any other element, integer or step, or group of elements, integers or

steps.

[0004] Any discussion of documents, acts, materials, devices, articles or the

like which has been included in the present specification is not to be taken as an

admission that any or all of these matters form part of the prior art base or were

common general knowledge in the field relevant to the present disclosure as it

existed before the priority date of each claim of this application.

SUMMARY

[0005] In overcoming the drawbacks and other limitations of the related art,

the present application provides a system and method that calculates target

setpoints for each thermal element and indexes through each thermal element to

provide power to the thermal element, sense an electrical characteristic of the

thermal element, and determine if the thermal element exceeds a target setpoint for

the thermal element based on the sensed electrical characteristic.

[0006] A thermal system comprising: a plurality of thermal elements; a control

system having a plurality of power nodes, wherein the thermal elements are

connected the plurality of power nodes, the control system is configured to calculate

target setpoints for the thermal elements based on temperature set points, and for

each thermal element, the control system is configured to (a) provide one of a

power, a return and an open circuit condition to the thermal element, (b) sense an

electrical characteristic of the thermal element by measuring the electrical

characteristic across the power nodes connected to the thermal elements, and (c)

determine if the thermal element exceeds a target setpoint for the thermal element

based on the sensed electrical characteristic.

[0007] A heater comprising: a base plate; a base heater secured to the base

plate; a substrate secured to the base heater; a tuning heater secured to the

substrate, the tuning heater comprising a plurality of heater elements; a chuck

secured to the tuning heater; and a control system having a plurality of power nodes,

wherein the heater elements are connected to the plurality of power nodes, the

control system is configured to calculate target setpoints for the heater elements

based on temperature set points, and for each heater element, the control system is configured to (a) provide one of a power, a return, and an open circuit condition to the heater element, (b) sense an electrical characteristic of the heater element by measuring the electrical characteristic across the power nodes connected to the heater elements, and (c) determine if the heater element exceeds a target setpoint for the heater element based on the sensed electrical characteristic.

[0008] A thermal system comprising: a plurality of thermal elements; a control

system having a plurality of power nodes, wherein the thermal elements are

connected to the plurality of power nodes, the control system operates the plurality

of power nodes in a plurality of modes in which a given node is selectively

connected to one of a power, a return, and an open circuit condition, and each mode

of the plurality of modes represents a different combination of the plurality of nodes

being connected to the power, the return, and the open circuit condition, the control

system is configured to calculate target setpoints for the thermal elements based on

temperature set points, and for each mode, the control systems is configured to (a)

provide power to the thermal elements according to the mode, (b) sense an

electrical characteristic of the mode by measuring the electrical characteristic across

the power nodes connected to the thermal element, and (c) determine whether each

thermal element exceeds a target setpoint for the thermal element based on the

sensed electrical characteristic.

[0009] Further features and advantages of this application will become readily

apparent to persons skilled in the art after a review of the following description, with

reference to the drawings and claims that are appended to and form a part of this

specification.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. la is a partial side view of a heater having a tuning layer and

constructed in accordance with the principles of one form of the present disclosure;

[0011] FIG. 1b is an exploded side view of another form of the heater having a

tuning layer or tuning heater and constructed in accordance with the principles of the

present disclosure;

[0012] FIG. 1c is a perspective exploded view of a heater illustrating an

exemplary four (4) zones for the base heater and eighteen (18) zones for the tuning

heater in accordance with the principles of the present disclosure;

[0013] FIG. 1d is a side view of another form of a high definition heater

system having a supplemental tuning layer and constructed in accordance with the

principles of the present disclosure;

[0014] FIG. 2 is a schematic for a bidirectional thermal array;

[0015] FIG. 3a is a schematic for a multi-parallel thermal array;

[0016] FIG. 3b is a schematic for a multi-parallel and bidirectional thermal

array;

[0017] FIG. 4 is a another schematic for a multi-parallel and bidirectional

thermal array;

[0018] FIG. 5 is a schematic for a thermal array with addressable switches;

[0019] FIG. 6A is a flowchart illustrating a method of controlling a thermal

array;

[0020] FIG. 6B is a timing diagram illustrating the control method from 6A;

[0021] FIG. 7A is a flowchart illustrating another control method for a thermal

array;

[0022] FIG. 7B is a four node topology used for one example of the described

methods;

[0023] FIG. 8 is a flowchart illustrating a method for measuring electrical

characteristics of a mode of the thermal array;

[0024] FIG. 9a is a flowchart illustrating a method for calibrating the thermal

array;

[0025] FIG. 9b is a flowchart illustrating a method for calculating target set

points for the thermal array;

[0026] FIG. 10 is a schematic for one implementation of a controller system.

DETAILED DESCRIPTION

[0027] The following description is merely exemplary in nature and is not

intended to limit the present disclosure, application, or uses. For example, the

following forms of the present disclosure are directed to chucks for use in

semiconductor processing, and in some instances, electrostatic chucks. However, it

should be understood that the heaters and systems provided herein may be

employed in a variety of applications and are not limited to semiconductor

processing applications.

[0028] Referring to FIG. 1a, one form of the present disclosure is a heater 50

that includes a base heater layer 52 having at least one heater circuit 54 embedded

therein. The base heater layer 52 has at least one aperture 56 (or via) formed

therethrough for connecting the heater circuit 54 to a power supply (not shown). The

base heater layer 52 provides primary heating while a tuning heater layer 60

disposed proximate the heater layer 52 as shown provides for fine tuning of a heat

distribution provided by the heater 50. The tuning layer 60 includes a plurality of individual heating elements 62 embedded therein, which are independently controlled. At least one aperture 64 is formed through the tuning layer 60 for connecting the plurality of individual heating elements 62 to the power supply and controller (not shown). As further shown, a routing layer 66 is disposed between the base heater layer 52 and the tuning layer 60 and defines an internal cavity 68. A first set of electrical leads 70 connects the heater circuit 54 to the power supply, which extend through the heater layer aperture 56. A second set of electrical leads

72 connects a plurality of heating elements 62 to the power supply and extend

through the internal cavity 68 of the routing layer 66, in addition to the aperture 55 in

the base heater layer 52. It should be understood that the routing layer 66 is

optional, and the heater 50 could be employed without the routing layer 66 and

instead having only the base heater layer 52 and the tuning heater layer 60.

[0029] In another form, rather than providing fine tuning of a heat distribution,

the tuning layer 60 may alternately be used to measure temperature in the chuck 12.

This form provides for a plurality of area-specific or discreet locations, of

temperature dependent resistance circuits. Each of these temperature sensors can

be individually read via a multiplexing switching arrangement, exemplary forms of

which are set forth in greater detail below, that allows substantially more sensors to

be used relative to the number of signal wires required to measure each individual

sensor. The temperature sensing feedback can provide necessary information for

control decisions, for instance, to control a specific zone of backside cooling gas

pressure to regulate heat flux from the substrate 26 to the chuck 12. This same

feedback can also be used to replace or augment temperature sensors installed

near the base heater 50 for temperature control of base heating zones 54 or balancing plate cooling fluid temperature (not shown) via ancillary cool fluid heat exchangers.

[0030] In one form, the base heater layer 50 and the tuning heater layer 60

are formed from enclosing heater circuit 54 and tuning layer heating elements 62 in

a polyimide material for medium temperature applications, which are generally below

2500 C. Further, the polyimide material may be doped with materials in order to

increase thermal conductivity.

[0031] In other forms, the base heater layer 50 and/or the tuning heater layer

60 are formed by a layered process, wherein the layer is formed through application

or accumulation of a material to a substrate or another layer using processes

associated with thick film, thin film, thermal spraying, or sol-gel, among others.

[0032] In one form, the base heating circuit 54 is formed from Inconel* and

the tuning layer heating elements 62 are a Nickel material. In still another form, the

tuning layer heating elements 62 are formed of a material having sufficient

temperature coefficient of resistance such that the elements function as both heaters

and temperature sensors, commonly referred to as "two-wire control." Such heaters

and their materials are disclosed in U.S. Patent No. 7,196,295 and pending U.S.

patent application serial no. 11/475,534, which are commonly assigned with the

present application and the disclosures of which are incorporated herein by

reference in their entirety.

[0033] With the two-wire control, various forms of the present disclosure

include temperature, power, and/or thermal impedance based control over the layer

heating elements 62 through knowledge or measurement of voltage and/or current

applied to each of the individual elements in the thermal impedance tuning layer 60, converted to electrical power and resistance through multiplication and division, corresponding in the first instance, identically to the heat flux output from each of these elements and in the second, a known relationship to the element temperature.

Together these can be used to calculate and monitor the thermal impedance load on

each element to allow an operator or control system to detect and compensate for

area-specific thermal changes that may result from, but are not limited to, physical

changes in the chamber or chuck due to use or maintenance, processing errors, and

equipment degradation. Alternatively, each of the individually controlled heating

elements in the thermal impedance tuning layer 60 can be assigned a setpoint

resistance corresponding to the same or different specific temperatures which then

modify or gate the heat flux originating from corresponding areas on a substrate

through to the base heater layer 52 to control the substrate temperature during

semiconductor processing.

[0034] In one form, the base heater 50 is bonded to a chuck 51, for example,

by using a silicone adhesive or even a pressure sensitive adhesive. Therefore, the

heater layer 52 provides primary heating, and the tuning layer 60 fine tunes, or

adjusts, the heating profile such that a uniform or desired temperature profile is

provided to the chuck 51, and thus the substrate (not shown).

[0035] In another form of the present disclosure, the coefficient of thermal

expansion (CTE) of the tuning layer heating elements 62 is matched to the CTE of

the tuning heating layer substrate 60 in order to improve thermal sensitivity of the

tuning layer heating elements 62 when exposed to strain loads. Many suitable

materials for two-wire control exhibit similar characteristics to Resistor Temperature

Devices (RTDs), including resistance sensitivity to both temperature and strain.

Matching the CTE of the tuning layer heating elements 62 to the tuning heater layer

substrate 60 reduces strain on the actual heating element. And as the operating

temperatures increase, strain levels tend to increase, and thus CTE matching

becomes more of a factor. In one form, the tuning layer heating elements 62 are a

high purity Nickel-Iron alloy having a CTE of approximately 15 ppm/°C, and the

polyimide material that encloses it has a CTE of approximately 16 ppm/°C. In this

form, materials that bond the tuning heater layer 60 to the other layers exhibit elastic

characteristics that physically decouple the tuning heater layer 60 from other

members of the chuck 12. It should be understood that other materials with

comparable CTEs may also be employed while remaining within the scope of the

present disclosure.

[0036] Referring now to FIGS. 1b-d, one exemplary form of the heater having

both a base heater layer and a tuning layer (as generally set forth above in FIG. 1a)

is illustrated and generally indicated by reference numeral 80. The heater 80

includes a base plate 82, (also referred to as a cooling plate), which in one form is

an Aluminum plate approximately 16mm in thickness. A base heater 84 is secured

to the base plate 82, in one form using an elastomeric bond layer 86 as shown. The

elastomeric bond may be one disclosed in U.S. Patent No. 6,073,577, which is

incorporated herein by reference in its entirety. A substrate 88 is disposed on top of

the base heater 84 and is an Aluminum material approximately 1mm in thickness

according to one form of the present disclosure. The substrate 88 is designed to

have a thermal conductivity to dissipate a requisite amount of power from the base

heater 84. Because the base heater 84 has relatively high power, without a requisite

amount of thermal conductivity, this base heater 84 would leave "witness" marks

(from the resistive circuit trace) on adjacent components, thereby reducing the

performance of the overall heater system.

[0037] A tuning heater 90 is disposed on top of the substrate 88 and is

secured to a chuck 92 using an elastomeric bond layer 94, as set forth above. The

chuck 92 in one form is an Aluminum Oxide material having a thickness of

approximately 2.5mm. It should be understood that the materials and dimensions as

set forth herein are merely exemplary and thus the present disclosure is not limited

to the specific forms as set forth herein. Additionally, the tuning heater 90 has lower

power than the base heater 84, and as set forth above, the substrate 88 functions to

dissipate power from the base heater 84 such that "witness" marks do not form on

the tuning heater 90.

[0038] The base heater 84 and the tuning heater 90 are shown in greater

detail in FIG. 1c, in which an exemplary four (4) zones are shown for the base heater

84, and eighteen (18) zones for the tuning heater 90. In one form, the heater 80 is

adapted for use with chuck sizes of 450mm, however, the heater 80 may be

employed with larger or smaller chuck sizes due to its ability to highly tailor the heat

distribution. Additionally, the high definition heater 80 may be employed around a

periphery of the chuck, or in predetermined locations across the chuck, rather than

in a stacked/planar configuration as illustrated herein. Further still, the high

definition heater 80 may be employed in process kits, chamber walls, lids, gas lines,

and showerheads, among other components within semiconductor processing

equipment. It should also be understood that the heaters and control systems

illustrated and described herein may be employed in any number of applications, and thus the exemplary semiconductor heater chuck application should not be construed as limiting the scope of the present disclosure.

[0039] The present disclosure also contemplates that the base heater 84 and

the tuning heater 90 not be limited to a heating function. It should be understood

that one or more of these members, referred to as a "base functional layer" and a

"tuning layer," respectively, may alternately be a temperature sensor layer or other

functional member while remaining within the scope of the present disclosure.

[0040] As shown in FIG. 1d, a dual tuning capability may be provided with the

inclusion of a secondary tuning layer heater 99 on the top surface of the chuck 12.

The secondary tuning layer may alternately be used as a temperature sensing layer

rather than a heating layer while remaining within the scope of the present

disclosure. Accordingly, any number of tuning layer heaters may be employed and

should not be limited to those illustrated and described herein.

[0041] Now referring to FIG. 2, a thermal array system 100 is provided. The

system 100 includes a controller 110. The controller 110 may be a control circuit or

a microprocessor based controller. The controller 110 may be configured to receive

sensor measurements and implement a control algorithm based on the

measurements. In some examples, the controller may measure an electrical

characteristic of one or more of the thermal array elements. Further, the controller

110 may include and/or control a plurality of switches to determine how power is

provided to each thermal element of the array based on the measurements.

[0042] In one example, power is provided to the array through a three-phase

power input as denoted by reference numerals 112, 114, 116. The input power may

be connected to a rectifier circuit 118 to provide a positive direct current (DC) power line 120 and a negative DC power line 122. The power may be distributed to the thermal array through six power nodes. The controller 110 may be configured to control a plurality of switches, such that the positive power line 120 can be routed to any one of the six power nodes and the negative power line 122 can also be routed to any one of the plurality of power nodes.

[0043] In the implementation shown, the power nodes are configured into two

groups of nodes. The first group of nodes includes power node 136a, power node

136b, and power node 136c. The second group includes power node 138a, power

node 138b, and power node 138c. In the implementation shown, the thermal

elements are configured into a matrix arrangement with three groups of thermal

elements and each group containing six thermal elements. However, as with each

implementation described herein, more or fewer nodes can be used and , further,

the number of thermal elements may be correspondingly increased or decreased

with the number of nodes.

[0044] The first group 160 of the thermal elements are all connected to node

138a. Similarly, the second group 170 of thermal elements are all connected to

power node 138b, while the third group 180 of thermal elements are all connected to

power node 138c. The thermal element may be heater elements. The heater

elements may be formed of an electrically conductive material with, for example, a

temperature dependent electrical resistance. More specifically, the thermal

elements may be heater elements with an electrical characteristic, such as a

resistance, capacitance, or inductance, that correlates to temperature. Although, the

thermal elements may also generally be classified as dissipative elements, such as

resistive elements. Accordingly, the thermal elements in each of the implementations described herein may have any of the characteristics described above.

[0045] Within each group, the six thermal elements are configured into pairs

of thermal elements. For example, in the first group 160, the first pair of thermal

elements 146a includes a first thermal element 164 and a second thermal element

168. The first thermal element 164 is configured in electrical parallel connection with

the second thermal element 168. Further, the first thermal element 164 is in

electrical series connection with a unidirectional circuit 162. The unidirectional

circuit 162 may be configured to allow current to flow through the thermal element

164 in one direction and not in the opposite direction. As such, the unidirectional

circuit 162 is shown in its simplest form as a diode.

[0046] The first unidirectional circuit 162 is shown as a diode with the cathode

connected to node 136a and the anode connected to node 138a through thermal

element 164. In a similar manner, the second unidirectional circuit 166 is shown as

a diode with a cathode connected to node 138a through the second thermal element

168 and an anode connected to node 136a, thereby illustrating the unidirectional

nature of the first unidirectional circuit 162 being opposite to the second

unidirectional circuit 166. It is noted that the implementation of a diode as a

unidirectional circuit may only work for a one volt power supply, however, various

other circuits may be devised including for example, circuits using silicon controlled

rectifiers (SCR's) that work for higher power supply voltages. Such implementations

of unidirectional circuits are described in more detail later, but could be used in

conjunction with any of the implementations described herein.

[0047] In a similar manner, the second thermal element 168 is in electrical

series connection with a second unidirectional circuit 166, again in its simplest form

shown as a diode. The first thermal element 164 and the first unidirectional circuit

162 are parallel with the second thermal element 168 and the second unidirectional

circuit 166 between the power node 138a and power node 136a. Accordingly, if the

controller 110 applies a positive voltage to node 136a and a negative voltage to

node 138a, power will be applied across both the first thermal element 164 and the

second thermal element 168 of the first pair 146a. As described above, the first

unidirectional circuit 162 is oriented in an opposite direction of the second

unidirectional circuit 166. As such, the first unidirectional circuit 162 allows current

to flow through the first thermal element 164 when a positive voltage is applied to

node 138a and a negative voltage is applied to node 136a, but prevents current from

flowing when a positive voltage is provided to node 136a and a negative voltage is

provided to node 138a. In contrast, when a positive voltage is applied to node 136a

and a negative voltage is applied to 138a, current is allowed to flow through the

second thermal element 168, however, current flow through the second thermal

element 168 is prevented by the second unidirectional circuit 166 when the polarity

is switched.

[0048] In addition, each pair of thermal elements within a group is connected

to the different power node of the first group of power nodes 136a, 136b, 136c.

Accordingly, the first pair of thermal elements 146a of the first group 160 is

connected between node 136a and node 138a. The second pair of thermal

elements 146b is connected between power node 136b and power node 138a, while

the third pair 146c of thermal elements of group 160 is connected between power node 136c and power node 138a. As such, the controller 110 may be configured to select the group of elements by connecting power node 138a to supply power or return then the pair of thermal elements (146a, 146b, 146c) may be selected by connecting one of the nodes 136a, 136b, or 136c, respectively, to supply power or return. Further, the controller 110 may select to provide power to the first element of each pair or the second element of each pair based on the polarity of the voltage provided between node 138a and nodes 136a, 136b, and/or 136c.

[0049] In the same manner, the second group of thermal elements 170 are

connected between node 138b of the second group of nodes, and node 136a, 136b,

and 136c. As such, the first pair 146d of thermal elements of group 170 may be

selected using power node 136a, while the second pair 146e and the third pair 146f

of thermal elements of group 170 may be selected by node 136b and 136c,

respectively.

[0050] Likewise, the second group of thermal elements 180 are connected

between node 138c of the second group of nodes, and node 136a, 136b, and 136c.

The first pair 146g of thermal elements of group 180 may be selected using power

node 136a, while the second pair 146h and the third pair 146i of thermal elements of

group 170 may be selected by node 136b and 136c, respectively.

[0051] For the implementation shown, the controller 110 manipulates a

plurality of switches to connect the positive power line 120 to one of the first group of

power nodes and the negative power line 122 to the second group of power nodes

or, alternatively, connects the positive power line 120 to the second group of power

nodes and the negative power line 122 to the first group of power nodes. As such,

the controller 110 provides a control signal 124 to a first polarity control switch 140 and a second polarity control switch 142. The first polarity control switch 140 connects the first group of power nodes to either the positive power supply line 120 or the negative power supply line 122, while the second polarity switch 142 connects the second group of power nodes to the positive power supply line 120 or the negative power supply line 122.

[0052] In addition, the controller 110 provides control signals 126 to the first

group power switches 130, 132, and 134. The switches 130, 132, and 134 connect

the output of switch 140 (the positive supply line 120 or the negative supply line 122)

to the first node 136a, the second node 136b, and the third node 136c, respectively.

In addition, the controller 110 provides control signals 128 to the second group

power switches 150, 152, and 154. The switches 150, 152, and 154 connect the

output of switch 142 (the positive supply line 120 or the negative supply line 122) to

the first node 138a, the second node 138b, and the third node 138c, respectively.

[0053] Now referring to FIG. 3a, a multi-parallel thermal array system 200 is

provided. The system 200 includes a control system 210. The control system may

include a microprocessor, switches, and other discrete components similar to those

described throughout the application to implement the logic described herein. The

thermal elements are arranged in a multi-parallel fashion across pairs of power

nodes. For the implementation shown, six power nodes (212, 214, 216, 218, 220,

222) are provided. Further, each thermal element is connected between a pair of

power nodes. More specifically, each thermal element is connected between a

different pair of power nodes. As such, each node has one thermal element

connected between itself and each other power node.

[0054] Accordingly, thermal element 230 is connected between node 212 and

node 222, thermal element 232 is connected between node 212 and node 220,

thermal element 234 is connected between node 212 and node 218, thermal

element 236 is connected between node 212 and node 216, and thermal element

238 is connected between node 212 and node 214. As such, node 212 is connected

to each of the other nodes 214, 216, 218, 220, and 222 through a thermal element

(230, 232, 234, 236, or 238).

[0055] Similarly, thermal element 240 is connected between node 214 and

node 222, thermal element 242 is connected between node 214 and node 220,

thermal element 244 is connected between node 214 and node 218, and thermal

element 246 is connected between node 214 and node 216. It is noted that the

thermal element connected between node 214 and node 212 has already been

identified as thermal element 238. In addition, the connections between each other

pair of elements are provided by thermal element 250 being connected between

node 216 and node 222, thermal element 252 being connected between node 216

and node 220, thermal element 254 being connected between node 216 and node

218, thermal element 260 being connected between node 218 and node 222,

thermal element 262 being connected between node 218 and node 220, and thermal

element 270 being connected between node 220 and node 222.

[0056] The controller 210 is configured to provide a power connection, a

return connection, or an open circuit to each node. In addition, it can be recognized

that the multi-parallel topology is significantly different from the matrix topology

provided in FIG. 2. The multi-parallel topology provides that the thermal element

network be considered in whole with regard to power distribution for heating as well as understanding the interaction of all elements for thermal sensing. For example, if a supply power is provided to node 212 and a return connection is provided to node

222, the primary power path would be through thermal element 230. However,

secondary paths would exist through each of the other elements within the network

back to node 222. As such, the controller 210 when providing power and return to

any configuration of nodes must consider the power being provided to the thermal

element of the primary path, as well as, the power being provided to all the other

elements through the secondary paths. This task can be significantly complex

based on each thermal element having different characteristics either by design,

environmental influences, or manufacturing tolerances.

[0057] For this topology, the control scheme may be employ six (6) wires and

fifteen elements (15) without the use of switching circuits having SCRs, diodes, and

other elements as set forth above. The maximum number of elements in relation to

wires for this control scheme is E = %(N x (N - 1)). While each wire may be powered

continuously, applying independent voltages to any node combination, this system

can be difficult to control. According to this form of the present disclosure, wires are

selectively connected to power, return, or are left open-circuit, using sequences of

these combinations for specified periods of time, in order to produce a desired

average heating distribution. For example, one combination could be to connect A

and B to power, connect C and D to return, and leave E and F open-circuit; another

combination could be to connect A and C to power, connect D to return, and leave

B, E and F open-circuit. These combinations or modes, are then applied in

sequence to the tuning layer heating elements for varying periods of time, e.g., a first

mode is applied for a first time t, a second mode is applied for a second time t2 , and so on, such that the resulting timed sequence produces the desired average heating distribution in the tuning layer heater. In one form, timing sequence time intervals are used that are much shorter than the thermal time constant of the heater so that temperature ripple in the heater is kept to a sufficiently low level. In the six wire example given, there are 301 possible non-redundant modes for N-wires where a non-redundant mode is one that produces power in at least one element and does not produce the same power at the same elements in the system as another mode.

If the modes associated with open-circuits are removed, then the number of non

redundant modes for N-wires is Modes= 2 N- -1. Accordingly, for the same six wire,

fifteen element system, there are 31 non-redundant, non-zero (null) modes. The

resulting mode matrix [PxM] for a six node, fifteen element system is then either (15

x 301) or (15 by 31) and a solution to the matrix equation [PE =PxM] Modes] is

needed, where PE is a vector of Power (heat flux) output from the elements. With

the open circuits, the number of multiparallel modes = (3 N - 2 N+1 - 1)/2(non

redundant). The [PxM] matrix is underdetermined and likely to be ill-conditioned if

the full open-circuit inclusive matrix is used and produces a mode vector that is

highly error prone and difficult to implement due to the number of modes that must

be produced in a given time window. Further, a solution is not always possible for all

desired power vectors. Complexity and errors may be reduced by selecting a subset

of modes chosen based on matrix condition. One method for evaluating matrix

condition of a selected subset of modes is to perform a singular value decomposition

on subsets of the [PxM] matrix, comparing subsets against each other and selecting

the set with the smallest ratio of largest to smallest non-zero singular values. Only

non-negative modes can be used because power can only be added to the system, so this matrix subset [PxMR] can then be used to solve a the non-negative least squares problem min||[PxMR]e[MOdes]- [PE where Modes >0. Examining the M1odes residues of the solution gives a measure of the solution error. A finite number of these solutions will be near exact, but as the number of wires and elements is increased, the system becomes more constrained and the range of low-error independent power solutions for each element decreases. It should be noted that the method presented is for power control to the elements and because of the underdetermined topography, stable resistive elements with low TCR would produce the lowest error solutions, but this does not preclude the use of high TCR elements or the use of a separate temperature sensing plane to bring this system under temperature control.

[0058] Now referring to FIG. 3b, a multi-parallel and bidirectional thermal

array system 300 is provided. The thermal array system 300 includes a control

system 310. The control system 310 may include a microprocessor, switches, and

other discrete components similar to those described throughout the application to

implement the logic described herein. As in Figure 2, the thermal elements are

arranged in a multi-parallel fashion across pairs of power nodes. Being bidirectional,

twice the number of thermal elements are able to be controlled with the same

number of nodes. For the embodiments shown, six power nodes (312, 314, 316,

318, 320, 222). Further, each pair of thermal element is connected between a pair

of power nodes, where each thermal element of the pair of thermal elements have a

different polarity. More specifically, each pair of thermal element is connected

between a different pair of power nodes. As such, each node has one pair of thermal element connected between itself and each other power node, where the thermal elements in each pair are activated by a different polarity of supply power.

[0059] Accordingly, thermal element pair 350 is connected between node 312

and node 322. The thermal element pair 350 includes a first thermal element 332

and a second thermal element 334. The first thermal element 332 is configured in

electrical parallel connection with the second thermal element 334. Further, the first

thermal element 332 is in electrical series connection with a unidirectional circuit

330. The unidirectional circuit 330 may be configured to allow current to flow

through the thermal element 332 in one direction and not in the opposite direction.

As such, the unidirectional circuit 330 is shown in its simplest form as a diode.

[0060] The first unidirectional circuit 330 is shown as a diode with the cathode

connected to node 312 and the anode connected to node 314 through thermal

element 332. In a similar manner, the second unidirectional circuit 336 is shown as

a diode with a cathode connected to node 314 and an anode connected to node 312

through the second thermal element 334, thereby illustrating the unidirectional

nature of the first unidirectional circuit 330 being opposite to the second

unidirectional circuit 336.

[0061] As such, the first unidirectional circuit 330 allows current to flow

through the first thermal element 332 when a positive voltage is applied to node 322

and a negative voltage is applied to node 312, but prevents current from flowing

when a positive voltage is provided to node 312 and a negative voltage is provided

to node 322. In contrast, when a positive voltage is applied to node 312 and a

negative voltage is applied to 322, current is allowed to flow through the second thermal element 334, however, current flow through the second thermal element 334 is prevented by the second unidirectional circuit 336 when the polarity is switched.

[0062] Thermal element pair 352 is connected between node 312 and node

320, thermal element pair 354 is connected between node 312 and node 318,

thermal element pair 356 is connected between node 312 and node 316, and

thermal element pair 358 is connected between node 312 and node 314. As such,

node 312 is connected to each of the other nodes 314, 316, 318, 320, and 322

through a thermal element pair (350, 352, 354, 356, or 358). Similarly, thermal

element pair 360 is connected between node 314 and node 322, thermal element

pair 362 is connected between node 314 and node 320, thermal element pair 364 is

connected between node 314 and node 318, and thermal element pair 366 is

connected between node 314 and node 316. It is noted that the connected between

node 314 and node 312 has already been identified through thermal element pair

358.

[0063] In addition, the connections between each other pair of elements are

provided by thermal element pair 370 being connected between node 316 and node

322, thermal element pair 372 being connected between node 316 and node 320,

thermal element pair 374 being connected between node 316 and node 318, thermal

element pair 380 being connected between node 318 and node 322, thermal

element pair 382 being connected between node 318 and node 320, and thermal

element pair 390 being connected between node 320 and node 322.

[0064] The controller 310 is configured to provide a power connection, a

return connection, or an open circuit to each node. As described above, the multi

parallel topology provides that the thermal element network be considered in whole with regard to power distribution for heating as well as understanding the interaction of all elements for thermal sensing. For example, if a supply power is provided to node 312 and a return connection is provided to node 322, the primary power path would be through thermal element pair 350. However, secondary paths would exist through each of the other elements within the network back to node 322. As such, the controller 310 when providing power and return to any configuration of nodes must consider the power being provided to the thermal element of the primary path as well as the power being provided to all the other elements through the secondary paths.

[0065] Now referring to FIG. 4, another implementation of a bidirectional and

multi-parallel thermal element system is provided. The system 400 includes a

controller 410 which controls a plurality of power nodes. For the implementation

shown, the controller 410 controls six power nodes 412, 414, 416, 418, 420, and

422. As previously discussed, each node is connected to each of the other nodes

through a thermal element. Further, in the bidirectional case, each element is

connected to each other element through two thermal elements, where one of the

thermal elements connects the pair of nodes in a first polarity and the second

thermal element connects the pair of elements in the opposite polarity.

[0066] In the system 400, each unidirectional circuit 430 is shown as a

combination of elements including a SCR 432, a diode 436 and a zener diode 434.

The unidirectional element 430 is in electrical series connection with each thermal

element, for example, thermal element 438. As shown, the thermal element 438 and

the unidirectional circuit 430 are in electrical series connection between node 414

and node 412. If a positive supply voltage was provided to node 414 and a return was provided to node 412, current would be allowed to flow through the thermal element 438 and the SCR 432. The thermal element 438 is connected between node 414 and the anode of SCR 432. The anode of SCR 432 is connected to the thermal element 438 and the anode of diode of 436. The cathode of diode 436 is connected to the cathode of zener diode 434. Further, the anode of zener diode 434 is connected to the source of the SCR 432 and node 412.

[0067] The SCR 432 fires when there is a gate current to the SCR. The SCR

receives gate current when current flows in the direction of the diode 436 and

exceeds the voltage gap of the zener diode 434. Although, the gate current of the

SCR could be triggered by another configuration of devices. Further, the triggering

could be my means other than electrical, for example optical or magnetic. Once the

SCR is activated and conducting current, it does not shut off until the current stops.

While this configuration is shown for exemplary purposes, it is noted that additional

unidirectional configurations may be used. For example, additional elements may

be used in conjunction with the SCR and diodes, for example, to provide a snubber

to prevent inadvertent triggering of the SCR.

[0068] Accordingly, a thermal configuration such as 440 including a thermal

element and unidirectional circuit are provided between each node for example,

node 414 and node 412. Further, in a bidirectional configuration, two thermal

configurations with opposite polarities may be connected between each pair of

nodes of the plurality of power nodes. For example, thermal configuration 440 is

connected between node 414 and node 412, but in an opposite polarity than

unidirectional circuit 430. As can be seen, the cathode of SCR 433 is connected to node 414 while the cathode of SCR 432 is connected to node 412. Therefore, each will conduct only in opposite polarity conditions.

[0069] Within the controller 410, each node may be connected to a pair of

switches, as denoted by reference numeral 492. The pair of switches may be

transistors, for example field effect transistors (FETs) in a half-bridge configuration.

The first transistor 490 may be a low control switch connecting the node 412 to a

return voltage when activated, while the second transistor 491 may be a high control

switch connecting the node 412 to a supply voltage when activated. The first

transistor 490 may have a source connected to a negative voltage line through a

shunt 498 and a drain connected to one of the plurality of nodes. The other

transistor 491 may have the source connected to the node 412 and a drain

connected to a positive voltage node. Further, the first transistor 490 and the

second transistor 491 may each have a gate connected to control circuitry or a

microprocessor implementing control logic. It is also noted that the control system

switching arrangement (e.g. half bridge configuration) can be applied to any of the

topologies applied herein.

[0070] Each other node also has a corresponding pair of transistors.

Specifically, node 414 is connected to transistor pair 493, node 416 is connected to

transistor pair 494, node 418 is connected to transistor pair 495, node 420 is

connected to transistor pair 496 and node 422 is connected to transistor pair 497.

While the control circuit 410 may provide a combination of return, supply power, or

open circuit to each of the nodes independently, at least one node will be connected

to a supply voltage and at least one node will be connected to a return. Various

combinations of supply power, return (e.g. ground), and open circuit conditions can be provided to the nodes. Each combination is a possible mode for powering the thermal element array.

[0071] For each mode or combination of node states, a current will flow

through the shunt 498 and may be measured by the control circuit 410. Further, a

microprocessor may measure the voltage across the shunt or the current through

the shunt to determine electrical characteristics of the thermal element array, such

as the network resistance. For example, the network resistance may be used for

controlling the amount of time each mode is applied, or for modifying other circuit

parameters such as the input voltage, the duty cycle, current, or other electrical

characteristics.

[0072] Now referring to FIG. 5, a thermal array system 500 with addressable

switches is provided. The controller 510 may be connected to a positive node 514

and negative node 516. A power source 512 is connected between the positive

node 514 and the negative node 516. Each thermal element is connected in

electrical series connection with an addressable switch between the positive node

514 and the negative node 516.

[0073] Each addressable switch may be a circuit of discreet elements

including for example, transistors, comparators and SCR's or integrated devices for

example, microprocessors, field-programmable gate arrays (FPGA's), or application

specific integrated circuits (ASIC's). Signals may be provided to the addressable

switches 524 through the positive node 514 and/or the negative node 516. For

example, the power signal may be frequency modulated, amplitude modulated, duty

cycle modulated, or include a carrier signal that provides a switch identification

indicating the identity of the switch or switches to be currently activated. In addition, various commands for example, a switch on, switch off, or calibration commands could be provided over the same communication medium. In one example, three identifiers could be communicated to all of the addressable switches allowing control of 27 addressable switches and, thereby, activating or deactivating 27 thermal elements independently. Each thermal element 522 and addressable switch 524 form an addressable module 520 connected between the positive node 514 of the negative node 516. Each addressable switch may receive power and communication from the power lines and, therefore, may also separately be connected to the first node 514 and/or the second node 516.

[0074] Each of the addressable modules may have a unique ID and may be

separated into groups based on each identifier. For example, all of the addressable

modules (520, 530, 532, 534, 536, 538, 540, 542, and 544) in the first row may have

a first or x identifier of one. Similarly, all of the addressable modules (546, 548, 550,

552, 554, 556, 558, 560, 562) in the second row may have an x identifier of two,

while the modules (564, 566, 568, 570, 572, 574, 576, 578, 580) in the third row

have an x identifier of three. In the same manner, the first three columns 582 of

addressable modules (520, 530, 532, 546, 548, 550, 564, 566, 568) may have a z

identifier of one. Meanwhile, the second three columns 584 may have a z identifier

of two, while the third three columns 586 may have a z identifier of three. Similarly,

to address each module within the group, each addressable module has a unique y

identifier within each group. For example, in group 526, addressable module 534

has a y identifier of one, addressable module 536 has a y identifier of two, and

addressable module 538 has a y identifier of three.

[0075] Now referring to FIG. 6A, a method 600 is provided for controlling the

thermal element array. The method starts at block 610. In block 612 the controller

calculates the set points for each thermal element of the array. For example,

resistance set points may be set for each thermal element such that a measured

resistance for that element can be used as a trigger to stop providing power to that

element. In block 614, the time window for each thermal element is calculated. The

time window may be the time allotted to power a particular thermal element.

Although, if the thermal element resistance is above the set point, the controller may

remain dormant for the remainder of the time window or may directly move to the

next window to power the next thermal element. However, it may be desirable to

have a minimum wait time for each thermal element such that power is not

constantly provided to the system for measurement purposes, thereby heating

elements beyond what is necessary for the heating application.

[0076] In block 616, the controller determines if the end of the time window

has been reached for the current thermal element. If the end of the time window had

been reached for the current element, the method follows line 620 to block 622. In

block 622, the controller increments to the next thermal element within the array and

proceeds to block 616 where the process continues. If the end of the time window

has not been reached the method follows line 618 to block 624. In block 624, the

controller may simultaneously provide power to the thermal element and measure

electrical characteristics of the thermal element. In block 626, the controller

determines if the thermal element has exceeded the thermal element set point

based on the measured characteristics. If the set point has been exceeded, the

method may wait until the timing window is complete or, after some delay, proceed along the line 628 to block 622. In block 622, the thermal element is incremented to the next thermal element and the process proceeds to block 616. If the thermal element has not exceeded the set point based on the measured characteristics, the process follows line 630 block 616 where the process continues.

[0077] Now referring FIG. 6B, a timing diagram illustrating one scenario of the

method 600 is provided. The first element is considered during the first time window

650. The resistance of the first element is denoted by line 654. Again, it is noted

that the resistance of the thermal element may correlate to the temperature of the

thermal element. The set point for the first thermal element is denoted by line 652.

The temperature of the thermal element increases over the first time window 650 as

power is applied to the thermal element. However, the first thermal element is too

cold and does not reach the set point 652, before the first time window 650 elapses.

[0078] During the second time window 656, the controller provides power to

the second element to measure the resistance 658. In this instance, the

temperature and, therefore, the resistance 658 is immediately higher than the

element set point 660. Since the resistance is too high, it is determined that the

element is too hot. Therefore, the second thermal element is immediately turned off

for the remainder of the second time window 656. The controller may remain

dormant for the remainder of the second time window 656 or may, after a predefined

time delay, move to the third time window 662.

[0079] During the third time window 662, a third element is powered and

monitored. The resistance of the third element 664 starts below the set point of the

third element 666. As power is provided to the third element, the resistance

increases as denoted by line 664 until the resistance reaches the set point of the third element 666 as denoted at point 668. When the set point is reached before the end of the time window, the element is turned off and the controller may remain dormant during the rest of the third time window 662. If, as in this example, there are only three thermal elements the first time window may repeat as denoted by reference numeral 670. Here again, the resistance 672 of the first element starts below the first element set point 674. However, the first element has warmed from the last starting point of time window 650. Therefore, the resistance 672 of the first element eventually reaches the first set point 674 at point 676 before the end of the time window 670. The first element having retained some of its energy from its last activation, the applied power was sufficient to reach the set point and turn off before the end of time window 670. Therefore, the controller may remain dormant for the rest of time window 670 or after a predefined time delay leading directly to the time window for the second element. The various time windows will then repeat based on the condition of each thermal element and environmental influences.

[0080] The control method shows the behavior of three positive TCR tuning

layer heating elements under various thermal conditions. Although other

implementations may used, for example negative TCR heating elements in which

case the setpoints would be approached from a higher resistance level. The method

of control is accomplished by calculating the resistance of each element during the

time window assigned for that element utilizing voltage and/or current information

obtained when the element is energized. It should be recognized that the element

resistance may be inferred by measuring only current or voltage as long as the

power is supplied by, respectively, a known voltage or current source. Energizing a

heating element increases its temperature, and thus its resistance rises while it is actively powered. Utilizing previously obtained calibration information, the sampled and active resistance is compared to a previously assigned set point for that heating element. As long as the resistance remains lower than the assigned set point, the element remains energized until the end of the assigned time window; or, if the element resistance is above or rises above its target set point resistance, the element is immediately turned off and remains off for the remainder of the assigned time window. Each element becomes active in sequence, and then the cycle begins again and repeats continuously.

[0081] Time windows need not be of fixed duration. It is sufficient that the

system dissipates enough energy from each element such that the minimum "On

time" required for the first measurement does not contribute more energy than can

be dissipated by the system before that element again becomes active, and that

sufficient energy can be supplied during the maximum "On-time" such that the

average temperature of each element can be increased for the control system to

assume control during its active window. Steady-state control is achieved when all

heating elements in the tuning layer consistently reach their individual set points

during their assigned time windows. Efficiency of control is achieved by choosing a

minimum set point range for the tuning heater layer, sufficient supplied power, short

time window duration, fast sampling, and the minimum required number of elements.

[0082] Now referring to FIG. 7a, another method for controlling the thermal

array is provided. The method starts in block 710, where the resistance set points

are calculated for each mode, along with a power command for each thermal

element. In block 712, the time period for each mode is determined. In block 714,

the mode is set to a first mode or initial mode. In block 716, the controller applies the current mode to the heater array. In block 718, the controller waits for the end of the time period continuing to provide power as defined by the mode. In block 720, the mode is incremented. In block 722, the controller determines if the current mode is the last mode of the sequence. If the current mode is not greater than the total number of modes in the sequence, the method follows line 724 to block 716, where the current mode is applied and the method continues.

[0083] Referring again to block 722, if the current mode is greater than the

total number of modes in a sequence, the method follows line 726 to block 728. In

block 728, the controller determines whether the system needs to determine

temperature at the thermal elements, for example by measuring characteristics of

the thermal elements. The control system may measure the thermal characteristics

based on various algorithms including the predetermined number of sequences,

based on a time period, or based on identified environmental characteristics. If the

temperature does need to be measured, the method follows line 734 to block 736,

where the temperatures are determined as described elsewhere in this application.

The method then follows line 738 to block 732. Alternatively, if the temperatures do

not need to be measured in block 728, the method flows along line 730 to block 732.

In block 732, the controller waits until the allotted sequence time has passed. It may

be important for the system to wait for the allotted sequence time, otherwise

additional heat may be added to the system faster than anticipated which may

compromise stability of the algorithm. The method then proceeds to block 740.

[0084] In block 740, the controller determines whether the power command

has changed, based on the measurement. Accordingly, an algorithm such as a PID

algorithm adjusts the power command, as denoted in block 742 based on the measurement performed by the controller in block 736. The algorithm in block 742 may determine the adjusted power command and provide information that the power command has changed to block 740. If the power command has changed in block

740, the method follows line 746 to block 712 where the time periods for each mode

are recomputed. The method then continues. If the system characteristics have not

changed, the method follows line 744 to block 714 where the control system resets

to the first mode and the method continues.

[0085] One specific example is provided for a system having four nodes 750

with six thermal elements 752 as shown in FIG. 7b. A multi-parallel array may be

comprised of an n-wire power interface, connected to a number of heaters such that

every possible pairing of control wires has a single heater connected between them.

It can be easily shown that the number heaters that can be connected in this way is

equal to n(n-1)2.

[0086] The development discussed with regard to FIG. 7b assumes a

normalized system, in which heater resistances are all one ohm and control lines are

driven at 1 volt, zero volts, or are open-circuited (high impedance). However, the

system can be scaled using the equations presented here to a system with other

voltages and resistances.

[0087] This method, in one implementation, partitions the control into two

parts, that is, a constant part and a deviation part, in which the constant part is equal

for all heaters, and the deviation part is equal and symmetric for all heaters. Other

control partitions are be possible that can provide for greater flexibility in the control.

For example, a system might be partitioned into two different constant parts and a

single deviation part, allowing for two distinct control zones at different mean power levels. Also, the system might be partitioned into a single constant part and two deviation parts to give greater range of control in a subset of the heaters. Note that regardless of the partitioning, it is possible to apply control vectors where the constraints on c can be violated, and yet control is possible even though stable control cannot be guaranteed.

[0088] In an implementation of this method, it could be advantageous to

maintain different sets of control constants, and switch between them dynamically in

order to better match system behavior to different operating conditions.

[0089] A mode table may be constructed for the system. Power may be

computed for each power supply and heater, for each unique combination of power

application to the array. These values may be stored in the mode table.

[0090] Below is a 4-node system mode table. Locations with "nan" indicating

open-circuit lines. For example, Mode #11 has ground connected at V1 and V4

(producing zero power), power connected at V3 (producing 2.67 watts), and V2 is

open-circuit.

1 4-GM amg au ag a2.0 .0 1 au a. 1ug 1.g 2 4-.M a au a.. aug 1ao alm Lug jug a.0 jug 3 4-GM amG a.g aug aug alm 10 Ia 1u tu aug 4- 3.0 amg .00 a.0 a.0 tu a1g amg t00 tug a.u 5 3.ao aao lug tug tug 121 10o tao aug aug aug a a. am .m 3a.W a.uG amo tao ao jug a.uG ju 7 3.ao ag aug aug 3.g alo alm t aug jug jug S 2.67 in g.ug g.u 2.67 a all G.44- g.ug 1u ug 3 2.67 Mn aug 2,67 aug a a44 anl 1Wg aug u 10 2.67 aug nan aug 2.7 an aGa 0.11 0.44 1.g 3 27 aug nan 2.67 tao a 1 aug 0.44 0.11 tug 2 27 aug 2.67 nan ag 1o an aug 0.44 10u 0.11 13 27 G 2.67 aug nan 1o Ga o 11 0.44 0.11 14- 27 aug au nan 267 Ug anl 0.11 n 0.44 15 27 aug au 2.67 nan aao to an 1u 0.11 0.44 36 2.67 nan aug 1.33 133 a4 al al tu tug au 17 2.67 aug nan 133 133 GA44 tg tg 0.1 0.11 a n2 2.67 aa 1.33 nan 133 1 G44 1a 0.1 an .11 s 2.67 N 133 13aug aun ao aM a44 a0 aa1 aug 2z 2.0 nan n a.0 2.0 Ulm U.2 U.25 0,25 0,25 100 a] a.ao Mn aug Mn a.ug aa2 aao a25 0,25 1u 0.25 22 a.ao on aug ag MNn aa2 aa2 aao 1u 025 .25 23 2.ao aao nan nan a.g a25 a25 i a. 0.25 0.25 24- 2.ao nan .g nan 25 M U25 0.25 . 0.25 25 2.a aao a.ug nan nan 1o a25 a25 0.25 aa5

[0091] From the mode table, construct a matrix A comprised of heater powers

for a subset of modes. This matrix must be at least rank n, where n is the number of

heaters in the system. One optimal selection of modes results in A having low matrix

condition number, maximum average total power, maximum available power

deviation, and a minimal number of modes.

[0092] As an example, choosing modes 1-10 gives the following:

-1 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0.11 0.11 0.44 0 1 1 0.11 0.44 0.11 1 0 1 -0.11 0 1 0.11 0.44 1

[0093] Note that this matrix is not a minimal-row solution, nor does it have the

lowest condition number of other solutions, but it does represent a controllable

system.

[0094] From this matrix, a power control algorithm can be constructed as is

shown below.

[0095] Notation conventions used in below:

matrix (upper case bold italic)

vector (lower case bold italic)

scalar (lower-case italic)

vector with 1's in every position

element-wise matrix division operator

[0096] Average heater power p can be controlled using a generalized duty

cycle vector d, where

0 !; dt! Y.dt < 0 5de 1and 1=

and where the modes X are applied to the array for times so that

ATd p

[0097] It can be shown that if we select d as

d = H(fi+ pAc) = fH1+ pHc

where c is an nx1 control vector whose elements satisfy-,

and where P and PA are constant mean power and deviation power parameters, and

H is the Moore-Penrose pseudo-inverse, i.e., H = pinv(AT) , then we will get a fixed mean control level in each heater summed with a deviation level that is proportional to the control vector elements, as follows: p=A pp =fl+PAC

[0098] Values for P and PA can be selected arbitrarily, but subject to the

following constraints:

1 PA I1FI1 H 111

ft pAmax(IHIY + HT)

[0099] To get the maximum possible deviation PA, we set the right-hand sides

of the above inequalities equal and then solve for and PA

max(IHI -- H )

1HTimax(HY +Hi) + YH|Y

THimax(|H|I+"-- HY)L + |1'I|Y4

ArA

[00100] For the example in Fig 7b, the pseudo-inverse of A to produces H -0.199432 0.176632 0.173926 0.163697 0.169614 -0.297939 0.153326 -0.241645 0.235286 0.148082 -0.301471 0.242824 0.215387 0.214565 -0.286556 -0.290792 0.211658 0.214995 -0.126356 -0.152259 0.138518 -0.097446 0.156789 0.261924 =pinVAT)- -0.149469 0.143359 -0.132658 0.159100 -0.127411 0.2722881 0.160492 -0.126985 -0.169760 0.168541 0.262082 -0.159336 0.284613 0.285435 0.286556 -0.209208 -0.211658 -0.214995 0.138044 0.188285 -0.061245 0.182287 -0.063245 0.024007 0.186182 -0.131370 -0.065526 0.183376 0.039389 -0.083488 0.117500 -0.074486 0.179800 -0.045754 0,189377 0.014794

[00101] Then the values of P and PA may be computed as described above:

- max(|I +HY )

~hTnimax(IHIT HI?) +T11i

":THTm ax(HI I-H ) + ITHIT= 0.063065

[00102] The equation for the duty cycles may be solved as a function of c using

d = H( + pAc) = 1HI + p MHC

to get: R0.91210 -1.2577e - D02 1.1139e - D02 1.D969e - D2 1.0324e - D02 1.D697e - 0D2 -1.769e -002 D.115617 9.6695e - DD3 -1.5239e - 002 1.4836e - D2 9.3386e - 003 -1.9012e - D02 1.5314e- D02 D.136576 1.3563e - DD2 1.3531e - D02 -1.8D72e - D02 -1.339e - 002 1.3348e - 0D2 1.3559e- DD2 R.088604 -7.9686e - D03 -9.6022e - 003 8.7356e - 003 -6.1454e - 003 9.8876e - 03 1.6518e- D02 D.D80799 -9.4262e - D03 9.D409e - 003 -8.3661e - D03 1.DD34e - D02 -6.0352e - D03 1.7172e- D02 D.D66D41 + 1.D121e- DD2 -8.0083e - 003 -1.0706e - D02 1.0629e - D02 1.6528e - 0D2 -1.D049e -002 c D.107959 1.7949e - DD2 1.8DOe - D02 1.8072e - 0D2 -1.3194o - 002 -1.3348e - D02 -1.359e -002 0.064579 -8.7D57e - D03 1.1874e - D02 -3.8624e - D03 1.1496e - D02 -3.9885e - D03 1.514De -DD3 0.062877 1.1742e - DD2 -8.2848e - 003 -4.1324e - D03 1.1565e - D02 2.4841e - 003 -5.2652e- 003 0.071518- 7.4101e - D03 -4.6975e - 003 1.1339e - 0D2 -2.8855o - 003 1.1943e - 0D2 9.330e- DD4

[00103] A time quantum T may be chosen that can be implemented in the

controller, e.g., one microsecond. Also choose a base control loop period T for the

system that is sufficiently smaller than the thermal time constant of the heater

system, e.g, 1 second.

[00104] A time period (e.g. in the form of a duty cycle) may be defined as

dc = round(') = round(1,000,000d)

and substitute in the equation for d to get the following: 91210 -12577 11139 10969 10324 10697 -18789 115617 9669 -15239 14838 9339 -19012 15314 136576 13583 13531 -18072 -18339 13348 13559 68604 -7969 -9602 8736 -6145 9888 16518 80799 -94262 9041 -8366 10D34 -8035 17172 c 66041 10121 -8OOS -10706 10629 16528 -10D49 107959 17949 18001 18072 -13194 -13348 -13559 64579 -8706 11874 -3862 11492 -3989 1514 62677 11742 -8285 -4132 11565 2484 -5265 -71518 -- 7410 -4697 11339 -2885 11943 933

[00105] This equation can be implemented in the controller as a pair of

constant coefficient matrices along with a function that computes the duty cycles dc

from the control vector c (which is a vector of floating point values).

[00106] In order to implement the control, we also need to know the modes

corresponding to the rows in A, which in our example comprises the first ten rows of

the mode table as shown below.

Moe tleiJ j 1l Al LApLpErlfl pEr2S4 prr141 pr25 r241 r41 3 4,W0 Q00 I.M I.M G.00 IM 1M00 G .00 1M 10M 2 4,40 CLC1U 2,O0 2.0 2.WO t.00 t(00 C1UI 1M L.U 10 9 4,W0 aG. . 2,oo zoo 2.Wo 1IM 1IM 1W0 1o o .oo 4. 4- 3.M0 3.lG EG (G 3.LM 1OU .00 (1OU 0(. (.OU 10Q 1(10 Um 10 1.G (10 1.M .O0 1.M 0.00 (.00 (.OU 5 13M1 (am IOU IOU OU 1( 1(1 m (LOU (LOU (LOU 6 3.M U.U QU Au (GG G 1U U.U 100 (LOU 10(M 7 3.MQ ag LWO (LO 3.CG CUQ age maa LWO I.0 I0 2 2.67 nan (.0 0.00 2.67 U.11 U.11 9.44 .O 1.00 100 3 2.67 nan (.O 2.67 .OU1 U2I(44 U.11 1W0 (.O 1OU 1G 2.7 (GL nan U.OU 2.67 0.II GMG IM 0.11 0.44 1OU

[00107] Because a practical hardware implementation will use half-bridge

drivers on each of the power wires, it is sufficient simply to know whether a line is to

be driven high, low, or open-circuited. Thus, we can construct the output modes by

inspection of the power values for each of the drive wires, where zero power is a low

drive, non-zero power is a high drive, and "nan" power is open circuit. The result, for

our example, is as follows:

ds? i V2 VX u V I law ~ ha~law 2 law law a law la hs hg 4- law h law law & law ht h hi S Lw lw law 7 law lv Law 8 cpgn Lw law rl 3 apen law hgd low ]a law open law h!h

[00108] Execution of control may proceed according to the following

pseudocode:

initialize timer M with a time quantum of7? start timer M do set cmp = 0 set i = 1 get the current value of c and compute dc set M's count value to zero do apply mode m; to the system cmp = cmp + dc[i] while M's count value is less than cmp do loop i=i+1 while i is <= the number of elements in dc turn off all outputs T while M's count value is less than do loop loop

[00109] Now referring to FIG. 8, a method 800 for measuring resistances is

provided. In particular the method 800 may be particularly useful with the method of

FIG. 7a (e.g. block 736). In block 810, the characteristic for example, may be

assigned a null vector and the mode may be set to the first mode. In block 812, the

controller applies the active mode to the thermal array. In block 814, the controller

measures the amount of current provided into the array for the active mode. In block

816, the controller indexes to the next mode to make it the active mode. In block

818, the controller determines if the active mode is greater than the total number of

modes. If the active mode is not greater than the total number of modes, the

method follows line 820 to block 812, where the next mode is applied to the thermal

array.

[00110] Referring again to block 818, if the active mode is greater than the total

number of modes, the method follows line 822 to block 824. In block 824, the

controller determines the current for each thermal element based on the current

applied to the active mode and the relationship of the resistances. The method then

proceeds to block 826, where the resistance for each thermal element is determined

based on the voltage provided to the system and the current that is allocated to each

thermal element. From the resistance measurement, the controller can then

determine a temperature of each thermal element according to a temperature

resistance relationship that is stored for each thermal element.

[00111] While in some implementations, the system may measure the current

applied to the mode to calculate the resistances of each thermal element. In some

implementations, the system may also or alternatively measure other parameters

such as the voltage at each of the nodes. Obtaining additional measurements can

help to over constrain the relationship and a least squares fit may be used to

determine the resistances. Over constraining the relationship may reduce the error

in the calculations and provide more reliable resistance values for each thermal

element. While this may be applied to the batch processing method of FIG. 7a and

7b, this could equally be applied to the indexing method described in relation to FIG

6a and 6b.

[00112] While the resistance may be used to calculate temperature information

at the thermal element, the power provided to the thermal element and/or thermal

array as a whole can be used to calculate heat flux at the thermal elements. In

some implementations this information may be used as feedback, for example

changing process parameters for a power setpoint. In some implementations, these characteristics may be used as feedback to an external process, for example, to control other environmental variables such as processing time or other process characteristics in manufacturing processes. One example, could include adjusting processing time in the semiconductor manufacturing process to increase chip yield.

Another example, could include providing a system diagnostic for system

degradation.

[00113] In some implementations, the thermal element acts as just a heater, in

other implementations, the thermal elements may act as heaters and thermal

sensors, or even in other implementations just as thermal sensors. In

implementations where the thermal elements are utilized as only sensors or are

switched between sensor and heater during non-overlapping time periods, the

sensing may be accomplished with a low voltage supply and/or a low power supply

(e.g. short time period).

[00114] The thermal array may be powered with a low amount of power to

acquire the measurement without significantly disturbing the temperature of the

thermal element. For example, the thermal array may be powered with a voltage

capable of causing less than 5% change in temperature for the temperature being

measured during the time period applied. In one example, a low average power is

provided by a pulse power provided for less than one second.

[00115] In other implementations, the controller may create an alert based on

the measured resistance (temperature) and/or power (heat flux) of each thermal

element or a combination of thermal elements. The alert may take many forms

including a visual alert, audible alert, a control signal, a message (e.g. a text or

email).

[00116] One specific example of measurement is provided with regard to the

system having four nodes and six elements in FIG. 7b. Using this topology, a

temperature measurement array may be enabled. Multiple thermal elements can be

used as RTD sensors to measure with fewer electrical connections (nodes) by using

a single integrated measurement system to compute the temperature for an entire

array of sensors. Through rapid sequential measurements of low power applied in

various combinations to one or more nodes (called Power Modes), all sensor

resistances can be computed and converted into temperature. Further, it is noted

that different modes may be used for powering than the modes that are used for

measuring the thermal array.

[00117] The following variables are defined:

nNodes = N #nodes, N>2, because N=2 is for a single, stand

alone RTD

nSensors = N x (N-1)/2 #sensors that can be connected between

different node pairs

iModes = 2N-1-1 # power modes (no floating nodes,

redundancies, or 0-vectors)

[00118] Next, a Power Mode matrix is defined of size iModes x nNodes, which

holds all combinations of each node powered with V+ or 0, but where the last node

is always 0 (e.g. return or ground). If we normalize V+ to equal 1, then the Power

Mode Matrix is just a binary table (because nodes must be either 0 or 1). The Power

Mode Matrix [M] (for nNodes N>5) is illustrated as follows column1 = least

significant bit]: mode#

00... 000 1 010.. .000 2 110... 0 00 001.. .0 0 4

[M 111 . .. 0 00 7

0 01.. . 110 2 1 01 .. . 1 102 011.. .1102-2 1 1 . . . 1 1 0 2 1

[00119] A Routing matrix [R] may then be formed from the absolute difference

between all node pairs for each Power Mode in [MJ. This results in [R] of size

iModes x nSensors which is not square for N>3 and not optimum for N>5. Using a

subset of available modes the matrix condition of [R] for N>5 can be reduced, which

may reduce the time of calculation and calculation error. For N>5, a minimum

condition [R] is achieved by using only modes of [MJ where two nodes are

simultaneously active and where N-2 nodes are simultaneously active.

[00120] The governing equations for the table above (for N>5) are:

The number of modes with two active nodes = (N-1) x (N-2)/2.

The number of modes with (N-2) active nodes = (N-1).

Using the reduced set of modes for N>5 results in a square

Routing matrix where #Sensors = #Modes, and the matrix condition of [R] = N-2.

[00121] The following pseudocode computes [R] from [M]:

R=zeros(nSensors,nSensors) Initialize the Routing Matrix

for i=1:nSensors The reduced number of modes

m=0

forj=1:nNodes-1 The number of system nodes less one

for k=j+1:nNodes

m=m+1

R(i,m)=abs(Mode(ij)-Mode(i,k)) Nonzero= current flow

end

end

end

[00122] For example: if N=6, there are 31 available modes and the mode

numbers with 2 active nodes are: 3 5 6 910 12 17 18 20 24, and the mode numbers

with N-2 active nodes are: 15 23 27 29 30

[00123] The resulting Routing Matrix [R] for N=6 is given as follows, where

each row is a mode [3 5 6 9 10 12 15 17 18 20 23 24 27 29 30], and each

column is a sensor.

0 11 11 1 1 11000000 100 1 1 1 1 00 1 10000 1 111 1 1000

[R]= 0 1 00 10 0 0 10

1 1 1 0100 100 1 0101 1 00 1 01 1 01 01 0101 1 1 1 1 1 0 1 0 101 0 101 1 1 0 1 01 01 01 01 01 101 001 01 01 01 1 01 101 001 100 1 101 1Q01 1

[00124] Thermatrixx above isnsquare,containsonlyones and zeros,and has

amatrixcondition of4,so itcanbeinvertedwithlowerror. The governing equations

for this sensing system are givensinimatrix formcasnfollows:

[is]=inv R -im]

[Note: If N=4 or 5,nSensors »nModes, the pseudo-inverse of([RJis used].

[00125] Where [MIisa vector of individual measurements of total current into

the sensor array for aeach Power mode; and [is]is avector of the equivalent sensor

currents if the sensors were individually driven with no cross coupling. This

procedure works as long as sensor resistances remain substantially constant

throughout the time it takes to cycle through all modes in the set.

[00126] First, a vector of baseline sensor conductance may be computed as

follows while holding the sensor array at a baseline temperature To (for example

25°C)

[00127] Next, measuring at some unknown temperature, a new vector is:

[00128] Using the sensor material's Temperature Coefficient of Resistance

(TCR), an element-wise sensor conductance ratio vector is calculated and applied to

the following equation to obtain the unknown sensor temperatures:

[&WA~',a- - L1T Tea

[00129] As such, go and gT can be extracted for known V; or if on a per-node

basis, V in the baseline measurements is the same as V for the unknown

temperature measurements, the element-wise ratio of the current vectors can be

substituted directly into the equation above. Note: There is no restriction for baseline

conductance variations in the first measurement or temperature variation between

sensors in the second measurement.

[00130] A method 900 is provided in FIG. 9a for calibrating the array and a

method 950 is provided in FIG. 9b for calculating target set points. The method 900

and the method 950 may be particularly useful with the indexed control method of

FIG. 6a (e.g. block 612) and the batch control method of FIG. 7a (e.g. block 710).

[00131] The method 900 begins in block 910. In block 912, the controller fixes

the array temperature to a base line temperature, for example 250 C. In block 914,

the controller determines whether the control process is controlling individual

elements or if the elements are configured into a multi-parallel arrangement and are

being controlled in a batch. If the elements are being measured in a batch, the

method follows line 916 to block 918. In block 918, a batch measurement

procedure, for example as described with regard to FIG. 8, may be used to gather batch measurements and transform the batch measurements to the individual element characteristics, which are then stored in a calibration baseline vector [R].

The method then follows line 924 to block 926 where the method ends.

[00132] Referring again to block 914, if the individual elements or

characteristics are measured for example, in an indexing mode, the method flows

along line 920 to block 922. In block 922, the individual element characteristics are

measured directly and stored in a calibration baseline vector [RO] as denoted by

block 922. The method then proceeds to block 926 where the method ends. In

alternative methods, the resistances could be manually measured for instance with

an ohm meter.

[00133] Method 950 begins in block 943. To compute the target setpoints, in

block 944 an operator provides temperature set points for each element or mode,

then the method proceeds to block 946. In block 946, the controller calculates the

element temperature above the base line temperature and stores the difference for

each element in a vector. In block 928, the controller applies the temperature

coefficient of resistance (TCR) to the stored vectors to generate an element target

resistance vector. The method then follows to block 930. If the thermal element

array is a bidirectional array, the method follows line 940 to block 938. If the thermal

element array is a multi-parallel array, the method follows line 932 to block 934. In

block 934, the element target resistance vector is transformed into an array target

resistance vector for each unique power mode. The method then follows line 936 to

block 938 where the target resistances may be converted to target voltages or target

currents based on the system voltages and currents. The method then proceeds to

block 942 where the vector of target voltages or currents corresponding to each power mode is the output of the target setpoint calculation method. The method ends in block 948.

[00134] One implementation of this method is described below with respect to

the four node topology of FIG. 7b. The thermal elements may be heating elements

made from high TCR materials so the heater control algorithm may be used, but

without the diodes or SCRs. Nodes are powered sequentially with one source and

one return, leaving the other nodes floating. This provides one dominant current path

for control if the resistances of the thermal elements are substantially similar.

However, the dominant current path is in parallel with one or more secondary paths

of two or more heating elements in series. The secondary pathways in this system

can be likened to cross coupling terms of a multiple-in/multiple-out control system.

For good control the cross coupling terms should not dominate the system, for

instance, by keeping the heating element resistances similar to each other.

[00135] The following variables are defined for the 4-node system shown in

FIG 7b.

nNodes = N #nodes, N>2, because N=2 is for a single heater

nHeaters = N x (N-1)12 #independent heaters that can be

connected between nodes

nPairModes = nHeaters #independent node pairs, other nodes float,

no redundancies

[00136] Because current into the system must equal current out of the system,

a Power Mode Matrix of size nPairModes x nNodes may be definded, where, for

each Mode (row) a '1' represents current flowing into one Node (column), '-1' represents current flowing out of another node, and '0' represents a floating node.

Note that the number of PairModes equals the number of heating elements.

1 -1 0 0 1 0 -1 0 1 0 0 -1

[M] = o i o -1 o D 1 -1

[00137] Also, a Vector [G] and a square Node matrix [GNJ may be defined

from heating element resistances:

1/R12 1/R13 1/R14

[G]= 1/R23 1/R24 1/R34 .

01+G2+G3 -G1 -G2 -G3

[GN]= -G1 G1+G4+GS -G4 -G5 -G2 -G4 G2+G4+GO -G -G3 -GS -G G3+G5+Go

[00138] To start the process, the baseline (e.g. 250 C) resistances of the

heating elements may be obtained, either by independent measurement or by the

method outlined above with regard to FIG 8.

[00139] Next, the target resistances of each of the heating elements at their

target temperature can be established to serve as the control points. It is recommended, where possible, that the target resistances at temperature be within

±30% of the mean to limit cross-coupling. The following formula may be used to

compute the target resistances:

RT=Ro X [1 + TCR x (TT-T)]

Where

Ro is the baseline resistance of a particular heating element

To is the baseline temperature corresponding to the resistance Ro

TT is the target temperature for that particular heating element

TCR is the temperature coefficient of resistance applicable for (TT-To)

[00140] The previously defined Conductance Node Matrix [GNJ may be

computed next.

[00141] Then, (nNodes-1) sub-matricies of [GNJ can be created by eliminating

one row-column starting with row-column 2. These matricies represent the systems

where the deleted row-column number is the grounded node of [MJ.

[00142] Next, nNodes-1 current vectors can be created with '1' in each of the

available bins and '0' in the others. For example in the 4-node system:

[00143] [11] = [1 00]T [12 =[0 1 T 3 =[0 0 1]T

[00144] nPairMode Voltage Vectors may then be created from each unique

combination of the [GNJ submatricies and current Vectors [11], [12], and [13] as follows:

[V]PairMode = [GNJn-1 X [Im]

[00145] The maximum from each Voltage vector may be retained and

assemble into a new Vector [Vn] in the order of the Mode Matrix [MJ, where the

current vector is represented by the '1', and [GN]n is represented by '-1' for the

eliminated row column.

[00146] The control loop may be closed for each mode by sequentially applying

current source and sink to a mode pair defined by [MJ, measuring the resulting

voltage across that pair while leaving power applied until the measured voltage

converges to the target voltage for that mode, or until a previously defined 'time-out'

requires sequencing to the next mode pair. Target Voltages are per amp of current

applied. Too much current causes divergence, too little current prevents closed loop

control. The convergence region for power is controlled by the ratio of minimum On

Time to Time-Out.

[00147] For one specific example if provided for the four node system having

six heating elements with the following resistances at 25°C:

R 0= [22.1858 20.2272 20.8922 21.3420 23.1205 20.0585]T

[00148] Assume a 70/30 Nickel-Iron heating element with a linear TCR of

0.5%/C and a target temperature for each element of 10 degrees over ambient. The

target resistances are then calculated for the desired temperature rise by increasing

each resistance by 5% (0.5% x 10):

RT= [23.2951 21.2385 21.9368 22.4091 24.2766 21.0615]T

[00149] The Conductance Matrix is based on the reciprocal of [RT:

0.1356 -0.0429 -0.0471 -0.0456

[GNJ= -0.0429 0.1287 -0.0446 -0.0412

-0.0471 -0.0446 0.1392 -0.0475

-0.0456 -0.0412 -0.0475 0.1343

[00150] The six Voltage Vectors are then:

1-9356 -0.0471 -0.0456 -0.0471 0.1392 -0.0475 x 0 -0.0456 -0.0475 0.1343 0

2=0.1356 -00429 -0.045' - I -0.0429 0.1287 -0.0412 x 0 -0.0456 -0.0412 0.1343 0

[V3]= 01356 -00429 -0.0471 - 1 -0.0429 0.1287 -00446 x 0 -0.0471 -0.0446 0.1392 0

[IV4] = 0.1356 -00429 -0.045 0 -0.0429 0.128T -0-0412 x 1 -0.0456 -0.0412 0.1343 0

[V5] = 0.1356 -00429 -0.0471 - 0 -0.0429 0.1287 -. 446 x 1 -0.0471 -0.0446 0.1392 0

[V6] = 0.135 -0.0429 -0.I471 I0 -0-0429 0.128 -00446 x o -0.0471 -0.0446 0.1392 1

[00151] The Target Voltage per amp for the control loop for the 6 modes [M] is

the maximum from each vector above:

[VT] = [11.431 10.844 11.080 11.218 11.587 10.862]

[00152] Any of the controllers, control systems, or engines described may be

implemented in one or more computer systems. One exemplary system is provided

in FIG. 10. The computer system 1100 includes a processor 1110 for executing

instructions such as those described in the methods discussed above. The

instructions may be stored in a computer readable medium such as memory 1112 or

storage devices 1114, for example a disk drive, CD, or DVD. The computer may

include a display controller 1116 responsive to instructions to generate a textual or

graphical display on a display device 1118, for example a computer monitor. In

addition, the processor 1110 may communicate with a network controller 1120 to communicate data or instructions to other systems, for example other general computer systems. The network controller 1120 may communicate over Ethernet or other known protocols to distribute processing or provide remote access to information over a variety of network topologies, including local area networks, wide area networks, the Internet, or other commonly used network topologies.

[00153] In other embodiments, dedicated hardware implementations, such as

application specific integrated circuits, programmable logic arrays and other

hardware devices, can be constructed to implement one or more of the methods

described herein. Applications that may include the apparatus and systems of

various embodiments can broadly include a variety of electronic and computer

systems. One or more embodiments described herein may implement functions

using two or more specific interconnected hardware modules or devices with

related control and data signals that can be communicated between and through

the modules, or as portions of an application-specific integrated circuit.

Accordingly, the present system encompasses software, firmware, and hardware

implementations.

[00154] Further, it is noted that any of the topologies described may be used

with any of the processing methods. Additionally, any the features described with

respect to one topology or method may be used with the other topologies or

methods.

[00155] In accordance with various embodiments of the present disclosure, the

methods described herein may be implemented by software programs executable

by a computer system. Further, in an exemplary, non-limited embodiment,

implementations can include distributed processing, component/object distributed processing, and parallel processing. Alternatively, virtual computer system processing can be constructed to implement one or more of the methods or functionality as described herein.

[00156] Further, the methods described herein may be embodied in a

computer-readable medium. The term "computer-readable medium" includes a

single medium or multiple media, such as a centralized or distributed database,

and/or associated caches and servers that store one or more sets of instructions.

The term "computer-readable medium" shall also include any medium that is

capable of storing, encoding or carrying a set of instructions for execution by a

processor or that cause a computer system to perform any one or more of the

methods or operations disclosed herein.

[00157] As a person skilled in the art will readily appreciate, the above

description is meant as an illustration of the principles of the disclosure. This

description is not intended to limit the scope or application of the disclosure in that

the disclosure is susceptible to modification, variation and change, without

departing from spirit of the disclosure, as defined in the following claims.

Claims (19)

CLAIMS We claim:

1. A thermal system comprising:

a plurality of thermal elements;

a control system having a plurality of power nodes, wherein the thermal

elements are connected the plurality of power nodes, the control system is

configured to calculate target setpoints for the thermal elements based on

temperature set points, and for each thermal element, the control system is

configured to (a) provide one of a power, a return and an open circuit condition to the

thermal element, (b) sense an electrical characteristic of the thermal element by

measuring the electrical characteristic across the power nodes connected to the

thermal elements, and (c) determine if the thermal element exceeds a target setpoint

for the thermal element based on the sensed electrical characteristic.

2. The system of claim 1, wherein the control system is configured to

determine a time window for powering each thermal element of the plurality of

thermal elements based on the target setpoint for the thermal element.

3. The system of claim 2, wherein the control system is configured to

discontinue providing power to the thermal element for a remaining portion of the

time window when the target setpoint is exceeded.

4. The system of claim 2, wherein the control system is configured to

discontinue providing power to the thermal element and move to the next time window after a predetermined time delay when the target setpoint is exceeded.

5. The system of any one of the preceding claims, wherein calculating the

target setpoints includes measuring a baseline resistance of the thermal elements.

6. The system of claim 5, wherein calculating the target setpoints includes

calculating a target resistance based on the baseline resistance, a temperature

change, and a temperature coefficient of resistance (TCR) for each thermal element.

7. The system of any one of the preceding claims, wherein the thermal

element is a dissipative element.

8. The system of claim 7, wherein the thermal element is a resistive

element.

9. The system of claim 8, wherein the thermal elements are comprised of

an electrically conductive material with a temperature dependent electrical

resistance.

10. The system of claim 9, wherein the control system is configured to

measure the resistance of the resistive element across the power nodes connected

to the resistive element to calculate a temperature of the resistive element.

11. A heater comprising: a base plate; a base heater secured to the base plate; a substrate secured to the base heater; a tuning heater secured to the substrate, the tuning heater comprising a plurality of heater elements; a chuck secured to the tuning heater; and a control system having a plurality of power nodes, wherein the heater elements are connected to the plurality of power nodes, the control system is configured to calculate target setpoints for the heater elements based on temperature set points, and for each heater element, the control system is configured to (a) provide one of a power, a return, and an open circuit condition to the heater element, (b) sense an electrical characteristic of the heater element by measuring the electrical characteristic across the power nodes connected to the heater elements, and (c) determine if the heater element exceeds a target setpoint for the heater element based on the sensed electrical characteristic.

12. The system of claim 11, wherein the control system is configured to

determine a time window for powering each heater element of the plurality of heater

elements based on target setpoint for each heater element.

13. The system of claim 12, wherein the control system is configured to

discontinue providing power to the heater element for a remaining portion of the time

window when the target setpoint is exceeded.

14. The system of claim 12, wherein the control system is configured to

discontinue providing power to the heater element and move to the next time window

after a predetermined time delay when the target setpoint is exceeded.

15. The system of any one of claims 11 to 14, wherein calculating the

target setpoints includes measuring a baseline resistance of the heater elements.

16. The system of claim 15, wherein calculating the target setpoints

includes calculating a target resistance based on the baseline resistance, a

temperature change, and a temperature coefficient of resistance (TCR) for each

heater element.

17. A thermal system comprising:

a plurality of thermal elements;

a control system having a plurality of power nodes, wherein the thermal

elements are connected to the plurality of power nodes, the control system operates

the plurality of power nodes in a plurality of modes in which a given node is

selectively connected to one of a power, a return, and an open circuit condition, and

each mode of the plurality of modes represents a different combination of the

plurality of nodes being connected to the power, the return, and the open circuit

condition,

the control system is configured to calculate target setpoints for the

thermal elements based on temperature set points, and for each mode, the control

systems is configured to (a) provide power to the thermal elements according to the mode, (b) sense an electrical characteristic of the mode by measuring the electrical characteristic across the power nodes connected to the thermal element, and (c) determine whether each thermal element exceeds a target setpoint for the thermal element based on the sensed electrical characteristic.

18. The system of claim 17, wherein calculating the target setpoints

includes measuring a baseline resistance of the thermal elements.

19. The system of claim 18, wherein calculating the target setpoints

includes calculating a target resistance based on the baseline resistance, a

temperature change, and a temperature coefficient of resistance (TCR) for each

thermal element.