AU2008202571B2 - Silicon Single Electron Device - Google Patents

Abstract

Abstract This invention concerns a silicon integrated circuit device capable of creating quantum confinement of semiconductor dots, and capable of operation at radio frequencies (rf) as a sensitive electrometer. In another aspect the invention concerns a method of making the device. In one important embodiment the invention is a silicon single electron transistor (SET). i18

Description

I AUSTRALIA Patents Act 1990 QUCOR PTY LTD COMPLETE SPECIFICATION Invention Title: Silicon Single Electron Device The invention is described in the following statement: Title Silicon Single Electron Device 5 Technical Field 'Tis invention concerns a silicon integrated circuit device capable of creating quantum confinement of semiconductor dots, and capable of operation at radio frequencies (rf) as a sensitive electrometer. In another aspect the invention concerns a 10 method of making the device. in one important embodiment the invention is a silicon single electron transistor (SET) Background Art 15 Recent achievements in controlling and measuring spin in GaAs-based semiconductor quantum dotsi have been substantially facilitated by a tunable gate architecture. ElectrostaticaIlly unable barriers have also been used to create well-defined quantum dots in other low-dinmensional systems, for example. semiconducting carbon nanotubes and InAs nanowires 20 Silicon is a particularly attractive material for use to investigate quantum dots, because of the expected long electron-spin coherence txme. This is a result of the small spin-orbit coupling in silicon and the primrily spin-zero nuclear background.

7 However,. single-electron spins have not yet been investigated in silicon quantum dots. 25 Recently, there has been considerable progr ess toward this goaL Coulomb blockade has been observed in etched Si/SiGe heterostretures and more recently, quantum dots have been defined in Si/SiGe using a Schottky split-g ate technique Fixed tunnel barriers, such as local dopant modulation' Or etching 1i5 have been used to 30 fabricate quantum dots in siIicon-on-insulator material Silicon nanowires have also been shown to confine a quantum dot, with the source and drain contacts forming the tunnel barriers, 6 Electrostatic tunnel barriers have been created using various double gated structures Polysilicon gates have been used to define a single- and double island single-electron transistor (SET) electrostatically 35 Throughout this specification the word "comprise", or variations such as comprises" or "comprising", vill be understood to imply the inclusion of a stated 3 element, integer or step, or group of elements, integers or steps, but not the exclusion of any other element, integer or step, or group of elements, integers or steps. Any discussion of documents, acts, materials, devices, articles or the like 5 which has been included in the present specification is not to be taken as an admission that any or all of these matters form part of the prior art base or were common general knowledge in the field relevant to the present disclosure as it existed before the priority date of each claim of this application. 10 Disclosure of the Invention The invention is a silicon integrated circuit device comprising a near intrinsic silicon substrate in which there are one or more ohmic contact regions; a first insulating layer 15 above the substrate; a lower layer of one or more aluminium gates on top of the first insulating layer; an upper aluminium gate that extends over the lower gates; and a second insulating layer of aluminium oxide over the surface of each of the lower gates to insulate them from the upper aluminium gate. 20 The device may be controlled by the voltages applied to the upper and lower gates. Voltage applied to the upper gate of this device is able to induce electrons into the channel to reduce resistance and enable conduction (like a MOSFET). However, voltage applied to the lower gates is able to locally deplete the channel beneath those gates to create tunnel barriers for controlling the flow of charge into and out of a 25 central island region of the channel between the barriers (like an SET). A quantum dot may be created within the device, in the central island region between two tunnel barriers. In this case the upper gate controls the number of electrons in the dot, and the lower gates control the coupling between the dot and the contact regions. 30 Very small dots may be confined, which demonstrate quantum confinement. Excited states may then be observed in bias spectroscopy measurements. Additional lower aluminium gates may be provided to create various desired functionalities. For example, by using three lower gates it is possible to produce a 35 double quantum dot. Large formations of multiple devices can be arranged to perform, for instance, quantum computing applications.

3a In one arrangement the device has two ohmic contact regions at opposite ends of a selectively conductive channel. There are two lower gates and these are arranged transversely over the channel, and the upper gate extends longitudinally over the channel. 5 The device may be combined with an rf tank circuit, Further, the device may be tuned to resonance with the tank circuit, by variation of the voltages on the gates, In this configuration an rf carrier signal may be applied to the channel of the SET by the rf tank circuit, and the reflected power may then be mixed with the carrier frequency and 10 measured using homodyne detection. In this mode of operation the device is capable of detecting the presence and movement of very small charges, down to a single 4 electron, in or in the vicinity of the central island. The high bandwidth of the device means it can be used to measure electronic tunnel rates and other tunnelling statistics. The sensitivity of the SET is a result of the sharp transconductance of the Coulomb 5 blockade oscillations. These oscillations occur when the charging energy of the island is greater than the thermal energy. Sensitive electrometry enables the determination of the electronic properties of nanostructures such as quantum dots down to the limit of few electron occupancy. 10 The device has a wide range of operational temperatures, especially at low temperatures. For instance operation as a quantum dot is expected to be below 100 mK, although it may operate in this fashion at temperatures up to 1 K. As a silicon SET the device may operate at temperatures up to 4 K or even 10 K. 15 The ohmic contact regions may be made by diffusing phosphorus dopants into the substrate. The first insulating layer may be a 5 nm thick layer of Si0 2 gate oxide that is 20 thermally grown on the surface of the substrate. The two lower gates may be aluminium fabricated using electron beam lithography (EBL), thermal evaporation and liftoff. Each of the lower gates may be less than 30 nm wide, and the separation between them less than 40 nm. 25 The lower gates may be partially oxidized using plasma oxidation technique to create the second insulating layer over the surface of each of the lower gates. The second insulating layer may be less than about 10 nm thick. 30 The upper gate may be aluminium, and it may be aligned to the lower gates during a second EBL stage, and again thermally evaporated and lifted off. The upper gate may be less than 100 nm wide, and could even be as narrow as 50 nm. In a further aspect the invention concerns a method for fabricating the device, 35 comprising the steps of: Preparing a near intrinsic, high resistivity, silicon substrate, or silicon-on insulator substrate. Forming one or more ohmic contact regions in the substrate.

5 Thermally growing a first insulating layer of SiC 2 oxide on the substrate. Fabricating a layer of one or more lower gates on top of the first insulating layer using electron beam lithography (EBL), thermal evaporation and liftoff Partially oxidising the lower gates using plasma oxidation technique to create a 5 second insulating layer over the surfaces of each of the lower gates. Fabricating an upper gate over the channel and lower gates during a second EBL stage, with thermal evaporation and liftoff. Annealing the device. 10 Brief Description of the Drawings Examples of the invention will now be described with reference to the accompanying drawings, in which: Fig. 1(a) is a schematic plan of a silicon device embodying the invention. 15 Fig. 1(b) is a schematic cross-section of the silicon device of Fig. 1. Fig. 2(a) is a graph comparing the turn-on characteristics of annealed and unannealed devices. Fig. 2(b) is a graph of the conductance response of each barrier gate, measured 20 while the upper gate and the other barrier gate were well above the threshold value at 3.5 V. Fig. 3(a) is a graph showing a single trace at V 8 ] = 0.43 V, V 8 2 = 0.37 V, showing Coulomb blockade oscillations. 25 Fig. 3(b) is a graph showing differential conductance as a function of the upper gate VG and the barrier gates V 8 i and VB 2 while a constant source-drain bias of 1.5 mV was applied. Fig. 3(c) is an enlarged section of (b) highlighting the diagonal lines of constant occupancy of the dot; the slope of these lines results from the capacitive 30 coupling of the dot to both the upper gate VG and the barrier gates V 8 I and V 8 2 . Fig. 3(d) is a graph showing the differential conductance as a function of each barrier gate voltage V 8 I and V3 2 , at VG = 1.3 V, measured using a constant source drain bias of 1.5 mV. 35 Fig. 4(a) is a bias spectroscopy image of a first sample, taken at V 8 , - VB 2 0.85 V, with a lock-in AC excitation voltage of 20 V, where N_ 100 electrons.

6 Fig. 4(b) is a bias spectroscopy image of a second sample taken at VBI = 0.43 V, VB 2 = 0.37 V, with a lock-in AC excitation voltage of 50 pV, and N -30 electrons on the left. Fig. 4(c) is a graph showing total capacitance of the second sample, as a 5 function of the applied gate voltage VG. Fig. 5(a) is a bias spectroscopy image taken in the few-electron regime, where a lock-in excitation of 50 uV was used and the number of electrons was reduced by decreasing the voltage VG applied to the top gate until the Coulomb diamonds were 10 the last visible. Fig. 5(b) is an enlarged view where the lines of conductance parallel to the Coulomb diamond edges are evidence of excited states in the device. Fig. 6 is a schematic diagram of the rf-measurement set-up. 15 Figs. 7 are graphs of conductance and reflected power characteristics at T-lOOmK. The reflected power has not been calibrated, and is a relative rather than absolute measure. Fig. 7(a) is the DC conductance as a function of all gates applied together. 20 Fig. 7(b) is the reflected power (black) and change in resonant frequency (grey) as a function of all gates applied together. Fig. 7(c) is DC conductance as a function of one of the barrier gates, VB2. Fig. 7(d) is reflected power as a function of one of the barrier gates, V12. 25 Figs. 8 are reflected power measurements demonstrating Coulomb blockade in the silicon SET. An rf carrier signal of 337MHz or 334MHz was used. Fig. 8(a) is reflected power as a function of upper gate, VG, at VB=0.716 V,

VB

2 =0.438 V. Fig. 8(b) is resonant frequency response at two upper gate voltages, 30 VG=l.876V and VG=l.879V, corresponding to a Coulomb blockade peak and trough respectively. Fig. 8(c) is reflected power as a function of upper gate, VG, at VBI=0.702 V,

VB

2 =0.478 V. Fig. 8(d) is reflected power as a function of both barrier gates, VBI and VB2, at 35 VG= 1.65 V, and with source-drain bias VsD=1.OmV. Fig. 8(e) is Coulomb diamonds, that is reflected power as a function of source drain bias, VSD and VG.

7 Fig. 9(a) is a graph of charge sensitivity, 6q as a function of carrier frequency. Fig. 9(b) is a graph of charge sensitivity, 5q as a function of carrier power. Fig. 9(c) is a graph of charge sensitivity, 8q as a function of gate frequency. Fig. 9(d) is a graph of attenuation of the applied gate signal as a function of 5 gate frequency. Best Modes of the Invention Device Fabrication and Geometry 10 Referring first to Figs. 1(a) and (b) the device 10 is seen to comprise a near intrinsic, high resistivity, silicon substrate 12. At either side of the device are regions 14 and 16 of phosphorus diffused n+ regions which provide ohmic contact regions for the device. A 5 nm thick layer of SiO 2 gate oxide 18 was thermally grown on the surface. 15 On top of this insulating oxide layer 18 two lower gates 20 and 22 were fabricated using electron beam lithography (EBL), thermal evaporation and liftoff. Each of the lower gates 20 and 22 were less than 30 nm wide, and the separation between them d is less than 40 nm. 20 The lower gates were then partially oxidized using plasma oxidation technique to create insulating layers 24 and 26 over their surfaces respectively. In particular, the aluminium gates were exposed to a low-pressure oxygen plasma (0.15 mbar) for 3 min at a temperature of about 150"C. This forms a layer of oxide at the gates' surfaces that is a few nanometers thick. 25 An upper aluminium gate 28 was aligned to the lower gates during a second EBL stage, and again thermally evaporated and lifted off. The upper gate 28 can be made in a range of widths w, for instance between 50 nm and 100 nm wide, in any event it crosses over the top of the two lower gates 20 and 22. 30 The final processing step was a low-temperature-forming gas anneal, comprising 15 min at 400*C in 95% N 2 / 5% H 2 . Slowly varying DC voltage Investigations 35 The geometry described in Fig. I can be used, by applying an appropriate voltage VG to the upper gate 28, to induce an accumulation layer, that is a two-dimensional electron gas (2DEG), in the intrinsic silicon substrate 12 (like a MOSFET).

8 Appropriate voltages, V, and V 2 , on the two lower gates 20 and 22, can locally deplete electrons from below the two lower gates 20 and 22, as shown at 32 and 34, to form tunable tunnel barriers (like a SET). This in turn allows the electrostatic confinement of a small number of electrons in the central island 36 under the space 5 between the lower gates 20 and 22. The confined silicon may form a quantum dot with a diameter of about 50 nm. Electrostatic manipulation of the lower gates 20 and 22 tunes the barriers on either side of the quantum dot, and this allows control of the tunnel rate across each barrier, as well as management of the interaction between electron occupancy and barrier transparency. 10 Electrical transport measurements were performed on several silicon quantum dots at the base temperature (-50 mK) of a dilution refrigerator, at an electron temperature of -100 mK. Standard low-frequency lock-in techniques were used to measure the two terminal conductance and differential conductance through the dot. Measurements 15 were performed in zero applied magnetic field, and made using a lock-in AC excitation voltage of 100 pV. Each ohmic contact typically has a resistance of-I kQ. The typical maximum mobility of similar MOSFET devices (5-nm Si02, Al gate) is -5000 cm 2 /(V s) at 4 K. 20 Turn-On Characteristics To measure the turn-on characteristic, a voltage was applied to all three gates simultaneously, VG, VBI and VB2, resulting in an approximately continuous field along the length of the nanowire 36. At 4 K, because of the high resistivity of the 25 wafer, the source-drain conductance is zero until the applied gate voltage is equal to the threshold value. As the applied gate voltage is increased above the threshold value, the sourcedrain current increases smoothly toward a maximum conductance. At millikelvin temperatures, conductance fluctuations occur in the MOSFET like turn-on characteristic. As shown in Fig. 2(a), these fluctuations are reproducible over several 30 sweeps of the voltage applied to all three gates. A comparison is made between devices made in the same batch, but without the final forming gas anneal. The fluctuations in these samples were not reproducible over different sweeps and were time-dependent, which is consistent with switching events 35 at the unannealed Si/Si0 2 interface or within the Si0 2 . A forming gas anneal is well established in standard Si MOSFETs for reducing the Si/Si0 2 interface trap density, and this result emphasizes the importance of this step for noise reduction in low temperature measurements. This anneal also improved the performance of the samples 9 by decreasing the threshold voltage, increasing the transconductance, and increasing the maximum conductance. Each of these effects is visible in the comparison of the annealed 40 and unannealed 42 samples in Fig. 2(a). 5 Conductance Characteristics The conductance characteristic of each of the barrier gates is shown in Fig. 2(b). To isolate the effect of each barrier gate, these characteristics were measured with both the upper gate and the other respective barrier gate well above the threshold value. 10 These results demonstrate that each of the lower gates may be used to tune its associated barrier from highly transparent (G > e2/h) to completely opaque (G = 0). Some conductance fluctuations are observed in each barrier, which are probably due to variations in the potential and resonances in each barrier. At 4 K, these fluctuations are not observed; the source-drain conductance increases smoothly with the applied 1 5 barrier gate voltage. The barriers both have a steeper turn-on than the channel. Some resonances can be observed in each barrier. 20 Coulomb Blockade The combined effect of both the upper gate and the lower barrier gates on the source drain conductance is illustrated in Fig. 3. The constant period and varying amplitude of the Coulomb oscillations, as shown in Fig. 3(a), are typical of transport through a 25 semiconducting island and demonstrate resolvable quantum states in the island 36. Fig. 3(b) displays the relationship between the upper and lower gates. The current through the device is zero when the applied gate voltage VG is below the threshold value, and also when opaque barriers are created by the lower gates 20 and 22. When 30 the source-drain current through the device is nonzero, Coulomb blockade with constant period is observed over a large region, demonstrating that a single island is formed by the tunable tunnel barriers over a large range of applied biases. The fine diagonal lines in the plot, which are enlarged in Fig. 3(c) to be more easily visible, are resolvable quantum states and correspond to regions of constant electron occupancy 35 of the dot. The independent control of each barrier is demonstrated further in Fig. 3(d). Diagonal lines in the plot indicate Coulomb blockade that is equally coupled to each barrier 10 gate and, therefore, is due to the central island. Also visible are vertical and horizontal lines, which are evidence of Coulomb blockade that is strongly coupled to the first and second barrier gates, respectively. The very small crosscoupling shown makes it likely that these resonances are due to the imperfect potential in each of the barriers. 5 Irregularities in the transport through the dot, as observed in Fig. 3(b), are likely to result from this same disorder in the barriers. We note that, in Fig. 3(d), there is some capacitive coupling between these barrier resonances and the central island, which may be suggestive of double dot charging. However, when the upper gate VG is used 10 to probe the Coulomb diamonds, a constant Coulomb blockade period is observed over a wide range (for example, see Fig. 4(b)). This is indicative of a single dot in the centrally defined island. The Many-Electron Regime 15 Various devices have been measured, with consistent results across different samples. Figs. 4(a) and (b) show Coulomb diamonds belonging to two different samples. The first sample in Fig 4(a) has a dot area of 30 nm x 105 nm), and the second sample in Fig. 4(b) has a dot area of 35 nm x 65 nm. 20 The dot in the first sample has a charging energy of e 2 /Cx) 2.5 meV. This gives a total capacitance value for the defined quantum dot of 64 aF, which is consistent with a simple parallel plate capacitance calculation of 61 aF, based on the lithographic dimensions of the dot, including the contribution of the barrier gates. The gate 25 capacitance (determined by the period of oscillations) is determined to be 13 aF, which, again, is consistent with the parallel-plate capacitor estimation of 21 aF. The ratio of the gate capacitance to the total capacitance is a = CG/C.E= 0.20. The dot in sample 2 has a charging energy, e /C, which increases from 2 meV to 4 30 meV, as the applied gate voltage, VG, decreases. This charging energy is larger, which is consistent with the smaller dimensions of this device. The total capacitance determined from the charging energy is 40-80 aF, and this finding again agrees with the calculated capacitance of 4l aF. The total capacitance is approximately linearly dependent on the applied gate voltage VG, as shown in Fig. 4(c), because the 35 capacitance increases as the size of the dot increases. The gate capacitance is determined to be 12 aF, from the period of oscillations, which is consistent with the calculated value of 16 aF. The gate capacitance does not change significantly over the applied voltage range, presumably because, as the dot extends under the barrier gates, it is electrostatically screened from the applied MOSFET gate voltage. This results in a gate capacitance ratio of a = 0.30 at VG = 1.2 V. The consistency of regular diamonds over such a large gate range confirms that this sample contains a single, electrostatically defined quantum dot, because multiple islands result in overlapping 5 diamonds. By varying the voltages applied to the upper gate and the lower gates, it is possible to measure transport through the quantum dot in different regimes: the upper gate VG is used to alter the number of electrons in the dot; and the lower barriers gates control 10 the coupling between the dot and the leads. We estimated the number of electrons in the dot using two different methods. The first method used the period of Coulomb oscillations, which represents the addition of a single electron. The relative voltage applied to the top gate, with respect to the threshold voltage, is divided by the Coulomb oscillation period, giving an estimate of the number of electrons in the dot 15 (assuming zero free electrons in the dot below the threshold voltage). The second method simply used the measured electron density of a similar device. Both methods give consistent estimates, within a few electrons. The number of electrons (N) in each of the dots shown is thus estimated to be N =100 in Fig. 4(a) and N =30 at the left of the long diamond sweep in Fig. 4(b). 20 The Few-Electron Regime To investigate transport phenomena in the few-electron regime, the applied gate bias VG was reduced to just above the threshold value. Fig. 5 shows data obtained with VG 25 = 1.10 V, Vi = V 2 = 0.754 V, and we estimate N= 10 electrons. There are indications of excited (quantum) states, shown in Fig. 5 by brighter lines of differential conductance parallel to the edges of the Coulomb diamonds outside of the blockaded region. These states become far more pronounced in the few-electron regime than in the many-electron regime; as observed in Fig. 5(b) in particular. The approximate 30 energy level spacing in a two-dimensional (2D) dot can be calculated using AE = 2fth 2 gm *A where g is the degeneracy, m* the effective mass, and A the area of the dot. If both 35 spin and valley degeneracies are included, then AE = 275 peV. Energy-level spacings up to 600 ieV are observed in Fig. 5, which is broadly consistent with the predicted value. In the few-electron regime, there are also many anomalies in the Coulomb 12 diamonds, such as the gap in conductance near VsD = 0 mV and also the brighter lines of conductance that are not parallel to the diamonds. We understand that these are mostly likely due to imperfections in the barriers. 5 It is interesting to note several features: Significantly, the spacing of the excited states changes considerably for different electron occupancy of the dot, which is consistent with the excited states of a dot in the few-electron regime. States in the barriers or leads are expected to remain at a constant spacing over several diamonds. It is not clear whether the excited states of the dot are due to orbital excited states alone or 10 whether there is also a splitting of the 2D valley degeneracy, as is anticipated in strongly confined 2D structures in silicon. Radio Frequency Investigations 15 To this point the device has been considered with applied slowly varying DC voltages. Electrical transport measurements were performed at the base temperature (-lOOmK) of a dilution refrigerator. As illustrated in Fig. 6, the silicon SET 60 was placed in an rf tank circuit 62, with an inductor L = 470nH and a parasitic capacitance, Cp, of approximately 450fF. A DC source-drain bias was applied using a 20 bias tee, with two-terminal DC conductance measurements performed using a standard low-frequency lock-in technique. Measurements were performed in zero applied magnetic field. An rf carrier signal 64 is applied to the source of the SET at the resonant frequency of the circuit (-340MHz). The reflected power is mixed with the carrier frequency and measured using homodyne detection, as shown in Fig. 6. 25 IV Characteristic In order to measure the IV characteristic, a voltage was applied to all three gates simultaneously, resulting in an approximately continuous potential along the length of 30 the narrow channel. At 4K, due to the high resistivity of the wafer, the source-drain conductance is zero until the applied voltage is at the threshold value. As the gate voltage is increased above threshold, the source-drain current increases smoothly towards a maximum conductance; see Fig. 7(a). 35 At millikelvin temperature, conductance fluctuations occur in the MOSFET IV characteristic, as seen in Fig. 7 (b). The non-zero DC resistance below threshold (3x10 3 ) is due to limits of the measurement. The reflected rf-signal was also measured as a function of the voltage applied to all three gates, and as a function of 13 frequency. The reflected rf-signal depends on the resistance of the SET, as described by the reflection coefficient, Z-50 r = Z+50 5 where Z = L/(RCp) is the impedance of the tank circuit including the SET resistance, R, at resonance. The resonant frequency is the frequency at which the minimum power is reflected. At an applied gate voltage well below the DC threshold value, there is a change in the resonant frequency, shown in Fig. 7(b). This change in 10 frequency is equivalent to a change in the parasitic capacitance, ACp = 40fF. This frequency shift occurs at a voltage approximately equal to the threshold voltage in similar MOSFETs with much wider gates. This suggests that the 2DEG is induced under the wide area leads before DC conduction is possible in the narrow channel. 15 Conductance Characteristics The conductance characteristic of one of the barrier gates is given in Fig. 7(c). In order to isolate the effect of each barrier gate, this characteristic was measured with both the upper gate and the other barrier gate well above threshold. The lower gates 20 may be used to tune their associated barrier from highly transparent (G > e 2 /h) to completely opaque (G = 0), as illustrated for Barrier 2 in Fig. 7(c). Barrier I displayed similar conductance and frequency characteristics. There is no significant shift in resonant frequency during the sweeps of each of the barrier gates. Resonances are observed during the sweep of each barrier gate potential. The matching resistance is 25 observed to be approximately 50k by correlating the DC resistance and the reflected rf-signal. It is interesting to note the asymmetry of the reflected power as a function of the applied barrier voltage. The reflected power is expected to approach zero as the resistance increases or decreases away from the matching resistance. 30 Coulomb Blockade Coulomb blockade oscillations are observed over a large range of applied upper gate bias, VG, as shown in Fig. 8(c) while the barrier gates are held at constant potential, V1I=0.702 V, V1 2 =0.478 V. The regular period is evidence that a single dot is formed 35 in the Si SET. The increasing amplitude of the Coulomb blockade peaks is a result of the decreasing resistance of the SET as the upper gate bias is increased. We chose to operate the SET near VG = 2.OV due to the large difference in reflected power between the peak and trough of the Coulomb blockade oscillations at this voltage.

14 The independent control of each barrier is demonstrated in Fig. 8 (d). The vertical and horizontal edges of the conducting region demonstrate that each barrier independently switches off the channel. The diagonal lines are Coulomb blockade oscillations 5 exhibiting equal coupling to both barriers, indicating regions of constant occupancy in the central island. The vertical and horizontal lines result from blockade which couples only to VB, and VB 2 respectively and are evidence of disorder in each barrier. Closed, periodic Coulomb diamonds are observed, as shown in Fig. 8 (e). The 10 measured charging energy, EC = e 2/Cj is I meV. The measured charging energy is lower than the estimated charging energy EC = 2meV , based on a parallel plate calculation of the total capacitance. Charge noise was observed, causing shifts in the Coulomb diamonds. This noise was observed when the rf-signal was applied and also during DC measurements of the conductance. 15 Charge Sensitivity The charge sensitivity of the silicon rf-SET was determined as a function of carrier frequency, carrier power, gate frequency and source-drain voltage. The charge 20 sensitivity is measured by superimposing a small sinusoidal signal onto the DC gate voltage, with an rms amplitude equivalent to -0.01 of an electron on the island. This results in amplitude modulation of the carrier signal. The resulting signal to noise ratio of the side-bands is then measured and the sensitivity is calculated using the expression: 25 Sq Aq ms B x l SNR/20 The best charge sensitivity was found to be 6q = 7.2te/qHz, at zero source-drain bias. The 3dB bandwidth of the resonant circuit is 15MHz, as revealed by the relationship 30 of the charge sensitivity to the frequency of the carrier signal, given in Fig. 9(a). The optimal carrier power for the best charge sensitivity depends on the charging energy of the SET. Since this SET has a larger charging energy than typical Al rf-SETs, it is possible to use a higher carrier power, as illustrated in Fig. 9(b). 35 The charge sensitivity increases sharply at a gate frequency of approximately 2.5MHz. This cut-off frequency is consistent with the expected RC time constant of the high resistance gate contact in this sample. This is confirmed by increasing the amplitude of the sinusoidal signal on the gate over a range of frequencies. Since the 15 SET resistance is non-linear, as the gate amplitude increases, more sidebands are visible in the demodulated signal. The magnitude of the nth sideband is given by the Bessel function Jn((2nCGVG)/e). The zeroes of the first sideband reveal the attenuation of the gate signal, given in Fig. 9(d). The frequency at which the gate 5 signal attenuation increases corresponds to the gate frequency at which the charge sensitivity also increases. This demonstrates that the bandwidth of this sample is not limited to 2.5MHz by the Si SET, but by the high resistance gate contact. Although the invention has been described with reference to a particular example, it 10 should be appreciated that it could be exemplified in many other forms and in combination with other features not mentioned above. For instance, there are a number of ways by which the Si rf-SET may be improved. It is possible to increase the charging energy of the Si SET by decreasing the upper gate width and also by increasing the gate oxide thickness, in both cases thus decreasing the capacitance. An 1 5 increased charging energy is expected to lead to both better charge sensitivity as well as a higher operating temperature. The lower gates may also be oxidised using other techniques, such as thermal oxidation or oxidation assisted by UV exposure. References 20 (1) Elzerman, J. M.; Hanson, R.; Willems van Beveren, L. H.; Witkamp, B.; K. Vandersypen, L. M.; Kouwenhoven, L. P. Nature 2004, 430, 431. (2) Petta, J. R.; Johnson, A. C.; Taylor, J. M.; Laird, E. A.; Yacoby, A.; 25 Lukin, M. D.; Marcus, C. M.; Hanson, M. P.; Gossard, A. C. Science 2005, 309, 2180. (3) Koppens, F. H. L.; Buizert, C.; Tielrooij, K. J.; Vink, I. T.; Nowack, K. C.; Meunier, T.; Kouwenhoven, L. P.; Vandersypen, L. M. K. Nature 2006, 442, 766. 30 (4) Biercuk, M. J.; Mason, N.; Marcus, C. M. Nano Lett. 2004, 4, 1. (5) Sapmaz, S.; Meyer, C.; Beliczynski, P.; Jarillo-Herrero, P.; Kouwenhoven, L. P. Nano Lett. 2006, 6, 1350. (6) Fasth, C.; Fuhrer, A.; Bjork, M. T.; Samuelson, L. Nano Lett. 2005, 5, 1487. 35 (7) Tahan, C.; Joynt, R. Phys. ReV. B: Condens. Matter Mater. Phys. 2005, 71, 075315. (8) Klein, L. J.; Lewis, K. L. M.; Slinker, K. A.; Goswami, S.; van der Weide, D. W.; Blick, R. H.; Mooney, P. M.; Chu, J. 0.; Coppersmith, 16 S. N.; Friesen, M.; Eriksson, M. A. J. Apple. Phys. 2006, 99, 023509. (9) Berer, T.; Pachinger, D.; Pillwein, G.; Muhlberger, M.; Lichtenberger, H.; Brunthaler, G.; Schaffler, F. Apple. Phys. Lett. 2006, 88, 1621 12. (10) Sakr, M. R.; Jiang, H. W.; Yablonovitch, E.; Croke, E. T. Apple. Phys. 5 Lett. 2005, 87, 223104. (11) Klein, L. J.; Savage, D. E.; Eriksson, M. A. Apple. Phys. Lett. 2007, 90, 033103. (12) Goswami, S.; Slinker, K. A.; Friesen, M.; McGuire, L. M.; Truitt, J. L.; Tahan, C.; Klein, L. J.; Chu, J. 0.; Mooney, P. M.; van der Weide, 10 D. W.; Joynt, R.; Coppersmith, S. N.; Eriksson, M. A. Nat. Phys. 2007,3,41. (13) Hofheinz, M.; Jehl, X.; Sanquer, M.; Molas, G.; Vinet, M.; Deleonibus, S. Apple. Phys. Lett. 2006, 89, 143504. (14) Rokhinson, L. P.; Guo, L. J.; Chou, S. Y.; Tsui, D. C. Phys. ReV. B: 15 Condens. Matter Mater. Phys. 2001, 63, 035321. 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Claims (15)

1. A silicon integrated circuit device comprising: a near intrinsic silicon substrate in which there are one or more ohmic contact 5 regions; a first insulating layer above the substrate; a lower layer of one or more aluminium gates on top of the first insulating layer; an upper aluminium gate that extends over the lower gates; and 10 a second insulating layer of aluminium oxide over the surface of each of the lower gates to insulate them from the upper aluminium gate.

2. A silicon integrated circuit device according to claim 1, wherein the lower layer of one or more aluminium gates comprises two or more aluminium gates, and a 15 quantum dot is created within the device, in a central island region between two of the aluminium gates.

3. A silicon integrated circuit device according to claim 1 or 2, wherein additional lower aluminium gates are provided. 20

4. A formation of multiple devices according to any preceding claim.

5. A device according to any one of claims 1 to 3 in combination with an rf tank circuit. 25

6. A device according to any one of claims 1 to 3, wherein the ohmic contact regions are made by diffusing phosphorus dopants into the substrate.

7. A device according to claim 6, wherein the first insulating layer is a 5 nm thick 30 layer of SiO 2 gate oxide that is thermally grown on the surface of the substrate.

8. A device according to claim 7, wherein the two lower gates are aluminium fabricated using electron beam lithography (EBL), thermal evaporation and liftoff. 35

9. A device according to claim 8, wherein each of the lower gates is less than 30 nm wide, and the separation between them less than 40 nm. 18

10. A device according to claim 9, wherein the lower gates are partially oxidized using plasma oxidation technique to create the second insulating layer over the surface of each of the lower gates. 5

11. A device according to claim 10, wherein the second insulating layer is less than about 10 nm thick.

12. A device according to claim 11, wherein the upper gate is aluminium, and it is aligned to the lower gates during a second EBL stage, and again thermally evaporated 10 and lifted off.

13. A device according to claim 12, wherein the upper gate is between 50 nm and 100 nm wide. 15

14. A method for fabricating a device according to claim 1, comprising the steps of: preparing a near intrinsic, high resistivity, silicon substrate; forming at least one ohmic contact region within the device; thermally growing a first insulating layer of SiO 2 oxide on the substrate; 20 fabricating a layer of lower gates on top of the first insulating layer, using electron beam lithography (EBL), thermal evaporation and liftoff; partially oxidising the lower gates using plasma oxidation technique to create a second insulating layer over the surface of each of the lower gates; fabricating an upper gate over the channel and lower gates during a second 25 EBL stage, with thermal evaporation and liftoff; and, annealing the device.

15. A silicon integrated circuit device substantially as hereinbefore described with reference to the accompanying drawings. 30