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AU2003280498A1 - Method of defining the dimensions of circuit elements by using spacer deposition techniques - Google Patents

Method of defining the dimensions of circuit elements by using spacer deposition techniques

Info

Publication number
AU2003280498A1
AU2003280498A1 AU2003280498A AU2003280498A AU2003280498A1 AU 2003280498 A1 AU2003280498 A1 AU 2003280498A1 AU 2003280498 A AU2003280498 A AU 2003280498A AU 2003280498 A AU2003280498 A AU 2003280498A AU 2003280498 A1 AU2003280498 A1 AU 2003280498A1
Authority
AU
Australia
Prior art keywords
defining
dimensions
circuit elements
deposition techniques
spacer deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003280498A
Other versions
AU2003280498A8 (en
Inventor
Carsten Hartig
Martin Mazur
Georg Sulzer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10228807A external-priority patent/DE10228807B4/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2003280498A8 publication Critical patent/AU2003280498A8/en
Publication of AU2003280498A1 publication Critical patent/AU2003280498A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H10W20/089—
    • H10D64/01326—
    • H10D64/01328—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/0142—Manufacturing their gate conductors the gate conductors having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10P50/71—
    • H10P50/73—
    • H10P76/4085—
    • H10P76/4088—
    • H10W20/076—
AU2003280498A 2002-06-27 2003-06-24 Method of defining the dimensions of circuit elements by using spacer deposition techniques Abandoned AU2003280498A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE10228807.0 2002-06-27
DE10228807A DE10228807B4 (en) 2002-06-27 2002-06-27 Process for the production of microstructure elements
US10/306,319 US6936383B2 (en) 2002-06-27 2002-11-27 Method of defining the dimensions of circuit elements by using spacer deposition techniques
US10/306,319 2002-11-27
PCT/US2003/020809 WO2004003977A2 (en) 2002-06-27 2003-06-24 Method of defining the dimensions of circuit elements by using spacer deposition techniques

Publications (2)

Publication Number Publication Date
AU2003280498A8 AU2003280498A8 (en) 2004-01-19
AU2003280498A1 true AU2003280498A1 (en) 2004-01-19

Family

ID=30001481

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003280498A Abandoned AU2003280498A1 (en) 2002-06-27 2003-06-24 Method of defining the dimensions of circuit elements by using spacer deposition techniques

Country Status (2)

Country Link
AU (1) AU2003280498A1 (en)
WO (1) WO2004003977A2 (en)

Families Citing this family (38)

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US7151040B2 (en) 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
US7910288B2 (en) 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
US7655387B2 (en) 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
US7115525B2 (en) 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
US7253118B2 (en) 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US7390746B2 (en) 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US7611944B2 (en) 2005-03-28 2009-11-03 Micron Technology, Inc. Integrated circuit fabrication
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7560390B2 (en) 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
US7396781B2 (en) 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
US7888721B2 (en) 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7413981B2 (en) 2005-07-29 2008-08-19 Micron Technology, Inc. Pitch doubled circuit layout
US7816262B2 (en) 2005-08-30 2010-10-19 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
US7829262B2 (en) * 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7322138B2 (en) 2005-08-31 2008-01-29 Southern Imperial, Inc. Shelf edge sign holder
US7776744B2 (en) 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US7572572B2 (en) 2005-09-01 2009-08-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7557032B2 (en) 2005-09-01 2009-07-07 Micron Technology, Inc. Silicided recessed silicon
US7393789B2 (en) 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7759197B2 (en) 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
DE602005015853D1 (en) 2005-09-14 2009-09-17 St Microelectronics Srl Method for producing a phase change memory arrangement with a uniform heating element height
US7476933B2 (en) 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
US7902074B2 (en) 2006-04-07 2011-03-08 Micron Technology, Inc. Simplified pitch doubling process flow
US7488685B2 (en) 2006-04-25 2009-02-10 Micron Technology, Inc. Process for improving critical dimension uniformity of integrated circuit arrays
US7723009B2 (en) 2006-06-02 2010-05-25 Micron Technology, Inc. Topography based patterning
US7611980B2 (en) 2006-08-30 2009-11-03 Micron Technology, Inc. Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US7666578B2 (en) 2006-09-14 2010-02-23 Micron Technology, Inc. Efficient pitch multiplication process
US8129289B2 (en) 2006-10-05 2012-03-06 Micron Technology, Inc. Method to deposit conformal low temperature SiO2
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8563229B2 (en) 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US7737039B2 (en) 2007-11-01 2010-06-15 Micron Technology, Inc. Spacer process for on pitch contacts and related structures
US7659208B2 (en) 2007-12-06 2010-02-09 Micron Technology, Inc Method for forming high density patterns
US7790531B2 (en) 2007-12-18 2010-09-07 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US8030218B2 (en) 2008-03-21 2011-10-04 Micron Technology, Inc. Method for selectively modifying spacing between pitch multiplied structures
US8076208B2 (en) 2008-07-03 2011-12-13 Micron Technology, Inc. Method for forming transistor with high breakdown voltage using pitch multiplication technique
US8492282B2 (en) 2008-11-24 2013-07-23 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits
CN114388357B (en) * 2022-01-12 2025-03-18 锐立平芯微电子(广州)有限责任公司 A method and device for manufacturing a multi-size metal gate

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5328810A (en) * 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
JPH0714916A (en) * 1993-06-22 1995-01-17 Nec Corp Isolation structure of MOS field effect transistor and manufacturing method thereof
JPH10223756A (en) * 1997-02-06 1998-08-21 Sony Corp Method of forming contact hole
TW451314B (en) * 1999-03-05 2001-08-21 United Microelectronics Corp Manufacture method of semiconductor device
US6255202B1 (en) * 2000-07-20 2001-07-03 Advanced Micro Devices, Inc. Damascene T-gate using a spacer flow

Also Published As

Publication number Publication date
AU2003280498A8 (en) 2004-01-19
WO2004003977A3 (en) 2004-06-03
WO2004003977A2 (en) 2004-01-08

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase