[go: up one dir, main page]

AU2003274530A1 - Integrated circuit with at least one bump - Google Patents

Integrated circuit with at least one bump

Info

Publication number
AU2003274530A1
AU2003274530A1 AU2003274530A AU2003274530A AU2003274530A1 AU 2003274530 A1 AU2003274530 A1 AU 2003274530A1 AU 2003274530 A AU2003274530 A AU 2003274530A AU 2003274530 A AU2003274530 A AU 2003274530A AU 2003274530 A1 AU2003274530 A1 AU 2003274530A1
Authority
AU
Australia
Prior art keywords
contact pad
mum
signal
processing circuit
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003274530A
Inventor
Heimo Scheucher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of AU2003274530A1 publication Critical patent/AU2003274530A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H10W72/20—
    • H10W72/251—
    • H10W72/923—
    • H10W72/9415—

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

In an integrated circuit ( 1 ) having a substrate ( 3 ) and having a signal-processing circuit ( 4 ) which is produced at a surface ( 8 ) of the substrate ( 3 ), there is provided on the substrate surface ( 8 ) a protective layer ( 12 ) that has at least one aperture ( 13 ) through which a second contact pad ( 14 ) is electrically and mechanically connected to a first contact pad ( 9 ), wherein the second contact pad ( 14 ) is of a height of at least 15 mum and projects laterally beyond the aperture ( 13 ) on all sides and is seated on the protective layer ( 12 ) by an overlap zone (z) that is closed on itself like a ring, wherein the overlap zone (z) has a constant width of overlap (w) of between 2 mum and 15 mum, and wherein at least one element of the signal-processing circuit ( 4 ), and preferably only one capacitor ( 5 ) of the signal-processing circuit ( 4 ), is provided opposite the first contact pad ( 9 ).
AU2003274530A 2002-11-08 2003-10-31 Integrated circuit with at least one bump Abandoned AU2003274530A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP02102552.3 2002-11-08
EP02102552 2002-11-08
PCT/IB2003/004877 WO2004042818A1 (en) 2002-11-08 2003-10-31 Integrated circuit with at least one bump

Publications (1)

Publication Number Publication Date
AU2003274530A1 true AU2003274530A1 (en) 2004-06-07

Family

ID=32309455

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003274530A Abandoned AU2003274530A1 (en) 2002-11-08 2003-10-31 Integrated circuit with at least one bump

Country Status (8)

Country Link
US (1) US7247943B2 (en)
EP (1) EP1563537B1 (en)
JP (1) JP2006505933A (en)
CN (1) CN100382293C (en)
AT (1) ATE392012T1 (en)
AU (1) AU2003274530A1 (en)
DE (1) DE60320299T2 (en)
WO (1) WO2004042818A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10337569B4 (en) * 2003-08-14 2008-12-11 Infineon Technologies Ag Integrated connection arrangement and manufacturing method
US20080123335A1 (en) * 2006-11-08 2008-05-29 Jong Kun Yoo Printed circuit board assembly and display having the same
WO2009007929A2 (en) 2007-07-12 2009-01-15 Nxp B.V. Integrated circuits on a wafer and methods for manufacturing integrated circuits
US8581423B2 (en) * 2008-11-17 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Double solid metal pad with reduced area
US9052304B2 (en) * 2009-03-13 2015-06-09 Terrasep, Llc Methods and apparatus for centrifugal liquid chromatography
JP5558336B2 (en) 2010-12-27 2014-07-23 株式会社東芝 Semiconductor device
US20130320522A1 (en) * 2012-05-30 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Re-distribution Layer Via Structure and Method of Making Same
JP6111907B2 (en) * 2013-07-05 2017-04-12 三菱電機株式会社 Manufacturing method of semiconductor device
CN105514085B (en) * 2014-10-14 2018-05-04 中芯国际集成电路制造(上海)有限公司 Wafer, the method for cutting crystal wafer and chip
CN115132687B (en) * 2022-09-02 2022-11-22 甬矽电子(宁波)股份有限公司 Package stacking structure and package stacking method

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5719448A (en) * 1989-03-07 1998-02-17 Seiko Epson Corporation Bonding pad structures for semiconductor integrated circuits
US5281855A (en) * 1991-06-05 1994-01-25 Trovan Limited Integrated circuit device including means for facilitating connection of antenna lead wires to an integrated circuit die
EP0637840A1 (en) * 1993-08-05 1995-02-08 AT&T Corp. Integrated circuit with active devices under bond pads
JP3432284B2 (en) * 1994-07-04 2003-08-04 三菱電機株式会社 Semiconductor device
US5821855A (en) * 1997-02-28 1998-10-13 Lewis; Tommy J. Recognition responsive security system
KR100267105B1 (en) * 1997-12-09 2000-11-01 윤종용 Semiconductor device with multi-layer pad and manufacturing method
TW430935B (en) * 1999-03-19 2001-04-21 Ind Tech Res Inst Frame type bonding pad structure having a low parasitic capacitance

Also Published As

Publication number Publication date
DE60320299D1 (en) 2008-05-21
DE60320299T2 (en) 2009-05-20
WO2004042818A1 (en) 2004-05-21
ATE392012T1 (en) 2008-04-15
US7247943B2 (en) 2007-07-24
US20060071240A1 (en) 2006-04-06
EP1563537B1 (en) 2008-04-09
CN100382293C (en) 2008-04-16
EP1563537A1 (en) 2005-08-17
JP2006505933A (en) 2006-02-16
CN1711638A (en) 2005-12-21

Similar Documents

Publication Publication Date Title
MY122959A (en) Stacked microelectronic packages
WO2003063248A8 (en) Semiconductor die package with semiconductor die having side electrical connection
TWI264756B (en) Semiconductor device
TWI267206B (en) Package assembly
WO2004015771A3 (en) Semiconductor device and method of manufacturing the same
WO2005020279A3 (en) Semiconductor device having electrical contact from opposite sides and method therefor
TW200614404A (en) Semiconductor device and manufacturing method thereof
TW200631064A (en) Semiconductor device
MY134479A (en) Method and apparatus for packaging integrated circuit devices
AU2002340128A1 (en) Mos devices and corresponding manufacturing methods and circuits
WO2003054954A3 (en) Electrical/optical integration scheme using direct copper bonding
TW200518267A (en) Integrated circuit chip
TW200620704A (en) Nitride-based compound semiconductor light emitting device
TW200603308A (en) Semiconductor device, circuit substrate, electro-optic device and electronic appliance
TW200617549A (en) IC chip, IC assembly and flat display
AU2003274530A1 (en) Integrated circuit with at least one bump
TW200629512A (en) Non-circular via holes for bumping pads and related structures
TW200620502A (en) Semiconductor device, circuit board, electro-optic device, electronic device
WO2003096416A3 (en) Reactive solder material
TW200627561A (en) Chip package
WO2005112113A3 (en) Mounting with auxiliary bumps
TW200501838A (en) Hybrid integrated circuit device
TW200723482A (en) Integrated circuit having bond pad with improved thermal and mechanical properties
WO2004030096A3 (en) Crack resistant interconnect module
WO2003067677A3 (en) Organic semiconductor photodetector

Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase