AU2002338729A1 - Router - Google Patents

Router

Info

Publication number: AU2002338729A1
Authority: AU; Australia
Prior art keywords: router
Prior art date: 2001-09-19
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Abandoned

Application number

AU2002338729A

Inventor

Daniel Bretz

Martin Vorbach

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

PACT XPP Technologies AG

Original Assignee

PACT XPP Technologies AG

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2001-09-19

Filing date

2002-09-18

Publication date

2003-04-01

2001-09-28 Priority claimed from US09/967,497 external-priority patent/US7266725B2/en

2001-10-08 Priority claimed from PCT/EP2001/011593 external-priority patent/WO2002029600A2/en

2002-03-05 Priority claimed from PCT/EP2002/002403 external-priority patent/WO2002071249A2/en

2002-03-05 Priority claimed from PCT/EP2002/002398 external-priority patent/WO2002071248A2/en

2002-03-21 Priority claimed from DE10212622A external-priority patent/DE10212622A1/en

2002-06-12 Priority claimed from DE10226186A external-priority patent/DE10226186A1/en

2002-06-20 Priority claimed from DE10227650A external-priority patent/DE10227650A1/en

2002-08-21 Priority claimed from DE10238174A external-priority patent/DE10238174A1/en

2002-08-27 Priority claimed from DE10240000A external-priority patent/DE10240000A1/en

2002-09-03 Priority claimed from PCT/DE2002/003278 external-priority patent/WO2003023616A2/en

2002-09-09 Priority claimed from PCT/EP2002/010084 external-priority patent/WO2003025770A2/en

2002-09-18 Application filed by PACT XPP Technologies AG filed Critical PACT XPP Technologies AG

2003-04-01 Publication of AU2002338729A1 publication Critical patent/AU2002338729A1/en

Status Abandoned legal-status Critical Current

Classifications

- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing

Landscapes

Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Computer Hardware Design (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Software Systems (AREA)
Computer Networks & Wireless Communication (AREA)
Evolutionary Computation (AREA)
Geometry (AREA)
Multi Processors (AREA)
Telephonic Communication Services (AREA)

AU2002338729A 2001-09-19 2002-09-18 Router Abandoned AU2002338729A1 (en)

Applications Claiming Priority (59)

Application Number	Priority Date	Filing Date	Title
DE10146132		2001-09-19
DE10146132.1		2001-09-19
US09/967,497		2001-09-28
US09/967,497 US7266725B2 (en)	2001-09-03	2001-09-28	Method for debugging reconfigurable architectures
AU16952/02		2001-09-30
EP0111299		2001-09-30
PCT/EP2001/011593 WO2002029600A2 (en)	2000-10-06	2001-10-08	Cell system with segmented intermediate cell structure
AU2002220600		2001-10-08
DE10154259.3		2001-11-05
DE10154259		2001-11-05
EP01129923.7		2001-12-14
EP01129923		2001-12-14
EP02001331.4		2002-01-18
EP02001331		2002-01-18
DE10206653		2002-02-15
DE10206653.1		2002-02-15
DE10206857		2002-02-18
DE10206856.9		2002-02-18
DE10206857.7		2002-02-18
DE10206856		2002-02-18
DE10207226.4		2002-02-21
DE10207224.8		2002-02-21
DE10207226		2002-02-21
DE10207224		2002-02-21
DE10208434		2002-02-27
DE10208434.3		2002-02-27
DE10208435.1		2002-02-27
DE10208435		2002-02-27
AU2002254921		2002-03-05
AU2002244738		2002-03-05
PCT/EP2002/002403 WO2002071249A2 (en)	2001-03-05	2002-03-05	Method and devices for treating and/or processing data
PCT/EP2002/002398 WO2002071248A2 (en)	2001-03-05	2002-03-05	Methods and devices for treating and/or processing data
AU2002257615		2002-03-05
PCT/EP2002/002402 WO2002071196A2 (en)	2001-03-05	2002-03-05	Methods and devices for treating and processing data
DE10212621		2002-03-21
DE10212621.6		2002-03-21
DE10212622A DE10212622A1 (en)	2002-03-21	2002-03-21	Computer program translation method allows classic language to be converted for system with re-configurable architecture
DE10212622.4		2002-03-21
EP02009868		2002-05-02
DE10219681		2002-05-02
DE10219681.8		2002-05-02
EP02009868.7		2002-05-02
DE10226186.5		2002-06-12
DE10226186A DE10226186A1 (en)	2002-02-15	2002-06-12	Data processing unit has logic cell clock specifying arrangement that is designed to specify a first clock for at least a first cell and a further clock for at least a further cell depending on the state
DE10227650A DE10227650A1 (en)	2001-06-20	2002-06-20	Reconfigurable elements
DE10227650.1		2002-06-20
DE10236271.8		2002-08-07
DE10236271		2002-08-07
DE10238174A DE10238174A1 (en)	2002-08-07	2002-08-21	Router for use in networked data processing has a configuration method for use with reconfigurable multi-dimensional fields that includes specifications for handling back-couplings
DE10238174.7		2002-08-21
DE10240000A DE10240000A1 (en)	2002-08-27	2002-08-27	Router for use in networked data processing has a configuration method for use with reconfigurable multi-dimensional fields that includes specifications for handling back-couplings
DE10240022		2002-08-27
DE10240022.9		2002-08-27
DE10240000.8		2002-08-27
PCT/DE2002/003278 WO2003023616A2 (en)	2001-09-03	2002-09-03	Method for debugging reconfigurable architectures
AU2002336896		2002-09-03
AU2002342668		2002-09-09
PCT/EP2002/010084 WO2003025770A2 (en)	2001-09-07	2002-09-09	Reconfigurable system
PCT/EP2002/010479 WO2003025781A2 (en)	2001-09-19	2002-09-18	Router

Publications (1)

Publication Number	Publication Date
AU2002338729A1 true AU2002338729A1 (en)	2003-04-01

Family

ID=32315059

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
AU2002338729A Abandoned AU2002338729A1 (en)	2001-09-19	2002-09-18	Router

Country Status (3)

Country	Link
EP (1)	EP1466264B1 (en)
AU (1)	AU2002338729A1 (en)
WO (1)	WO2003025781A2 (en)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US7266725B2 (en)	2001-09-03	2007-09-04	Pact Xpp Technologies Ag	Method for debugging reconfigurable architectures
DE19651075A1 (en)	1996-12-09	1998-06-10	Pact Inf Tech Gmbh	Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like
DE19654593A1 (en)	1996-12-20	1998-07-02	Pact Inf Tech Gmbh	Reconfiguration procedure for programmable blocks at runtime
DE19654846A1 (en)	1996-12-27	1998-07-09	Pact Inf Tech Gmbh	Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.)
DE19704728A1 (en)	1997-02-08	1998-08-13	Pact Inf Tech Gmbh	Method for self-synchronization of configurable elements of a programmable module
US6542998B1 (en)	1997-02-08	2003-04-01	Pact Gmbh	Method of self-synchronization of configurable elements of a programmable module
DE19704742A1 (en)	1997-02-11	1998-09-24	Pact Inf Tech Gmbh	Internal bus system for DFPs, as well as modules with two- or multi-dimensional programmable cell structures, for coping with large amounts of data with high networking effort
EP2226732A3 (en)	2000-06-13	2016-04-06	PACT XPP Technologies AG	Cache hierarchy for a multicore processor
AU2002220600A1 (en)	2000-10-06	2002-04-15	Pact Informationstechnologie Gmbh	Cell system with segmented intermediate cell structure
US8058899B2 (en)	2000-10-06	2011-11-15	Martin Vorbach	Logic cell array and bus system
US6990555B2 (en)	2001-01-09	2006-01-24	Pact Xpp Technologies Ag	Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US7444531B2 (en)	2001-03-05	2008-10-28	Pact Xpp Technologies Ag	Methods and devices for treating and processing data
US7581076B2 (en)	2001-03-05	2009-08-25	Pact Xpp Technologies Ag	Methods and devices for treating and/or processing data
US9037807B2 (en)	2001-03-05	2015-05-19	Pact Xpp Technologies Ag	Processor arrangement on a chip including data processing, memory, and interface elements
US7210129B2 (en)	2001-08-16	2007-04-24	Pact Xpp Technologies Ag	Method for translating programs for reconfigurable architectures
US7996827B2 (en)	2001-08-16	2011-08-09	Martin Vorbach	Method for the translation of programs for reconfigurable architectures
US7434191B2 (en)	2001-09-03	2008-10-07	Pact Xpp Technologies Ag	Router
US7577822B2 (en)	2001-12-14	2009-08-18	Pact Xpp Technologies Ag	Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
AU2003214003A1 (en)	2002-02-18	2003-09-09	Pact Xpp Technologies Ag	Bus systems and method for reconfiguration
US8914590B2 (en)	2002-08-07	2014-12-16	Pact Xpp Technologies Ag	Data processing method and device
WO2004038599A1 (en)	2002-09-06	2004-05-06	Pact Xpp Technologies Ag	Reconfigurable sequencer structure
US7693257B2 (en)	2006-06-29	2010-04-06	Accuray Incorporated	Treatment delivery optimization
US8078834B2 (en)	2008-01-09	2011-12-13	Analog Devices, Inc.	Processor architectures for enhanced computational capability
US8108653B2 (en) *	2008-01-09	2012-01-31	Analog Devices, Inc.	Processor architectures for enhanced computational capability and low latency

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
EP0190813B1 (en) *	1985-01-29	1991-09-18	The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and	Processing cell for fault tolerant arrays
DE4416881C2 (en)	1993-05-13	1998-03-19	Pact Inf Tech Gmbh	Method for operating a data processing device
WO2002071249A2 (en)	2001-03-05	2002-09-12	Pact Informationstechnologie Gmbh	Method and devices for treating and/or processing data
DE19651075A1 (en)	1996-12-09	1998-06-10	Pact Inf Tech Gmbh	Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like
DE19654593A1 (en)	1996-12-20	1998-07-02	Pact Inf Tech Gmbh	Reconfiguration procedure for programmable blocks at runtime
DE19654595A1 (en)	1996-12-20	1998-07-02	Pact Inf Tech Gmbh	I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures
DE19654846A1 (en)	1996-12-27	1998-07-09	Pact Inf Tech Gmbh	Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.)
DE19704044A1 (en)	1997-02-04	1998-08-13	Pact Inf Tech Gmbh	Address generation with systems having programmable modules
DE19704728A1 (en)	1997-02-08	1998-08-13	Pact Inf Tech Gmbh	Method for self-synchronization of configurable elements of a programmable module
DE19861088A1 (en)	1997-12-22	2000-02-10	Pact Inf Tech Gmbh	Repairing integrated circuits by replacing subassemblies with substitutes
DE19807872A1 (en)	1998-02-25	1999-08-26	Pact Inf Tech Gmbh	Method of managing configuration data in data flow processors
DE10028397A1 (en)	2000-06-13	2001-12-20	Pact Inf Tech Gmbh	Registration method in operating a reconfigurable unit, involves evaluating acknowledgement signals of configurable cells with time offset to configuration
DE19926538A1 (en)	1999-06-10	2000-12-14	Pact Inf Tech Gmbh	Hardware with decoupled configuration register partitions data flow or control flow graphs into time-separated sub-graphs and forms and implements them sequentially on a component
DE10081643D2 (en)	1999-06-10	2002-05-29	Pact Inf Tech Gmbh	Sequence partitioning on cell structures
DE10103624A1 (en)	2000-02-10	2001-09-20	Traub Otto	Basic frame has recliner element with surface, fixed handles and support
DE10036627A1 (en)	2000-07-24	2002-02-14	Pact Inf Tech Gmbh	Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
AU2002220600A1 (en)	2000-10-06	2002-04-15	Pact Informationstechnologie Gmbh	Cell system with segmented intermediate cell structure
AU2002254921A1 (en)	2001-03-05	2002-09-19	Pact Informationstechnologie Gmbh	Methods and devices for treating and processing data

2002
- 2002-09-18 AU AU2002338729A patent/AU2002338729A1/en not_active Abandoned
- 2002-09-18 EP EP02777144A patent/EP1466264B1/en not_active Expired - Lifetime
- 2002-09-18 WO PCT/EP2002/010479 patent/WO2003025781A2/en not_active Ceased

Also Published As

Publication number	Publication date
WO2003025781A2 (en)	2003-03-27
EP1466264B1 (en)	2011-09-14
EP1466264A2 (en)	2004-10-13
WO2003025781A3 (en)	2004-05-27

Publication	Publication Date	Title
AU2002360508A1 (en)	2003-06-23	Substituted hydroxyethylamines
AU149383S (en)	2002-09-24	Router
AU2002338729A1 (en)	2003-04-01	Router
AU2002313565A1 (en)	2003-03-18	Putter-heads
AU2002251024A1 (en)	2003-03-20	Substituted fluoroalcoxyphenylsulfonylurea
AU2002321215A1 (en)	2003-05-22	Substituted 4-aminocyclohexanols
AU2002313943A1 (en)	2003-02-24	Electromobile
AU2002226571A1 (en)	2002-08-12	Biligands
AU2001100406A4 (en)	2001-11-01	DriverSMS
AU2002313073A1 (en)	2002-12-03	Phytocystatin
AU2001256515A1 (en)	2002-11-25	Router
AU2002257925A1 (en)	2003-06-30	Numberplates
AU2002100746A4 (en)	2003-05-29	Adrail
AU2001100532A4 (en)	2001-11-29	FonePark
AU2001100522A4 (en)	2001-11-22	e-Trans
AU2001100214A4 (en)	2001-08-30	Dolly-trolley
AU2001100338A4 (en)	2001-10-04	Sunglove
AU2001255071A1 (en)	2002-10-15	Router bit
AU2002322343A1 (en)	2003-03-03	Improved inductrack configuration
AU2002317861A1 (en)	2003-01-29	Substituted benzo-nitro-heterocycles
AU2002358003A1 (en)	2003-06-10	Substituted acylaminophenyluracils
AU2002321430A1 (en)	2003-02-24	Wavelength router
AU2002317838A1 (en)	2003-01-08	Plasma-accelerator configuration
AU2001298048A1 (en)	2003-05-19	**
AU2002362548A1 (en)	2003-04-07	**

Legal Events

Date	Code	Title	Description
2004-06-17	MK6	Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase