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AU2002222830A1 - Transmitter circuit comprising timing deskewing means - Google Patents

Transmitter circuit comprising timing deskewing means

Info

Publication number
AU2002222830A1
AU2002222830A1 AU2002222830A AU2283002A AU2002222830A1 AU 2002222830 A1 AU2002222830 A1 AU 2002222830A1 AU 2002222830 A AU2002222830 A AU 2002222830A AU 2283002 A AU2283002 A AU 2283002A AU 2002222830 A1 AU2002222830 A1 AU 2002222830A1
Authority
AU
Australia
Prior art keywords
transmitter circuit
timing
deskewing means
timing deskewing
transmitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002222830A
Inventor
Igor Anatolievich Abrosimov
Vasily Grigorievich Atyunin
Alexander Roger Deas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=26936369&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=AU2002222830(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Individual filed Critical Individual
Publication of AU2002222830A1 publication Critical patent/AU2002222830A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/32—Reducing cross-talk, e.g. by compensating
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0292—Arrangements specific to the receiver end

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Logic Circuits (AREA)
  • Information Transfer Systems (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
AU2002222830A 2000-10-31 2001-10-31 Transmitter circuit comprising timing deskewing means Abandoned AU2002222830A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US24417900P 2000-10-31 2000-10-31
US60/244,179 2000-10-31
US31029901P 2001-08-06 2001-08-06
US60/310,299 2001-08-06
PCT/RU2001/000482 WO2002037679A2 (en) 2000-10-31 2001-10-31 Transmitter circuit comprising timing deskewing means

Publications (1)

Publication Number Publication Date
AU2002222830A1 true AU2002222830A1 (en) 2002-05-15

Family

ID=26936369

Family Applications (2)

Application Number Title Priority Date Filing Date
AU2001290402A Abandoned AU2001290402A1 (en) 2000-10-31 2001-09-06 Channel time calibration means
AU2002222830A Abandoned AU2002222830A1 (en) 2000-10-31 2001-10-31 Transmitter circuit comprising timing deskewing means

Family Applications Before (1)

Application Number Title Priority Date Filing Date
AU2001290402A Abandoned AU2001290402A1 (en) 2000-10-31 2001-09-06 Channel time calibration means

Country Status (6)

Country Link
US (1) US6480021B2 (en)
EP (1) EP1405154B1 (en)
JP (1) JP4017518B2 (en)
AU (2) AU2001290402A1 (en)
DE (1) DE60111654T2 (en)
WO (2) WO2002039629A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7099293B2 (en) * 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
US7961000B1 (en) * 2004-09-01 2011-06-14 Cypress Semiconductor Corporation Impedance matching circuit and method
WO2006052720A1 (en) * 2004-11-05 2006-05-18 Qualcomm Incorporated Integrated circuit with adaptive speed binning
US7622543B2 (en) * 2004-11-09 2009-11-24 E.I. Du Pont De Nemours And Company Polymerization of macrocyclic polyester oligomers using N-heterocyclic carbene catalysts
US8081706B2 (en) * 2005-08-24 2011-12-20 Altera Corporation Lane-to-lane skew reduction in multi-channel, high-speed, transceiver circuitry
JP4718933B2 (en) * 2005-08-24 2011-07-06 富士通株式会社 Parallel signal skew adjustment circuit and skew adjustment method
KR100666179B1 (en) * 2005-11-18 2007-01-09 삼성전자주식회사 Output driver and output driving method for initial strengthening of output data by timing
US20110036617A1 (en) * 2007-08-03 2011-02-17 Leonid Kokurin Compensating Conductive Circuit
US10235103B2 (en) 2014-04-24 2019-03-19 Xitore, Inc. Apparatus, system, and method of byte addressable and block addressable storage and retrival of data to and from non-volatile storage memory
FR3071938A1 (en) 2017-10-02 2019-04-05 Stmicroelectronics (Rousset) Sas DETECTION OF A TEMPORAL CONDITION ON A BIFILAR BUS
CN111277291A (en) * 2018-11-16 2020-06-12 英业达科技有限公司 Circuit arrangement
KR102549607B1 (en) 2019-01-28 2023-06-29 삼성전자주식회사 Electronic circuit capable of selectively compensating for crosstalk noise and inter-symbol interference

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5570029A (en) * 1994-03-30 1996-10-29 Fluke Corporation Cable crosstalk measurement system
JP2889113B2 (en) * 1994-04-26 1999-05-10 インターナショナル・ビジネス・マシーンズ・コーポレイション Delay generation device, data processing system and data transmission system
CA2302367C (en) * 1997-09-04 2003-10-07 Deog-Kyoon Jeong Controllable delays in multiple synchronized signals for reduced electromagnetic interference at peak frequencies
US5953521A (en) * 1997-11-03 1999-09-14 Intel Corporation Data-pattern induced skew reducer
JP4634605B2 (en) * 1998-03-12 2011-02-16 エルピーダメモリ株式会社 Data transmission system
WO2000000836A1 (en) * 1998-06-29 2000-01-06 Iliya Valeryevich Klochkov A skew calibration means and a method of skew calibration
US6275077B1 (en) * 1999-08-31 2001-08-14 Sun Microsystems, Inc. Method and apparatus for programmable adjustment of bus driver propagation times
US6380758B1 (en) * 2000-09-29 2002-04-30 Intel Corporation Impedance control for wide range loaded signals using distributed methodology

Also Published As

Publication number Publication date
JP2004532536A (en) 2004-10-21
AU2001290402A1 (en) 2002-05-21
DE60111654D1 (en) 2005-07-28
EP1405154B1 (en) 2005-06-22
EP1405154A2 (en) 2004-04-07
US20020051506A1 (en) 2002-05-02
DE60111654T2 (en) 2006-05-18
WO2002037679A8 (en) 2002-07-11
US6480021B2 (en) 2002-11-12
WO2002039629A2 (en) 2002-05-16
JP4017518B2 (en) 2007-12-05
WO2002039629A3 (en) 2003-10-02
WO2002037679A3 (en) 2004-02-12
WO2002039629A9 (en) 2002-12-12
WO2002037679A2 (en) 2002-05-10

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