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AU2002218136A1 - Data path arrangement - Google Patents

Data path arrangement

Info

Publication number
AU2002218136A1
AU2002218136A1 AU2002218136A AU1813602A AU2002218136A1 AU 2002218136 A1 AU2002218136 A1 AU 2002218136A1 AU 2002218136 A AU2002218136 A AU 2002218136A AU 1813602 A AU1813602 A AU 1813602A AU 2002218136 A1 AU2002218136 A1 AU 2002218136A1
Authority
AU
Australia
Prior art keywords
data path
path arrangement
arrangement
data
path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002218136A
Inventor
Wolfram Drescher
Gerhard Fettweis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP Semiconductors Germany GmbH
Original Assignee
Systemonic AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Systemonic AG filed Critical Systemonic AG
Publication of AU2002218136A1 publication Critical patent/AU2002218136A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
AU2002218136A 2000-10-16 2001-10-15 Data path arrangement Abandoned AU2002218136A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10051284.4 2000-10-16
DE10051284A DE10051284A1 (en) 2000-10-16 2000-10-16 Data path arrangement e.g. for CPU, has processor bus joined to input of input register and to output of output register
PCT/DE2001/003915 WO2002033569A2 (en) 2000-10-16 2001-10-15 Data path arrangement

Publications (1)

Publication Number Publication Date
AU2002218136A1 true AU2002218136A1 (en) 2002-04-29

Family

ID=7659995

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002218136A Abandoned AU2002218136A1 (en) 2000-10-16 2001-10-15 Data path arrangement

Country Status (6)

Country Link
US (1) US20040044818A1 (en)
EP (1) EP1330726A2 (en)
JP (1) JP2004512598A (en)
AU (1) AU2002218136A1 (en)
DE (1) DE10051284A1 (en)
WO (1) WO2002033569A2 (en)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4203157A (en) * 1978-09-05 1980-05-13 Motorola, Inc. Carry anticipator circuit and method
US4272828A (en) * 1979-01-03 1981-06-09 Honeywell Information Systems Inc. Arithmetic logic apparatus for a data processing system
JPS5757345A (en) * 1980-09-24 1982-04-06 Toshiba Corp Data controller
JPS60258671A (en) * 1984-06-05 1985-12-20 Nec Corp Processor
US4641276A (en) * 1984-10-22 1987-02-03 General Electric Company Serial-parallel data transfer system for VLSI data paths
KR860007588A (en) * 1985-03-25 1986-10-15 미쓰다 가쓰시게 Data processing device
US5692139A (en) * 1988-01-11 1997-11-25 North American Philips Corporation, Signetics Div. VLIW processing device including improved memory for avoiding collisions without an excessive number of ports
JPH0758460B2 (en) * 1988-05-25 1995-06-21 日本電気株式会社 Floating-point arithmetic normalization control method
US5301340A (en) * 1990-10-31 1994-04-05 International Business Machines Corporation IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to every register file per cycle
US7114056B2 (en) * 1998-12-03 2006-09-26 Sun Microsystems, Inc. Local and global register partitioning in a VLIW processor

Also Published As

Publication number Publication date
WO2002033569A2 (en) 2002-04-25
JP2004512598A (en) 2004-04-22
US20040044818A1 (en) 2004-03-04
EP1330726A2 (en) 2003-07-30
WO2002033569A3 (en) 2003-01-03
DE10051284A1 (en) 2002-04-25

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