AU2001290107A1 - Register assignment in a processor - Google Patents
Register assignment in a processorInfo
- Publication number
- AU2001290107A1 AU2001290107A1 AU2001290107A AU9010701A AU2001290107A1 AU 2001290107 A1 AU2001290107 A1 AU 2001290107A1 AU 2001290107 A AU2001290107 A AU 2001290107A AU 9010701 A AU9010701 A AU 9010701A AU 2001290107 A1 AU2001290107 A1 AU 2001290107A1
- Authority
- AU
- Australia
- Prior art keywords
- processor
- register assignment
- assignment
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/002—Countermeasures against attacks on cryptographic mechanisms
- H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/08—Randomization, e.g. dummy operations or using noise
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
- H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0023697 | 2000-09-27 | ||
| GBGB0023697.6A GB0023697D0 (en) | 2000-09-27 | 2000-09-27 | Register assignment in a processor |
| PCT/GB2001/004294 WO2002027476A1 (en) | 2000-09-27 | 2001-09-26 | Register assignment in a processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AU2001290107A1 true AU2001290107A1 (en) | 2002-04-08 |
Family
ID=9900249
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU2001290107A Abandoned AU2001290107A1 (en) | 2000-09-27 | 2001-09-26 | Register assignment in a processor |
Country Status (3)
| Country | Link |
|---|---|
| AU (1) | AU2001290107A1 (en) |
| GB (1) | GB0023697D0 (en) |
| WO (1) | WO2002027476A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9424034B2 (en) * | 2013-06-28 | 2016-08-23 | Intel Corporation | Multiple register memory access instructions, processors, methods, and systems |
| US11017125B2 (en) * | 2016-12-13 | 2021-05-25 | University Of Florida Research Foundation, Incorporated | Uniquified FPGA virtualization approach to hardware security |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0686912B1 (en) * | 1994-06-03 | 1998-12-16 | Motorola, Inc. | Data processor with an execution unit for performing load instructions and method of operation |
| US5694565A (en) * | 1995-09-11 | 1997-12-02 | International Business Machines Corporation | Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions |
| US6035394A (en) * | 1998-02-17 | 2000-03-07 | International Business Machines Corporation | System for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallel |
-
2000
- 2000-09-27 GB GBGB0023697.6A patent/GB0023697D0/en not_active Ceased
-
2001
- 2001-09-26 AU AU2001290107A patent/AU2001290107A1/en not_active Abandoned
- 2001-09-26 WO PCT/GB2001/004294 patent/WO2002027476A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| WO2002027476A1 (en) | 2002-04-04 |
| GB0023697D0 (en) | 2000-11-08 |
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