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AU2001277224A1 - Multiple block sequential memory management - Google Patents

Multiple block sequential memory management

Info

Publication number
AU2001277224A1
AU2001277224A1 AU2001277224A AU7722401A AU2001277224A1 AU 2001277224 A1 AU2001277224 A1 AU 2001277224A1 AU 2001277224 A AU2001277224 A AU 2001277224A AU 7722401 A AU7722401 A AU 7722401A AU 2001277224 A1 AU2001277224 A1 AU 2001277224A1
Authority
AU
Australia
Prior art keywords
memory management
multiple block
sequential memory
block sequential
management
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001277224A
Inventor
Karlon West
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Times N Systems Inc
Original Assignee
Times N Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Times N Systems Inc filed Critical Times N Systems Inc
Publication of AU2001277224A1 publication Critical patent/AU2001277224A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T137/00—Fluid handling
    • Y10T137/2496—Self-proportioning or correlating systems
    • Y10T137/2514—Self-proportioning flow systems
    • Y10T137/2521—Flow comparison or differential response

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU2001277224A 2000-07-26 2001-07-26 Multiple block sequential memory management Abandoned AU2001277224A1 (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US22097400P 2000-07-26 2000-07-26
US22074800P 2000-07-26 2000-07-26
US60/220,748 2000-07-26
US60/220,974 2000-07-26
US09/912,834 US6665777B2 (en) 2000-07-26 2001-07-25 Method, apparatus, network, and kit for multiple block sequential memory management
US09/912,834 2001-07-25
PCT/US2001/023863 WO2002008907A2 (en) 2000-07-26 2001-07-26 Multiple block sequential memory management

Publications (1)

Publication Number Publication Date
AU2001277224A1 true AU2001277224A1 (en) 2002-02-05

Family

ID=27396828

Family Applications (2)

Application Number Title Priority Date Filing Date
AU2001279085A Abandoned AU2001279085A1 (en) 2000-07-26 2001-07-26 Shared as needed programming model
AU2001277224A Abandoned AU2001277224A1 (en) 2000-07-26 2001-07-26 Multiple block sequential memory management

Family Applications Before (1)

Application Number Title Priority Date Filing Date
AU2001279085A Abandoned AU2001279085A1 (en) 2000-07-26 2001-07-26 Shared as needed programming model

Country Status (3)

Country Link
US (1) US6665777B2 (en)
AU (2) AU2001279085A1 (en)
WO (1) WO2002008907A2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020013822A1 (en) * 2000-07-26 2002-01-31 West Karlon K. Shared as needed programming model
US6754789B2 (en) * 2002-02-22 2004-06-22 Mcgraw-Edison Company Distributed fault resilient shared memory
US8060680B2 (en) * 2002-09-16 2011-11-15 Hewlett-Packard Development Company, L.P. Method of allocating memory
CA2422252C (en) * 2003-03-14 2008-09-02 Ibm Canada Limited - Ibm Canada Limitee Reduced synchronization reservation system and method for a shared memory buffer
US8225327B2 (en) * 2005-09-15 2012-07-17 International Business Machines Corporation Synchronizing access to a shared resource utilizing selective locking
FR2919401B1 (en) * 2007-07-24 2016-01-15 Thales Sa METHOD FOR TESTING DATA PATHS IN AN ELECTRONIC CIRCUIT
US20120144104A1 (en) * 2010-12-02 2012-06-07 Advanced Micro Devices, Inc. Partitioning of Memory Device for Multi-Client Computing System
US9817700B2 (en) * 2011-04-26 2017-11-14 International Business Machines Corporation Dynamic data partitioning for optimal resource utilization in a parallel data processing system
US20130262814A1 (en) * 2012-03-29 2013-10-03 Advanced Micro Devices, Inc. Mapping Memory Instructions into a Shared Memory Address Place
CN104753814B (en) * 2013-12-31 2018-04-06 国家计算机网络与信息安全管理中心 Packet distribution processing method based on network card
CN106168916B (en) * 2016-06-24 2018-06-26 北京百度网讯科技有限公司 Data transmission method and system

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52123137A (en) 1976-04-09 1977-10-17 Hitachi Ltd Duplication memory control unit
DE69124285T2 (en) 1990-05-18 1997-08-14 Fujitsu Ltd Data processing system with an input / output path separation mechanism and method for controlling the data processing system
US5448716A (en) 1992-10-30 1995-09-05 International Business Machines Corporation Apparatus and method for booting a multiple processor system having a global/local memory architecture
US5604882A (en) 1993-08-27 1997-02-18 International Business Machines Corporation System and method for empty notification from peer cache units to global storage control unit in a multiprocessor data processing system
US5566321A (en) * 1993-12-13 1996-10-15 Cray Research, Inc. Method of managing distributed memory within a massively parallel processing system
JP3253473B2 (en) * 1995-01-27 2002-02-04 富士通株式会社 Method and apparatus for resynchronization processing of duplicated shared memory
CA2146170C (en) * 1995-04-03 2001-04-03 Matthew A. Huras Server detection of client process termination
US5765157A (en) 1996-06-05 1998-06-09 Sun Microsystems, Inc. Computer system and method for executing threads of execution with reduced run-time memory space requirements
US5946710A (en) * 1996-11-14 1999-08-31 Unisys Corporation Selectable two-way, four-way double cache interleave scheme
US6026474A (en) * 1996-11-22 2000-02-15 Mangosoft Corporation Shared client-side web caching using globally addressable memory
US6360303B1 (en) 1997-09-30 2002-03-19 Compaq Computer Corporation Partitioning memory shared by multiple processors of a distributed processing system
US6026401A (en) * 1997-10-14 2000-02-15 International Business Machines Corporation Locking tool data objects in a framework environment
EP0917056B1 (en) 1997-11-04 2008-01-09 Compaq Computer Corporation A multi-processor computer system and a method of operating thereof
US6070194A (en) * 1997-12-17 2000-05-30 Advanced Micro Devices, Inc. Using an index and count mechanism to coordinate access to a shared resource by interactive devices
US6157989A (en) * 1998-06-03 2000-12-05 Motorola, Inc. Dynamic bus arbitration priority and task switching based on shared memory fullness in a multi-processor system
US6629152B2 (en) * 1998-06-29 2003-09-30 International Business Machines Corporation Message passing using shared memory of a computer
US6314501B1 (en) 1998-07-23 2001-11-06 Unisys Corporation Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory
US6427195B1 (en) 2000-06-13 2002-07-30 Hewlett-Packard Company Thread local cache memory allocator in a multitasking operating system

Also Published As

Publication number Publication date
WO2002008907A3 (en) 2002-08-08
WO2002008907A2 (en) 2002-01-31
AU2001279085A1 (en) 2002-02-05
US6665777B2 (en) 2003-12-16
US20020029800A1 (en) 2002-03-14

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