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AU2001276732A1 - Memory access controller - Google Patents

Memory access controller

Info

Publication number
AU2001276732A1
AU2001276732A1 AU2001276732A AU7673201A AU2001276732A1 AU 2001276732 A1 AU2001276732 A1 AU 2001276732A1 AU 2001276732 A AU2001276732 A AU 2001276732A AU 7673201 A AU7673201 A AU 7673201A AU 2001276732 A1 AU2001276732 A1 AU 2001276732A1
Authority
AU
Australia
Prior art keywords
memory access
access controller
controller
memory
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001276732A
Inventor
Tetsuya Ikeda
Minoru Okamoto
Toshitsugu Sawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of AU2001276732A1 publication Critical patent/AU2001276732A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System (AREA)
  • Executing Machine-Instructions (AREA)
AU2001276732A 2000-08-30 2001-08-06 Memory access controller Abandoned AU2001276732A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000261817A JP2002073406A (en) 2000-08-30 2000-08-30 Memory access control device
JP2000-261817 2000-08-30
PCT/JP2001/006720 WO2002019113A1 (en) 2000-08-30 2001-08-06 Memory access controller

Publications (1)

Publication Number Publication Date
AU2001276732A1 true AU2001276732A1 (en) 2002-03-13

Family

ID=18749598

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001276732A Abandoned AU2001276732A1 (en) 2000-08-30 2001-08-06 Memory access controller

Country Status (6)

Country Link
US (1) US20020174312A1 (en)
EP (1) EP1315090A1 (en)
JP (1) JP2002073406A (en)
CN (1) CN1388928A (en)
AU (1) AU2001276732A1 (en)
WO (1) WO2002019113A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200731078A (en) * 2005-12-27 2007-08-16 Via Tech Inc Computer system with clock-controlled wait states
KR100782307B1 (en) * 2006-04-26 2007-12-06 삼성전자주식회사 How to control the operating clock frequency of the hard disk drive, the recording medium, and the hard disk drive
FR2916066A1 (en) * 2007-05-10 2008-11-14 Samsung Electronics Co Ltd METHOD FOR OPERATING A MEMORY DEVICE AND ELECTRONIC DEVICE
KR100914265B1 (en) 2007-05-10 2009-08-27 삼성전자주식회사 Nonvolatile memory device, memory system including it and how to read it
TWI361354B (en) 2007-09-11 2012-04-01 Realtek Semiconductor Corp Memory access controlling apparatus and related method
CN101452416B (en) * 2007-11-28 2012-07-18 瑞昱半导体股份有限公司 Memory access control device and related method
CH699207B1 (en) * 2008-07-25 2013-05-15 Em Microelectronic Marin Sa shared memory processor circuit.
CN104346484A (en) * 2013-07-31 2015-02-11 上海华虹集成电路有限责任公司 Processor chip simulator with nonvolatile memory
CN105242874B (en) * 2015-09-09 2017-03-08 天津瑞发科半导体技术有限公司 A kind of flash memories control device and a kind of flash memory flash memory device
WO2023155165A1 (en) * 2022-02-18 2023-08-24 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for performing periodic task

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4588097A (en) * 1984-04-03 1986-05-13 Hauser Ivo J Safety closure cap for containers
JPH02311943A (en) * 1989-05-29 1990-12-27 Oki Electric Ind Co Ltd Wait action control circuit for cpu
GB9012041D0 (en) * 1990-05-30 1990-07-18 Beeson & Sons Ltd Improvements in or relating to containers
JPH0635839A (en) * 1992-07-10 1994-02-10 Hitachi Ltd System controller
JPH0675852A (en) * 1992-08-26 1994-03-18 Yaskawa Electric Corp Memory access speedup circuit
DE4231703C2 (en) * 1992-09-22 1996-01-11 Siemens Ag Microprocessor with CPU and EEPROM
JPH08147161A (en) * 1994-11-21 1996-06-07 Nec Corp Data processor
US5627835A (en) * 1995-04-04 1997-05-06 Oki Telecom Artificial window size interrupt reduction system for CDMA receiver
JP3562215B2 (en) * 1997-05-13 2004-09-08 セイコーエプソン株式会社 Microcomputer and electronic equipment
JPH11167515A (en) * 1997-10-03 1999-06-22 Matsushita Electric Ind Co Ltd Data transmission device and data transmission method

Also Published As

Publication number Publication date
EP1315090A1 (en) 2003-05-28
US20020174312A1 (en) 2002-11-21
CN1388928A (en) 2003-01-01
WO2002019113A1 (en) 2002-03-07
JP2002073406A (en) 2002-03-12

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