AU2001269903A1 - Block-level read while write method and apparatus - Google Patents
Block-level read while write method and apparatusInfo
- Publication number
- AU2001269903A1 AU2001269903A1 AU2001269903A AU6990301A AU2001269903A1 AU 2001269903 A1 AU2001269903 A1 AU 2001269903A1 AU 2001269903 A AU2001269903 A AU 2001269903A AU 6990301 A AU6990301 A AU 6990301A AU 2001269903 A1 AU2001269903 A1 AU 2001269903A1
- Authority
- AU
- Australia
- Prior art keywords
- block
- write method
- level read
- read
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/608,454 US6772273B1 (en) | 2000-06-29 | 2000-06-29 | Block-level read while write method and apparatus |
| US09608454 | 2000-06-29 | ||
| PCT/US2001/019505 WO2002003388A2 (en) | 2000-06-29 | 2001-06-15 | Block-level read while write method and apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AU2001269903A1 true AU2001269903A1 (en) | 2002-01-14 |
Family
ID=24436577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU2001269903A Abandoned AU2001269903A1 (en) | 2000-06-29 | 2001-06-15 | Block-level read while write method and apparatus |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6772273B1 (en) |
| EP (1) | EP1297529A2 (en) |
| JP (1) | JP2004509426A (en) |
| KR (1) | KR100525794B1 (en) |
| CN (1) | CN1280833C (en) |
| AU (1) | AU2001269903A1 (en) |
| TW (1) | TWI261252B (en) |
| WO (1) | WO2002003388A2 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4061272B2 (en) * | 2002-01-09 | 2008-03-12 | 株式会社ルネサステクノロジ | Memory system and memory card |
| KR100481857B1 (en) * | 2002-08-14 | 2005-04-11 | 삼성전자주식회사 | Flash memory device having decoder to reduce chip area and to implement independent operation of each bank |
| CN100433194C (en) * | 2002-12-10 | 2008-11-12 | 华邦电子股份有限公司 | Flash memory with elastic region-arranging partition and forming method |
| US6996635B2 (en) * | 2003-08-22 | 2006-02-07 | International Business Machines Corporation | Apparatus and method to activate transparent data storage drive firmware updates |
| US7562180B2 (en) | 2006-03-28 | 2009-07-14 | Nokia Corporation | Method and device for reduced read latency of non-volatile memory |
| WO2009052525A1 (en) | 2007-10-19 | 2009-04-23 | Virident Systems, Inc. | Managing memory systems containing components with asymmetric characteristics |
| US8027192B2 (en) * | 2008-08-20 | 2011-09-27 | Samsung Electronics Co., Ltd. | Resistive memory devices using assymetrical bitline charging and discharging |
| CN102257482B (en) * | 2008-12-19 | 2015-06-03 | 惠普开发有限公司 | Redundant data storage for uniform read latency |
| US8433845B2 (en) | 2009-04-08 | 2013-04-30 | Google Inc. | Data storage device which serializes memory device ready/busy signals |
| US8250271B2 (en) | 2009-04-08 | 2012-08-21 | Google Inc. | Command and interrupt grouping for a data storage device |
| US8995161B2 (en) | 2011-06-10 | 2015-03-31 | Micron Technology, Inc. | Apparatus and methods to perform read-while write (RWW) operations |
| US10340010B2 (en) * | 2016-08-16 | 2019-07-02 | Silicon Storage Technology, Inc. | Method and apparatus for configuring array columns and rows for accessing flash memory cells |
| US10719248B2 (en) * | 2018-04-20 | 2020-07-21 | Micron Technology, Inc. | Apparatuses and methods for counter update operations |
| CN111739569B (en) * | 2020-06-19 | 2022-04-26 | 西安微电子技术研究所 | SDRAM (synchronous dynamic random access memory) control system and control method for reading and writing simultaneously |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5245570A (en) * | 1990-12-21 | 1993-09-14 | Intel Corporation | Floating gate non-volatile memory blocks and select transistors |
| US5245572A (en) | 1991-07-30 | 1993-09-14 | Intel Corporation | Floating gate nonvolatile memory with reading while writing capability |
| US5701143A (en) * | 1995-01-31 | 1997-12-23 | Cirrus Logic, Inc. | Circuits, systems and methods for improving row select speed in a row select memory device |
| JPH08263361A (en) | 1995-03-23 | 1996-10-11 | Mitsubishi Electric Corp | Flash memory card |
| EP0745995B1 (en) | 1995-05-05 | 2001-04-11 | STMicroelectronics S.r.l. | Nonvolatile, in particular flash-EEPROM, memory device |
| US6081878A (en) | 1997-03-31 | 2000-06-27 | Lexar Media, Inc. | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
| US5796657A (en) | 1996-03-29 | 1998-08-18 | Aplus Integrated Circuits, Inc. | Flash memory with flexible erasing size from multi-byte to multi-block |
| US5867430A (en) | 1996-12-20 | 1999-02-02 | Advanced Micro Devices Inc | Bank architecture for a non-volatile memory enabling simultaneous reading and writing |
| US5847998A (en) | 1996-12-20 | 1998-12-08 | Advanced Micro Devices, Inc. | Non-volatile memory array that enables simultaneous read and write operations |
| US5896340A (en) * | 1997-07-07 | 1999-04-20 | Invox Technology | Multiple array architecture for analog or multi-bit-cell memory |
| JP3570879B2 (en) | 1997-07-09 | 2004-09-29 | 富士通株式会社 | Nonvolatile semiconductor memory device |
| US6088264A (en) | 1998-01-05 | 2000-07-11 | Intel Corporation | Flash memory partitioning for read-while-write operation |
| US5894437A (en) | 1998-01-23 | 1999-04-13 | Hyundai Elecronics America, Inc. | Concurrent read/write architecture for a flash memory |
| US5995415A (en) * | 1998-09-23 | 1999-11-30 | Advanced Micro Devices, Inc. | Simultaneous operation flash memory device with a flexible bank partition architecture |
| US6005803A (en) * | 1998-09-23 | 1999-12-21 | Advanced Micro Devices, Inc. | Memory address decoding circuit for a simultaneous operation flash memory device with a flexible bank partition architecture |
| DE60030876T2 (en) | 1999-04-01 | 2007-05-03 | Lexar Media, Inc., Fremont | Scope management of a high-capacity non-volatile memory |
| EP1047077A1 (en) * | 1999-04-21 | 2000-10-25 | STMicroelectronics S.r.l. | Nonvolatile memory device with double hierarchical decoding |
| US6091619A (en) * | 1999-04-23 | 2000-07-18 | Tektronix, Inc. | Array architecture for long record length fast-in slow-out (FISO) analog memory |
| US6310805B1 (en) * | 2000-03-07 | 2001-10-30 | Advanced Micro Devices, Inc. | Architecture for a dual-bank page mode memory with redundancy |
-
2000
- 2000-06-29 US US09/608,454 patent/US6772273B1/en not_active Expired - Lifetime
-
2001
- 2001-05-14 TW TW090111443A patent/TWI261252B/en not_active IP Right Cessation
- 2001-06-15 EP EP01948456A patent/EP1297529A2/en not_active Withdrawn
- 2001-06-15 WO PCT/US2001/019505 patent/WO2002003388A2/en not_active Ceased
- 2001-06-15 JP JP2002507376A patent/JP2004509426A/en active Pending
- 2001-06-15 KR KR10-2002-7017578A patent/KR100525794B1/en not_active Expired - Fee Related
- 2001-06-15 CN CNB018121276A patent/CN1280833C/en not_active Expired - Fee Related
- 2001-06-15 AU AU2001269903A patent/AU2001269903A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| EP1297529A2 (en) | 2003-04-02 |
| JP2004509426A (en) | 2004-03-25 |
| KR100525794B1 (en) | 2005-11-03 |
| WO2002003388A2 (en) | 2002-01-10 |
| CN1440555A (en) | 2003-09-03 |
| KR20030014276A (en) | 2003-02-15 |
| TWI261252B (en) | 2006-09-01 |
| WO2002003388A3 (en) | 2002-05-16 |
| CN1280833C (en) | 2006-10-18 |
| US6772273B1 (en) | 2004-08-03 |
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