AU2001243540A1 - A method and apparatus for diagnosing memory using self-testing circuits - Google Patents
A method and apparatus for diagnosing memory using self-testing circuitsInfo
- Publication number
- AU2001243540A1 AU2001243540A1 AU2001243540A AU4354001A AU2001243540A1 AU 2001243540 A1 AU2001243540 A1 AU 2001243540A1 AU 2001243540 A AU2001243540 A AU 2001243540A AU 4354001 A AU4354001 A AU 4354001A AU 2001243540 A1 AU2001243540 A1 AU 2001243540A1
- Authority
- AU
- Australia
- Prior art keywords
- self
- testing circuits
- diagnosing memory
- diagnosing
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09522279 | 2000-03-09 | ||
| US09/522,279 US6421794B1 (en) | 2000-03-09 | 2000-03-09 | Method and apparatus for diagnosing memory using self-testing circuits |
| PCT/US2001/007598 WO2001067463A1 (en) | 2000-03-09 | 2001-03-09 | A method and apparatus for diagnosing memory using self-testing circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AU2001243540A1 true AU2001243540A1 (en) | 2001-09-17 |
Family
ID=24080217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU2001243540A Abandoned AU2001243540A1 (en) | 2000-03-09 | 2001-03-09 | A method and apparatus for diagnosing memory using self-testing circuits |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6421794B1 (en) |
| AU (1) | AU2001243540A1 (en) |
| WO (1) | WO2001067463A1 (en) |
Families Citing this family (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6557129B1 (en) * | 1999-11-23 | 2003-04-29 | Janusz Rajski | Method and apparatus for selectively compacting test responses |
| JP2002099447A (en) * | 2000-09-22 | 2002-04-05 | Fujitsu Ltd | Processor |
| US6691252B2 (en) * | 2001-02-23 | 2004-02-10 | Hewlett-Packard Development Company, L.P. | Cache test sequence for single-ported row repair CAM |
| JP2002260398A (en) * | 2001-03-05 | 2002-09-13 | Mitsubishi Electric Corp | Multi-bit test circuit |
| US6732312B2 (en) * | 2001-03-09 | 2004-05-04 | Agilent Technologies, Inc. | Test vector compression method |
| US20040088614A1 (en) * | 2002-11-01 | 2004-05-06 | Ting-Chin Wu | Management system for defective memory |
| US7240260B2 (en) * | 2002-12-11 | 2007-07-03 | Intel Corporation | Stimulus generation |
| DE10258511A1 (en) * | 2002-12-14 | 2004-07-08 | Infineon Technologies Ag | Integrated circuit and associated packaged integrated circuit |
| CA2414632A1 (en) * | 2002-12-18 | 2004-06-18 | Logicvision, Inc. | Method and circuit for collecting memory failure information |
| US7409621B2 (en) * | 2002-12-26 | 2008-08-05 | Intel Corporation | On-chip jitter testing |
| DE10331068A1 (en) * | 2003-07-09 | 2005-02-17 | Infineon Technologies Ag | Method for reading error information from an integrated module and integrated memory module |
| DE10331607B4 (en) * | 2003-07-12 | 2007-02-15 | Infineon Technologies Ag | Output driver for an integrated circuit and method for driving an output driver |
| US7418637B2 (en) * | 2003-08-07 | 2008-08-26 | International Business Machines Corporation | Methods and apparatus for testing integrated circuits |
| US7444564B2 (en) * | 2003-11-19 | 2008-10-28 | International Business Machines Corporation | Automatic bit fail mapping for embedded memories with clock multipliers |
| KR100555532B1 (en) * | 2003-11-27 | 2006-03-03 | 삼성전자주식회사 | Memory test circuit and test system |
| US7251757B2 (en) * | 2003-12-02 | 2007-07-31 | International Business Machines Corporation | Memory testing |
| JP4157066B2 (en) * | 2004-03-29 | 2008-09-24 | 株式会社東芝 | Semiconductor integrated circuit |
| US7203873B1 (en) | 2004-06-04 | 2007-04-10 | Magma Design Automation, Inc. | Asynchronous control of memory self test |
| US7370249B2 (en) * | 2004-06-22 | 2008-05-06 | Intel Corporation | Method and apparatus for testing a memory array |
| US7263638B2 (en) * | 2004-12-16 | 2007-08-28 | Infineon Technologies Ag | Memory having test circuit |
| US7305602B2 (en) * | 2005-02-11 | 2007-12-04 | International Business Machines Corporation | Merged MISR and output register without performance impact for circuits under test |
| US20070070740A1 (en) * | 2005-09-28 | 2007-03-29 | Hynix Semiconductor Inc. | Semiconductor memory device having data-compress test mode |
| US7378833B2 (en) * | 2005-09-30 | 2008-05-27 | Intel Corporation | Supply voltage characteristic measurement |
| KR100810140B1 (en) * | 2005-11-16 | 2008-03-06 | 엠텍비젼 주식회사 | Selective test vector compression method and device |
| CN102129031B (en) | 2006-02-17 | 2015-03-11 | 明导公司 | Multi-stage test response compactors |
| KR100771875B1 (en) * | 2006-07-10 | 2007-11-01 | 삼성전자주식회사 | A semiconductor memory device and a test method for a semiconductor memory device capable of arbitrarily setting the number of memory cells to be tested |
| US20080077836A1 (en) * | 2006-09-27 | 2008-03-27 | Khoche A Jay | Diagnostic Information Capture from Memory Devices with Built-in Self Test |
| US7707467B2 (en) * | 2007-02-23 | 2010-04-27 | Micron Technology, Inc. | Input/output compression and pin reduction in an integrated circuit |
| TWI327732B (en) * | 2007-03-03 | 2010-07-21 | Nanya Technology Corp | Memory device and related testing method |
| US7793187B2 (en) * | 2007-06-07 | 2010-09-07 | Intel Corporation | Checking output from multiple execution units |
| US7904701B2 (en) * | 2007-06-07 | 2011-03-08 | Intel Corporation | Activating a design test mode in a graphics card having multiple execution units to bypass a host cache and transfer test instructions directly to an instruction cache |
| US7802146B2 (en) * | 2007-06-07 | 2010-09-21 | Intel Corporation | Loading test data into execution units in a graphics card to test execution |
| US20110055646A1 (en) * | 2007-09-18 | 2011-03-03 | Nilanjan Mukherjee | Fault diagnosis in a memory bist environment |
| WO2010102235A1 (en) * | 2009-03-05 | 2010-09-10 | Mentor Graphics Corporation | Fault diagnosis for non-volatile memories |
| US8296611B2 (en) * | 2010-03-29 | 2012-10-23 | Elite Semiconductor Memory Technology Inc. | Test circuit for input/output array and method and storage device thereof |
| KR101208960B1 (en) * | 2010-11-26 | 2012-12-06 | 에스케이하이닉스 주식회사 | Semiconductor apparatus and test method thereof |
| CN113886166B (en) * | 2021-08-31 | 2025-03-07 | 北京时代民芯科技有限公司 | Automatic test circuit for variable bit width memory in programmable logic device |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL7416755A (en) | 1974-12-23 | 1976-06-25 | Philips Nv | METHOD AND DEVICE FOR TESTING A DIGITAL MEMORY. |
| US4228528B2 (en) | 1979-02-09 | 1992-10-06 | Memory with redundant rows and columns | |
| JP2780354B2 (en) | 1989-07-04 | 1998-07-30 | 富士通株式会社 | Semiconductor memory device |
| EP0424612A3 (en) * | 1989-08-30 | 1992-03-11 | International Business Machines Corporation | Apparatus and method for real time data error capture and compression for redundancy analysis of a memory |
| DE4028819A1 (en) | 1990-09-11 | 1992-03-12 | Siemens Ag | CIRCUIT ARRANGEMENT FOR TESTING A SEMICONDUCTOR MEMORY BY MEANS OF PARALLEL TESTS WITH DIFFERENT TEST BIT PATTERNS |
| US5377148A (en) | 1990-11-29 | 1994-12-27 | Case Western Reserve University | Apparatus and method to test random access memories for a plurality of possible types of faults |
| EP0599524A3 (en) | 1992-11-24 | 1996-04-17 | Advanced Micro Devices Inc | Self-test for integrated memory networks. |
| US5467455A (en) * | 1993-11-03 | 1995-11-14 | Motorola, Inc. | Data processing system and method for performing dynamic bus termination |
| US5557619A (en) * | 1994-04-04 | 1996-09-17 | International Business Machines Corporation | Integrated circuits with a processor-based array built-in self test circuit |
| JP3552175B2 (en) * | 1995-05-17 | 2004-08-11 | 株式会社アドバンテスト | Fail memory device |
| TW338159B (en) * | 1996-04-29 | 1998-08-11 | Texas Instruments Inc | Apparatus and method for subarray testing in dynamic random access memories using a built-in-self-test unit |
| GB9623215D0 (en) | 1996-11-07 | 1997-01-08 | Process Insight Limited | Solid state memory test system with defect compression |
| US5961653A (en) * | 1997-02-19 | 1999-10-05 | International Business Machines Corporation | Processor based BIST for an embedded memory |
| US5954830A (en) * | 1997-04-08 | 1999-09-21 | International Business Machines Corporation | Method and apparatus for achieving higher performance data compression in ABIST testing by reducing the number of data outputs |
| US5913928A (en) * | 1997-05-09 | 1999-06-22 | Micron Technology, Inc. | Data compression test mode independent of redundancy |
| JP2982741B2 (en) * | 1997-05-13 | 1999-11-29 | 日本電気株式会社 | Fault diagnosis device for integrated circuit and recording medium therefor |
| US6272588B1 (en) * | 1997-05-30 | 2001-08-07 | Motorola Inc. | Method and apparatus for verifying and characterizing data retention time in a DRAM using built-in test circuitry |
| JP3463543B2 (en) * | 1997-10-29 | 2003-11-05 | 安藤電気株式会社 | Address generation circuit for data compression |
| US6134684A (en) * | 1998-02-25 | 2000-10-17 | International Business Machines Corporation | Method and system for error detection in test units utilizing pseudo-random data |
| US6067262A (en) * | 1998-12-11 | 2000-05-23 | Lsi Logic Corporation | Redundancy analysis for embedded memories with built-in self test and built-in self repair |
-
2000
- 2000-03-09 US US09/522,279 patent/US6421794B1/en not_active Expired - Lifetime
-
2001
- 2001-03-09 WO PCT/US2001/007598 patent/WO2001067463A1/en not_active Ceased
- 2001-03-09 AU AU2001243540A patent/AU2001243540A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| US6421794B1 (en) | 2002-07-16 |
| WO2001067463A1 (en) | 2001-09-13 |
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