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AU2001240082A1 - Tiled graphics architecture - Google Patents

Tiled graphics architecture

Info

Publication number
AU2001240082A1
AU2001240082A1 AU2001240082A AU4008201A AU2001240082A1 AU 2001240082 A1 AU2001240082 A1 AU 2001240082A1 AU 2001240082 A AU2001240082 A AU 2001240082A AU 4008201 A AU4008201 A AU 4008201A AU 2001240082 A1 AU2001240082 A1 AU 2001240082A1
Authority
AU
Australia
Prior art keywords
blit
primitives
bins
operations
sorted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001240082A
Inventor
Hsieh-Cheng Hsieh
Vladimir Pentkovski
Hsin-Chu Tsai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001240082A1 publication Critical patent/AU2001240082A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T11/00—2D [Two Dimensional] image generation
    • G06T11/40—Filling a planar surface by adding surface attributes, e.g. colour or texture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Graphics (AREA)
  • Image Generation (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Walking Sticks, Umbrellas, And Fans (AREA)

Abstract

A method for processing 2D operations in a tiled graphics architecture is disclosed. A graphics controller processes both 3D primitives and 2D blit operations. The 3D primitives are sorted into bins using well-known techniques. When a 2D blit operation is to be processed, the 2D blit operation is also sorted into bins. The sorted 3D primitives and sorted 2D blit operations are then delivered to blit and rendering engines on a bin-by-bin basis. By sorting the 2D blit operations into bins along with the 3D primitives, there is no need to flush the bins (send primitives to rendering engines) whenever a 2D blit operation requires processing. The sorting of 2D blit operations into bins reduces the frequency of graphics cache misses and improves graphics memory bandwidth utilization, thereby improving overall computer system performance.
AU2001240082A 2000-03-31 2001-03-06 Tiled graphics architecture Abandoned AU2001240082A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/540,615 US6819321B1 (en) 2000-03-31 2000-03-31 Method and apparatus for processing 2D operations in a tiled graphics architecture
US09540615 2000-03-31
PCT/US2001/007218 WO2001075803A1 (en) 2000-03-31 2001-03-06 Tiled graphics architecture

Publications (1)

Publication Number Publication Date
AU2001240082A1 true AU2001240082A1 (en) 2001-10-15

Family

ID=24156223

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001240082A Abandoned AU2001240082A1 (en) 2000-03-31 2001-03-06 Tiled graphics architecture

Country Status (11)

Country Link
US (1) US6819321B1 (en)
EP (1) EP1269417B1 (en)
JP (1) JP4719399B2 (en)
KR (1) KR100560088B1 (en)
CN (2) CN1421022A (en)
AT (1) ATE450843T1 (en)
AU (1) AU2001240082A1 (en)
DE (1) DE60140661D1 (en)
HK (1) HK1049724B (en)
TW (1) TW561422B (en)
WO (1) WO2001075803A1 (en)

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US8139058B2 (en) * 2006-11-03 2012-03-20 Vivante Corporation Hierarchical tile-based rasterization algorithm
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US9965886B2 (en) 2006-12-04 2018-05-08 Arm Norway As Method of and apparatus for processing graphics
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GB0900700D0 (en) * 2009-01-15 2009-03-04 Advanced Risc Mach Ltd Methods of and apparatus for processing graphics
KR100927128B1 (en) * 2009-04-30 2009-11-18 주식회사 넥서스칩스 3D graphic processing apparatus and processing method using tile dirty table
KR101683556B1 (en) * 2010-01-06 2016-12-08 삼성전자주식회사 Apparatus and method for tile-based rendering
GB201004673D0 (en) * 2010-03-19 2010-05-05 Imagination Tech Ltd Processing of 3D computer graphics data on multiple shading engines
WO2011161723A1 (en) 2010-06-24 2011-12-29 富士通株式会社 Drawing device and drawing method
US9342322B2 (en) 2011-09-12 2016-05-17 Microsoft Technology Licensing, Llc System and method for layering using tile-based renderers
KR101953133B1 (en) 2012-02-27 2019-05-22 삼성전자주식회사 Apparatus and method for rendering
JP5910310B2 (en) 2012-05-22 2016-04-27 富士通株式会社 Drawing processing apparatus and drawing processing method
US9317948B2 (en) 2012-11-16 2016-04-19 Arm Limited Method of and apparatus for processing graphics
US10204391B2 (en) 2013-06-04 2019-02-12 Arm Limited Method of and apparatus for processing graphics
GB2526598B (en) * 2014-05-29 2018-11-28 Imagination Tech Ltd Allocation of primitives to primitive blocks
GB2537659B (en) * 2015-04-22 2019-05-01 Imagination Tech Ltd Tiling a primitive in a graphics processing system
GB2537661B (en) 2015-04-22 2018-09-26 Imagination Tech Ltd Tiling a primitive in a graphics processing system
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CN106345118B (en) * 2016-08-24 2019-07-30 网易（杭州）网络有限公司 A kind of rendering method and device
US10970118B2 (en) 2017-08-02 2021-04-06 Advanced Micro Devices, Inc. Shareable FPGA compute engine
US11422812B2 (en) 2019-06-25 2022-08-23 Advanced Micro Devices, Inc. Method and apparatus for efficient programmable instructions in computer systems
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Also Published As

Publication number Publication date
KR20030005251A (en) 2003-01-17
TW561422B (en) 2003-11-11
EP1269417B1 (en) 2009-12-02
WO2001075803A1 (en) 2001-10-11
CN1421022A (en) 2003-05-28
US6819321B1 (en) 2004-11-16
DE60140661D1 (en) 2010-01-14
HK1049724B (en) 2010-07-16
CN103106640B (en) 2016-11-02
JP4719399B2 (en) 2011-07-06
HK1049724A1 (en) 2003-05-23
CN103106640A (en) 2013-05-15
JP2003529859A (en) 2003-10-07
ATE450843T1 (en) 2009-12-15
EP1269417A1 (en) 2003-01-02
KR100560088B1 (en) 2006-03-10

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