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AU1203692A - Novel transaction system architecture - Google Patents

Novel transaction system architecture

Info

Publication number
AU1203692A
AU1203692A AU12036/92A AU1203692A AU1203692A AU 1203692 A AU1203692 A AU 1203692A AU 12036/92 A AU12036/92 A AU 12036/92A AU 1203692 A AU1203692 A AU 1203692A AU 1203692 A AU1203692 A AU 1203692A
Authority
AU
Australia
Prior art keywords
system architecture
transaction system
novel transaction
novel
architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU12036/92A
Inventor
Gordon Paul Eckley Jr.
Jeffrey Paul Hill
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Verifone Inc
Original Assignee
Verifone Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Verifone Inc filed Critical Verifone Inc
Publication of AU1203692A publication Critical patent/AU1203692A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer And Data Communications (AREA)
AU12036/92A 1991-01-09 1992-01-09 Novel transaction system architecture Abandoned AU1203692A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US63958491A 1991-01-09 1991-01-09
US639584 2000-08-14

Publications (1)

Publication Number Publication Date
AU1203692A true AU1203692A (en) 1992-08-17

Family

ID=24564718

Family Applications (1)

Application Number Title Priority Date Filing Date
AU12036/92A Abandoned AU1203692A (en) 1991-01-09 1992-01-09 Novel transaction system architecture

Country Status (2)

Country Link
AU (1) AU1203692A (en)
WO (1) WO1992012486A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110990319B (en) * 2019-11-28 2021-07-20 北京雷石天地电子技术有限公司 Synchronous serial bus multiplexing method, apparatus, terminal and non-transitory computer-readable storage medium

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4263650B1 (en) * 1974-10-30 1994-11-29 Motorola Inc Digital data processing system with interface adaptor having programmable monitorable control register therein
US4617642A (en) * 1982-05-06 1986-10-14 Data General Corporation Select switch responsive to a break code
US4807109A (en) * 1983-11-25 1989-02-21 Intel Corporation High speed synchronous/asynchronous local bus and data transfer method
US4773005A (en) * 1984-09-07 1988-09-20 Tektronix, Inc. Dynamic address assignment system
US4868832A (en) * 1986-04-30 1989-09-19 Marrington S Paul Computer power system
US4943707A (en) * 1987-01-06 1990-07-24 Visa International Service Association Transaction approval system
JPS63254585A (en) * 1987-04-13 1988-10-21 Toshiba Corp Data processing method

Also Published As

Publication number Publication date
WO1992012486A1 (en) 1992-07-23

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