AU1097901A - Method for implementing a multi-level system model for deterministically handling selected data - Google Patents

Method for implementing a multi-level system model for deterministically handling selected data

Info

Publication number: AU1097901A
Authority: AU; Australia
Prior art keywords: deterministically; implementing; selected data; system model; level system
Prior art date: 1999-10-21
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Abandoned

Application number

AU10979/01A

Inventor

Bruce A. Fairman

Harold A. Ludtke

Scott D. Smyers

Glen D Stone

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Sony Electronics Inc

Original Assignee

Sony Electronics Inc

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1999-10-21

Filing date

2000-10-18

Publication date

2001-04-30

2000-10-18 Application filed by Sony Electronics Inc filed Critical Sony Electronics Inc

2001-04-30 Publication of AU1097901A publication Critical patent/AU1097901A/en

Status Abandoned legal-status Critical Current

Classifications

- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Landscapes

Engineering & Computer Science (AREA)
Software Systems (AREA)
Theoretical Computer Science (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Hardware Redundancy (AREA)
Accessory Devices And Overall Control Thereof (AREA)
Small-Scale Networks (AREA)

AU10979/01A 1999-10-21 2000-10-18 Method for implementing a multi-level system model for deterministically handling selected data Abandoned AU1097901A (en)

Applications Claiming Priority (5)

Application Number	Priority Date	Filing Date	Title
US16121999P	1999-10-21	1999-10-21
US16120699P	1999-10-21	1999-10-21
US60161219		1999-10-21
US60161206		1999-10-21
PCT/US2000/029043 WO2001029655A2 (en)	1999-10-21	2000-10-18	Method for implementing a multi-level system model for deterministically handling selected data

Publications (1)

Publication Number	Publication Date
AU1097901A true AU1097901A (en)	2001-04-30

Family

ID=26857615

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
AU10979/01A Abandoned AU1097901A (en)	1999-10-21	2000-10-18	Method for implementing a multi-level system model for deterministically handling selected data

Country Status (3)

Country	Link
AU (1)	AU1097901A (en)
TW (1)	TW480438B (en)
WO (1)	WO2001029655A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US6891822B1 (en) *	2000-09-08	2005-05-10	Sharewave, Inc.	Method and apparatus for transferring isocronous data within a wireless computer network

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5487170A (en) *	1993-12-16	1996-01-23	International Business Machines Corporation	Data processing system having dynamic priority task scheduling capabilities
US5758105A (en) *	1995-12-04	1998-05-26	International Business Machines Corporation	Method and apparatus for bus arbitration between isochronous and non-isochronous devices
US5812844A (en) *	1995-12-07	1998-09-22	Microsoft Corporation	Method and system for scheduling the execution of threads using optional time-specific scheduling constraints
US5928321A (en) *	1997-05-30	1999-07-27	Sony Corporation	Task and stack manager for digital video decoding

2000
- 2000-10-18 TW TW89121843A patent/TW480438B/en not_active IP Right Cessation
- 2000-10-18 AU AU10979/01A patent/AU1097901A/en not_active Abandoned
- 2000-10-18 WO PCT/US2000/029043 patent/WO2001029655A2/en not_active Ceased

Also Published As

Publication number	Publication date
WO2001029655A3 (en)	2002-02-14
TW480438B (en)	2002-03-21
WO2001029655A2 (en)	2001-04-26

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Legal Events

Date	Code	Title	Description
2002-06-20	MK6	Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase