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AR003888A1 - Metodo y aparato para el circuito de interfaz entre conductores pares de doble finalidad en medios de velocidad multiple de una red - Google Patents

Metodo y aparato para el circuito de interfaz entre conductores pares de doble finalidad en medios de velocidad multiple de una red

Info

Publication number
AR003888A1
AR003888A1 ARP960104749A ARP960104749A AR003888A1 AR 003888 A1 AR003888 A1 AR 003888A1 AR P960104749 A ARP960104749 A AR P960104749A AR P960104749 A ARP960104749 A AR P960104749A AR 003888 A1 AR003888 A1 AR 003888A1
Authority
AR
Argentina
Prior art keywords
network
interface circuit
multiple speed
speed means
double purpose
Prior art date
Application number
ARP960104749A
Other languages
English (en)
Original Assignee
3Com Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3Com Corp filed Critical 3Com Corp
Publication of AR003888A1 publication Critical patent/AR003888A1/es

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/4013—Management of data rate on the bus
    • H04L12/40136—Nodes adapting their rate to the physical link properties
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/323—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the physical layer [OSI layer 1]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Dc Digital Transmission (AREA)
  • Bidirectional Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Small-Scale Networks (AREA)

Abstract

Se proporciona un método y un aparato que permiten conectar un adaptador de red de doble velocidad al mismo conector físico, sin el uso deconmutadores mecánicos ni electromecánicos. En la vía de transmisión, la invención utiliza unseparado r de amplificador diferencial (130) para acoplarselectivamente una vía de transmisión de alta velocidad a la red, con el amplificador diferencial conectado a la misma impedancia de salida de uno delos dos circuitos del controlador.En la vía d e recepción, la invención permite que los datos sean recibidos en paralelo por los dos circuitos del receptor,con un circuito aislado del otro mediante un par de seguidores de emisor (40, 50) de muy alta impedancia de entrada.
ARP960104749A 1995-10-18 1996-10-15 Metodo y aparato para el circuito de interfaz entre conductores pares de doble finalidad en medios de velocidad multiple de una red AR003888A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/544,745 US5715287A (en) 1995-10-18 1995-10-18 Method and apparatus for dual purpose twisted pair interface circuit for multiple speed media in a network

Publications (1)

Publication Number Publication Date
AR003888A1 true AR003888A1 (es) 1998-09-09

Family

ID=24173418

Family Applications (1)

Application Number Title Priority Date Filing Date
ARP960104749A AR003888A1 (es) 1995-10-18 1996-10-15 Metodo y aparato para el circuito de interfaz entre conductores pares de doble finalidad en medios de velocidad multiple de una red

Country Status (5)

Country Link
US (1) US5715287A (es)
AR (1) AR003888A1 (es)
AU (1) AU7516896A (es)
CO (1) CO4520176A1 (es)
WO (1) WO1997015123A1 (es)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5896417A (en) * 1996-10-25 1999-04-20 National Semiconductor Corporation Apparatus utilizing current-to-voltage conversion for transmitting data at different data transfer rates especially in applications such as dual-rate ethernet local-area networks
US6014409A (en) * 1997-02-05 2000-01-11 Cabletron Systems, Inc. Passive analog filter for network interface
TW454124B (en) * 1997-11-28 2001-09-11 Accton Technology Corp Network stack with automatic switch device for the switch
WO1999053627A1 (en) 1998-04-10 1999-10-21 Chrimar Systems, Inc. Doing Business As Cms Technologies System for communicating with electronic equipment on a network
US6938040B2 (en) 1998-04-28 2005-08-30 International Business Machines Corporation Pattern matching in communications network where first memory stores set of patterns, and second memory stores mask data identifying patterns in the first memory
US5953345A (en) * 1998-06-02 1999-09-14 Cisco Technology, Inc. Reduced pin-count 10Base-T MAC to transceiver interface
US7031333B1 (en) 1998-06-02 2006-04-18 Cisco Technology, Inc. Reduced pin count media independent interface
US6385208B1 (en) * 1998-06-02 2002-05-07 Cisco Technology, Inc. Serial media independent interface
TW433648U (en) * 1998-06-04 2001-05-01 Molex Inc Electrical converter module
US6393457B1 (en) 1998-07-13 2002-05-21 International Business Machines Corporation Architecture and apparatus for implementing 100 Mbps and GBPS Ethernet adapters
US6243426B1 (en) * 1998-09-30 2001-06-05 Advanced Micro Devices, Inc. Apparatus and method for slew rate control of MLT-3 transmitter using zero drive
JP2005086662A (ja) * 2003-09-10 2005-03-31 Seiko Epson Corp 半導体装置
US20070162662A1 (en) * 2005-12-23 2007-07-12 Duggan Brian J Methods and apparatuses for dynamically switching network protocols for use in a printing device
JP5082329B2 (ja) * 2006-08-10 2012-11-28 富士電機株式会社 Ｄｃ−ｄｃコンバータ
EP3499807B1 (en) 2017-12-12 2020-06-03 Nxp B.V. Reconfigurable ethernet receiver and an analog front-end circuit thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5249183A (en) * 1991-03-14 1993-09-28 Level One Communications, Inc. Interfacing unit for local area networks
AU2344192A (en) * 1991-07-17 1993-02-23 Tutankhamon Electronics Network monitor and test apparatus
US5541957A (en) * 1994-06-15 1996-07-30 National Semiconductor Corporation Apparatus for transmitting and/or receiving data at different data transfer rates especially in applications such as dual-rate ethernet local-area networks

Also Published As

Publication number Publication date
CO4520176A1 (es) 1997-10-15
AU7516896A (en) 1997-05-07
US5715287A (en) 1998-02-03
WO1997015123A1 (en) 1997-04-24

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